diff --git a/EVT/CH32V20x_List.txt b/EVT/CH32V20x_List.txt index 6dfe479..2c8e32f 100644 --- a/EVT/CH32V20x_List.txt +++ b/EVT/CH32V20x_List.txt @@ -1,5 +1,5 @@ -南京沁恒微电子股份有限公司 2023.10 +南京沁恒微电子股份有限公司 2024.02 最新资料请到我们的网站上查询 https://wch.cn @@ -36,6 +36,8 @@ https://wch.cn | | | | |-- DualADC_SlowInterleaved：双ADC慢速交叉采样例程 ——仅适用于CH32V20x_D6 | | | | |-- ExtLines_Trigger：外部触发ADC转换例程 | | | | |-- Internal_Temperature：内部温度传感器例程 + | | | | |-- Temperature_External_channel：温度传感器_外部通道交替注入例程 + | | | | |-- TIM_trigger：定时器触发ADC转换例程 | | | |-- APPLICATION | | | | |-- USBPD | | | | | |-- I2C_OP_CH223：通过I2C操作CH223例程 ——仅适用于CH32V20x_D8 @@ -86,14 +88,14 @@ https://wch.cn | | | | | |-- adv_ali_light_multi_element：多元素天猫精灵风扇灯例程。同时包含风扇开关摇头和灯开关颜色控制。用于对照原天猫精灵灯例程，快速熟悉添加多个属性的方法。 | | | | | |-- adv_ali_light_with_peripheral：天猫精灵灯例程的基础上，添加亮度和色温控制，并支持手机BLE调试助手连接控制。 | | | | | |-- adv_proxy：代理节点例程，可通过PB_GATT层（BLE连接）进行配网。 - | | | | | |-- adv_vendor：厂商自定义模型例程，配合self_provisioner_vendor使用，支持有应答传输和无应答透传两种通信属性，自行拟定通信协议。 + | | | | | |-- adv_vendor：厂商自定义模型例程，配合provisioner_vendor使用，支持有应答传输和无应答透传两种通信属性，自行拟定通信协议。 | | | | | |-- adv_vendor_friend：厂商自定义模型例程的基础上，支持朋友节点功能 | | | | | |-- adv_vendor_low_power：厂商自定义模型例程的基础上，支持低功耗节点功能，需与朋友节点配合使用 | | | | | |-- adv_vendor_self_provision：厂商自定义模型例程的基础上，支持本地自配网，适配无配网者或简化配网流程等特殊应用场景 | | | | | |-- adv_vendor_self_provision_IAP：MESH备份无线升级IAP例程，检测当前代码标志，判断是否搬运备份区代码到用户区并运行用户区代码 | | | | | |-- adv_vendor_self_provision_with_peripheral：MESH备份无线升级用户例程，厂商自定义模型例程的基础上，支持手机BLE调试助手连接控制，通过BLE接收配网信息并将自身配网，适用于终端控制组网应用，可自行拟定通信协议实现手机控制mesh网络中所有设备。 - | | | | | |-- self_provisioner_vendor：厂商自定义模型自配网发起者例程，配合adv_vendor使用，自动配网周围未配网设备，并将其加入自身mesh网络，默认支持配网6个设备。默认配置设备绑定1个APPKEY,用于有应答传输和无应答透传，配置设备绑定1个订阅地址，用于群发无应答消息 - | | | | | |-- self_provisioner_vendor_with_peripheral：厂商自定义模型自配网发起者例程的基础上，支持手机BLE调试助手连接控制，中转手机与mesh网络的通信，可自行拟定通信协议实现手机控制mesh网络中所有设备。 + | | | | | |-- provisioner_vendor：厂商自定义模型自配网发起者例程，配合adv_vendor使用，自动配网周围未配网设备，并将其加入自身mesh网络，默认支持配网6个设备。默认配置设备绑定1个APPKEY,用于有应答传输和无应答透传，配置设备绑定1个订阅地址，用于群发无应答消息 + | | | | | |-- provisioner_vendor_with_peripheral：厂商自定义模型自配网发起者例程的基础上，支持手机BLE调试助手连接控制，中转手机与mesh网络的通信，可自行拟定通信协议实现手机控制mesh网络中所有设备。 | | | | | |-- MESH_LIB：MESH协议栈库文件及其头文件 | | | | | |-- 沁恒MESH APP管理配网应用手册.pdf | | | | | |-- 沁恒低功耗蓝牙MESH软件开发参考手册.pdf @@ -155,14 +157,21 @@ https://wch.cn | | | | |-- Stop_Mode：低功耗，停机模式例程 | | | | |-- Standby_RAM_LV_Mode：待机模式开启LV时，RAM 2K、30K低功耗数据保持例程 | | | | |-- Standby_RAM_Mode：待机模式不开启LV时，RAM 2K、30K低功耗数据保持例程 + | | | | |-- PVD_Wakeup：STOP模式PVD中断唤醒例程 + | | | | |-- PVD_VoltageJudger：PVD电压判定例程 + | | | |-- PMP + | | | | |-- PMP：物理内存保护例程 | | | |-- RCC | | | | |-- Get_CLK：获取system-HCLK-AHB1-AHB2时钟例程 | | | | |-- MCO：MCO引脚时钟输出例程 | | | | |-- HSI_PLL_Source：HSI或HSI/2作为PLL输入时钟例程 + | | | | |-- HSI_Calibration：HSI校准例程 + | | | | |-- HSE_CLK：检查HSE频率例程 | | | |-- RT-Thread | | | | |-- RT_Thread_Core：RT-Thread移植例程 | | | |-- RTC | | | | |-- RTC_Calendar：日历例程 + | | | | |-- RTC_Calibration：RTC校准例程 | | | |-- SPI | | | | |-- 1Lines_half-duplex：单线半双工模式，Master/Slave 模式数据收发 | | | | |-- 2Lines_FullDuplex：双线全双工模式，Master/Slave 模式数据收发 @@ -188,6 +197,7 @@ https://wch.cn | | | | |-- Synchro_ExtTrigger：从模式例程，包括复位模式、门控模式、触发模式 | | | | |-- Synchro_Timer：定时器同步模式 | | | | |-- TIM_DMA：定时器使用DMA例程 + | | | | |-- Encoder：定时器编码器例程 | | | |-- TOUCHKEY | | | | |-- TKey：TouchKey检测例程 | | | |-- USART diff --git a/EVT/CH32V20x_List_EN.txt b/EVT/CH32V20x_List_EN.txt index 67f124f..e995dbc 100644 --- a/EVT/CH32V20x_List_EN.txt +++ b/EVT/CH32V20x_List_EN.txt @@ -1,5 +1,5 @@ -Nanjing Qinheng Microelectronics Co., Ltd. 2023.09 +Nanjing Qinheng Microelectronics Co., Ltd. 2024.02 https://wch-ic.com @@ -35,6 +35,8 @@ Directory | | | | |-- DualADC_SlowInterleaved: dual ADC slow interleaved sampling routine, only applied to CH32V20x_D6 | | | | |-- ExtLines_Trigger: external lines trigger ADC conversion routine | | | | |-- Internal_Temperature: internal temperature sensor routine + | | | | |-- TIM_Trigger:TIM trigger ADC conversion routine + | | | | |-- Temperature_External_channel:Temperature External channel Injection alternating inversion routine | | | |-- APPLICATION | | | | |-- USBPD | | | | | |-- I2C_OP_CH223锛欼2C Operates CH223 routine, only applied to CH32V20x_D8 @@ -85,14 +87,14 @@ Directory | | | | | |-- adv_ali_light_multi_element: Multi-element fan lamp, which is used to compare the original Tmall Genie light routine to quickly become familiar with the method of adding multi-element Tmall definition attributes. | | | | | |-- adv_ali_light_with_peripheral: Based on the Tmall Genie light routine, add brightness and color temperature controls, it supports the connection control of BLE debugging tool on the mobile phone. | | | | | |-- adv_proxy: proxy node routine, which can be used to provision network through the PV_GATT layer (BLE connection). - | | | | | |-- adv_vendor: vendor-defined model routine, used with self_provisioner_vendor, supports two communication attributes of response transmission and non-response transparent transmission, and develops the communication protocol by yourself. + | | | | | |-- adv_vendor: vendor-defined model routine, used with provisioner_vendor, supports two communication attributes of response transmission and non-response transparent transmission, and develops the communication protocol by yourself. | | | | | |-- adv_vendor_friend: based on vendor-defined model routine, support friend node function | | | | | |-- adv_vendor_low_power: On the basis of the vendor custom model routine, support low-power node functions and should be used with friend nodes | | | | | |-- adv_vendor_self_provision: On the basis of the vendor custom model routine, support local provision | | | | | |-- adv_vendor_self_provision_IAP:MESH backup wireless upgrade IAP routine, detect the current code flag, judge whether to move the backup area code to the user area and run the user area code | | | | | |-- adv_vendor_self_provision_with_peripheral: MESH backup wireless upgrade user routine, On the basis of the vendor custom model routine, supports the connection control of the mobile phone BLE debugging assistant, receives the distribution network information through BLE and distributes the network itself. It is suitable for terminal control networking applications. It can formulate the communication protocol by itself to realize the mobile phone control all devices in the mesh network. - | | | | | |-- self_provisioner_vendor: vendor-defined model self-provisioning network initiator routine, used with adv_vendor, automatically provision network to the surrounding devices without network, and add it to its own mesh network, support provision network to six devices by default . The default configuration device is bound with single APPKEY, which is used for response transmission and non-response transparent transmission, and the configuration device is bound with single subscription address, which is used for mass sending of unanswered messages - | | | | | |-- self_provisioner_vendor_with_peripheral: Based on the vendor-defined model self-provisioning network initiator routine, can be connected and controlled by BLE debugging tool on the mobile phone, transfer the communication between the mobile phone and the mesh network, and can draw up the communication protocol to implement that all devices in mesh network can be controlled the mobile phone. + | | | | | |-- provisioner_vendor: vendor-defined model self-provisioning network initiator routine, used with adv_vendor, automatically provision network to the surrounding devices without network, and add it to its own mesh network, support provision network to six devices by default . The default configuration device is bound with single APPKEY, which is used for response transmission and non-response transparent transmission, and the configuration device is bound with single subscription address, which is used for mass sending of unanswered messages + | | | | | |-- provisioner_vendor_with_peripheral: Based on the vendor-defined model self-provisioning network initiator routine, can be connected and controlled by BLE debugging tool on the mobile phone, transfer the communication between the mobile phone and the mesh network, and can draw up the communication protocol to implement that all devices in mesh network can be controlled the mobile phone. | | | | | |-- MESH_LIB: MESH protocol stack library file and header file | | | | | |-- Qinheng MESH APP Management Distribution Network Application Manual.pdf | | | | | |-- Qinheng Low Energy Bluetooth MESH Software Development Reference Manual.pdf @@ -154,14 +156,21 @@ Directory | | | | |-- Stop_Mode: low power, stop mode routine | | | | |-- Standby_RAM_LV_Mode: when LV is enabled in standby mode, RAM 2k and 30K low-power data holding routines | | | | |-- Standby_RAM_Mode:when LV is not enabled in standby mode, RAM 2k and 30K low-power data holding routines + | | | | |-- PVD_Wakeup锛歋TOP mode PVD wakeup MCU Routine + | | | | |-- PVD_VoltageJudger锛歅VD voltage Judger Routine + | | | |-- PMP + | | | | |-- PMP锛歅hysical memory protection Routine | | | |-- RCC | | | | |-- Get_CLK:Get system-HCLK-AHB1-AHB2 clock routine | | | | |-- MCO: MCO pin clock output routine | | | | |-- HSI_PLL_Source:HSI or HSI/2 as PLL input clock routine + | | | | |-- HSI_Calibration锛欻SI calibrate routine + | | | | |-- HSE_CLK:HSE frequency check routine | | | |-- RT-Thread | | | | |-- RT_Thread_Core:RT-Thread migration routine | | | |-- RTC | | | | |-- RTC_Calendar:Calendar Routines + | | | | |-- RTC_Calibration锛歊TC calibrate Routines | | | |-- SPI | | | | |-- 1Lines_half-duplex: single wire half duplex mode, master/slave mode, data transceiver | | | | |-- 2Lines_FullDuplex: two-wire full duplex mode, master/slave mode, data transceiver @@ -187,6 +196,7 @@ Directory | | | | |-- Synchro_ExtTrigger:slave mode routine, including reset mode, gating mode and trigger mode | | | | |-- Synchro_Timer:timer synchronization mode | | | | |-- TIM_DMA: timer DMA routines + | | | | |-- Encode:Timer encoder mode routines | | | |-- TOUCHKEY | | | | |-- TKey:TouchKey Detection Routine | | | |-- USART diff --git a/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c b/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c index 5a6fdbc..2bff14d 100644 --- a/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } diff --git a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c b/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c index f28b306..bd24a08 100644 --- a/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void ADC1_2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/main.c b/EVT/EXAM/ADC/AnalogWatchdog/User/main.c index 17c0d5e..4cee515 100644 --- a/EVT/EXAM/ADC/AnalogWatchdog/User/main.c +++ b/EVT/EXAM/ADC/AnalogWatchdog/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -58,7 +58,7 @@ void ADC_Function_Init(void) ADC_AnalogWatchdogCmd(ADC1, ADC_AnalogWatchdog_SingleRegEnable); NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); @@ -124,7 +124,7 @@ int main(void) { u16 ADC_val; - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); SystemCoreClockUpdate(); Delay_Init(); USART_Printf_Init(115200); diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c b/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c index 37a03a8..e5cb1c5 100644 --- a/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -22,6 +22,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/Auto_Injection/User/main.c b/EVT/EXAM/ADC/Auto_Injection/User/main.c index a226c06..2722fce 100644 --- a/EVT/EXAM/ADC/Auto_Injection/User/main.c +++ b/EVT/EXAM/ADC/Auto_Injection/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. diff --git a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c b/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c index 5a6fdbc..2bff14d 100644 --- a/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c index 5a6fdbc..2bff14d 100644 --- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c index 321c46e..795b370 100644 --- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c +++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -147,7 +147,7 @@ void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsiz DMA_Init(DMA_CHx, &DMA_InitStructure); NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c index 46a5ccd..823a02b 100644 --- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c +++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -54,7 +54,7 @@ void ADC_Function_Init(void) ADC_DeInit(ADC2); NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c index d3853a6..2adfd96 100644 --- a/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c +++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -125,7 +125,7 @@ void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsiz DMA_Init(DMA_CHx, &DMA_InitStructure); NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c index eef2acf..4acf1c3 100644 --- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c +++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -55,7 +55,7 @@ void ADC_Function_Init(void) ADC_DeInit(ADC2); NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c index ee9cd5d..7e07e5f 100644 --- a/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c index 4102332..76a299e 100644 --- a/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c +++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -60,7 +60,7 @@ void ADC_Function_Init(void) ADC_ExternalTrigInjectedConvCmd(ADC1, ENABLE); NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c b/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/ADC/TIM_Trigger/.cproject b/EVT/EXAM/ADC/TIM_Trigger/.cproject new file mode 100644 index 0000000..d094d90 --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/.cproject @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EVT/EXAM/ADC/TIM_Trigger/.project b/EVT/EXAM/ADC/TIM_Trigger/.project new file mode 100644 index 0000000..ea3dc4e --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/.project @@ -0,0 +1,61 @@ + + + TIM_Trigger + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + + + Core + 2 + PARENT-2-PROJECT_LOC/SRC/Core + + + Debug + 2 + PARENT-2-PROJECT_LOC/SRC/Debug + + + Ld + 2 + PARENT-2-PROJECT_LOC/SRC/Ld + + + Peripheral + 2 + PARENT-2-PROJECT_LOC/SRC/Peripheral + + + Startup + 2 + PARENT-2-PROJECT_LOC/SRC/Startup + + + diff --git a/EVT/EXAM/ADC/TIM_Trigger/.template b/EVT/EXAM/ADC/TIM_Trigger/.template new file mode 100644 index 0000000..7a6625c --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/.template @@ -0,0 +1,17 @@ +Mcu Type=CH32V20x +Address=0x08000000 +Target Path=obj\TIM_Trigger.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32V203 +Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. + +PeripheralVersion=1.0 +MCU=CH32V203RBT6 +CLKSpeed=1 diff --git a/EVT/EXAM/ADC/TIM_Trigger/TIM_Trigger.wvproj b/EVT/EXAM/ADC/TIM_Trigger/TIM_Trigger.wvproj new file mode 100644 index 0000000..2cd99d9 --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/TIM_Trigger.wvproj @@ -0,0 +1,2 @@ +iCZ ?"莵竢焷F<.勄趴?/O┠緾hQN$*籈Bk!2t+buh唍Ub]xl媗| ++"<摨AH42}z8p;mu1-h籓d聎氮7x{5丆qEx=;Βe⒑2 偒*BP M" \ No newline at end of file diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h new file mode 100644 index 0000000..6142fd8 --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h @@ -0,0 +1,40 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Library configuration file. + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ +#ifndef __CH32V20x_CONF_H +#define __CH32V20x_CONF_H + +#include "ch32v20x_adc.h" +#include "ch32v20x_bkp.h" +#include "ch32v20x_can.h" +#include "ch32v20x_crc.h" +#include "ch32v20x_dbgmcu.h" +#include "ch32v20x_dma.h" +#include "ch32v20x_exti.h" +#include "ch32v20x_flash.h" +#include "ch32v20x_gpio.h" +#include "ch32v20x_i2c.h" +#include "ch32v20x_iwdg.h" +#include "ch32v20x_pwr.h" +#include "ch32v20x_rcc.h" +#include "ch32v20x_rtc.h" +#include "ch32v20x_spi.h" +#include "ch32v20x_tim.h" +#include "ch32v20x_usart.h" +#include "ch32v20x_wwdg.h" +#include "ch32v20x_it.h" +#include "ch32v20x_misc.h" + + +#endif /* __CH32V20x_CONF_H */ + + + + + diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c new file mode 100644 index 0000000..13c75eb --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c @@ -0,0 +1,45 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/29 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h new file mode 100644 index 0000000..eaac7e0 --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h @@ -0,0 +1,18 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains the headers of the interrupt handlers. + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ +#ifndef __CH32V20x_IT_H +#define __CH32V20x_IT_H + +#include "debug.h" + + +#endif /* __CH32V20x_IT_H */ + + diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/main.c b/EVT/EXAM/ADC/TIM_Trigger/User/main.c new file mode 100644 index 0000000..ddbe399 --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/User/main.c @@ -0,0 +1,209 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : main.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Main program body. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +/* + *@Note + *TIM trigger ADC conversion routine: + *ADC channel 1 (PA1) - injection group channel, TIM2 CH1 pin (PA0) TIM trigger, + *In this mode, an ADC conversion is triggered by an event on TIM2 CH1 TIM trigger, and a JEOC interrupt is generated after + *the conversion is completed. + * + */ + + +#include "debug.h" + +/* Global Variable */ +s16 Calibrattion_Val = 0; + +/********************************************************************* + * @fn ADC_Function_Init + * + * @brief Initializes ADC collection. + * + * @return none + */ +void ADC_Function_Init(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + GPIO_InitTypeDef GPIO_InitStructure = {0}; + NVIC_InitTypeDef NVIC_InitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_ADCCLKConfig(RCC_PCLK2_Div8); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + ADC_DeInit(ADC1); + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigInjecConv_T1_CC4|ADC_ExternalTrigConv_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfChannel = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_InjectedSequencerLengthConfig(ADC1, 1); + ADC_InjectedChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_7Cycles5); + ADC_ExternalTrigInjectedConvCmd(ADC1, ENABLE); + + NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE); + ADC_Cmd(ADC1, ENABLE); + + ADC_BufferCmd(ADC1, DISABLE); //disable buffer + ADC_ResetCalibration(ADC1); + while(ADC_GetResetCalibrationStatus(ADC1)); + ADC_StartCalibration(ADC1); + while(ADC_GetCalibrationStatus(ADC1)); + Calibrattion_Val = Get_CalibrationValue(ADC1); + +// ADC_BufferCmd(ADC1, ENABLE); //enable buffer +} + +u16 Get_ADC_Val(u8 ch) +{ + u16 val; + + ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_7Cycles5); + ADC_SoftwareStartConvCmd(ADC1, ENABLE); + + while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)); + val = ADC_GetConversionValue(ADC1); + + return val; +} + +void GPIO_Toggle_INIT(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +} +/********************************************************************* + * @fn TIM1_PWM_In + * + * @brief Initializes PWM. + * + * @return none + */ + +void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + TIM_OCInitTypeDef TIM_OCInitStructure = {0}; + TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA| RCC_APB2Periph_TIM1, ENABLE); +// RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + TIM_TimeBaseInitStructure.TIM_Period = arr; + TIM_TimeBaseInitStructure.TIM_Prescaler = psc; + TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseInitStructure); + + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = ccp; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OC4Init(TIM1, &TIM_OCInitStructure); + + TIM_CtrlPWMOutputs(TIM1, ENABLE); + TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Disable); + TIM_ARRPreloadConfig(TIM1, ENABLE); + TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update); + TIM_Cmd(TIM1, ENABLE); +} +/********************************************************************* + * @fn Get_ConversionVal1 + * + * @brief Get Conversion Value. + * + * @param val - Sampling value + * + * @return val+Calibrattion_Val - Conversion Value. + */ +u16 Get_ConversionVal(s16 val) +{ + if((val + Calibrattion_Val) < 0) + return 0; + if((Calibrattion_Val + val) > 4095 || val==4095) + return 4095; + return (val + Calibrattion_Val); +} + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) +{ + SystemCoreClockUpdate(); + USART_Printf_Init(115200); + printf("SystemClk:%d\r\n", SystemCoreClock); + GPIO_Toggle_INIT(); + ADC_Function_Init(); + printf("CalibrattionValue:%d\n", Calibrattion_Val); + TIM1_PWM_In(7200,100-1,3600); + + while(1); +} + +void ADC1_2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn ADC1_2_IRQHandler + * + * @brief ADC1_2 Interrupt Service Function. + * + * @return none + */ +void ADC1_2_IRQHandler() +{ + u16 ADC_val,ADC; + + if(ADC_GetITStatus(ADC1, ADC_IT_JEOC)) + { +// printf("ADC Extline trigger conversion...\r\n"); + ADC_val = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_1); + ADC= Get_ADC_Val(ADC_Channel_5); + printf("%04d %04d\r\n",ADC_val ,ADC); + } + + ADC_ClearITPendingBit(ADC1, ADC_IT_JEOC); +} diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c new file mode 100644 index 0000000..a804336 --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c @@ -0,0 +1,986 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Source File. + * For HSE = 32Mhz (CH32V208x/CH32V203RBT6) + * For HSE = 8Mhz (other CH32V203x) +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE( void ); +#elif defined SYSCLK_FREQ_144MHz_HSE +static void SetSysClockTo144_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI( void ); +#elif defined SYSCLK_FREQ_144MHz_HSI +static void SetSysClockTo144_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#if defined (CH32V20x_D8W) + if((RCC->CFGR0 & (3<<22)) == (3<<22)) + { + SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull; +#else + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; +#endif + } + else + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = (HSE_VALUE>>2) * pllmull; +#else + SystemCoreClock = HSE_VALUE * pllmull; +#endif + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source + * CH32V20x_D6 (HSE=8MHZ) + * CH32V20x_D8 (HSE=32MHZ) + * CH32V20x_D8W (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { +#if defined (CH32V20x_D8W) + RCC->CFGR0 |= (uint32_t)(3<<22); + /* HCLK = SYSCLK/2 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; +#else + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +#endif + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#endif diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.h b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.h new file mode 100644 index 0000000..aec0f3f --- /dev/null +++ b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.h @@ -0,0 +1,29 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32v20x_H +#define __SYSTEM_ch32v20x_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V20x_SYSTEM_H */ diff --git a/EVT/EXAM/ADC/Temperature_External_channel/.cproject b/EVT/EXAM/ADC/Temperature_External_channel/.cproject new file mode 100644 index 0000000..d094d90 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/.cproject @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EVT/EXAM/ADC/Temperature_External_channel/.project b/EVT/EXAM/ADC/Temperature_External_channel/.project new file mode 100644 index 0000000..95df473 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/.project @@ -0,0 +1,61 @@ + + + Temperature_External_channel + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + + + Core + 2 + PARENT-2-PROJECT_LOC/SRC/Core + + + Debug + 2 + PARENT-2-PROJECT_LOC/SRC/Debug + + + Ld + 2 + PARENT-2-PROJECT_LOC/SRC/Ld + + + Peripheral + 2 + PARENT-2-PROJECT_LOC/SRC/Peripheral + + + Startup + 2 + PARENT-2-PROJECT_LOC/SRC/Startup + + + diff --git a/EVT/EXAM/ADC/Temperature_External_channel/.template b/EVT/EXAM/ADC/Temperature_External_channel/.template new file mode 100644 index 0000000..873c596 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/.template @@ -0,0 +1,17 @@ +Mcu Type=CH32V20x +Address=0x08000000 +Target Path=obj\Temperature_External_channel.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32V203 +Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. + +PeripheralVersion=1.0 +MCU=CH32V203RBT6 +CLKSpeed=1 diff --git a/EVT/EXAM/ADC/Temperature_External_channel/Temperature_External_channel.wvproj b/EVT/EXAM/ADC/Temperature_External_channel/Temperature_External_channel.wvproj new file mode 100644 index 0000000..2cd99d9 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/Temperature_External_channel.wvproj @@ -0,0 +1,2 @@ +iCZ ?"莵竢焷F<.勄趴?/O┠緾hQN$*籈Bk!2t+buh唍Ub]xl媗| ++"<摨AH42}z8p;mu1-h籓d聎氮7x{5丆qEx=;Βe⒑2 偒*BP M" \ No newline at end of file diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h new file mode 100644 index 0000000..6142fd8 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h @@ -0,0 +1,40 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Library configuration file. + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ +#ifndef __CH32V20x_CONF_H +#define __CH32V20x_CONF_H + +#include "ch32v20x_adc.h" +#include "ch32v20x_bkp.h" +#include "ch32v20x_can.h" +#include "ch32v20x_crc.h" +#include "ch32v20x_dbgmcu.h" +#include "ch32v20x_dma.h" +#include "ch32v20x_exti.h" +#include "ch32v20x_flash.h" +#include "ch32v20x_gpio.h" +#include "ch32v20x_i2c.h" +#include "ch32v20x_iwdg.h" +#include "ch32v20x_pwr.h" +#include "ch32v20x_rcc.h" +#include "ch32v20x_rtc.h" +#include "ch32v20x_spi.h" +#include "ch32v20x_tim.h" +#include "ch32v20x_usart.h" +#include "ch32v20x_wwdg.h" +#include "ch32v20x_it.h" +#include "ch32v20x_misc.h" + + +#endif /* __CH32V20x_CONF_H */ + + + + + diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c new file mode 100644 index 0000000..13c75eb --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c @@ -0,0 +1,45 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2023/12/29 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h new file mode 100644 index 0000000..eaac7e0 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h @@ -0,0 +1,18 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains the headers of the interrupt handlers. + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ +#ifndef __CH32V20x_IT_H +#define __CH32V20x_IT_H + +#include "debug.h" + + +#endif /* __CH32V20x_IT_H */ + + diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/main.c b/EVT/EXAM/ADC/Temperature_External_channel/User/main.c new file mode 100644 index 0000000..f079892 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/main.c @@ -0,0 +1,159 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : main.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Main program body. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +/* + *@Note + *Temperature-External channel Injection alternating inversion routine: + *Temperature inversion then External channel inversion + * + */ + +#include "debug.h" + +s16 Calibrattion_Val = 0; + +/********************************************************************* + * @fn ADC_Function_Init + * + * @brief Initializes ADC collection. + * + * @return none + */ +void ADC_Function_Init(void) +{ + ADC_InitTypeDef ADC_InitStructure = {0}; + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_ADCCLKConfig(RCC_PCLK2_Div8); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + ADC_DeInit(ADC1); + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfChannel = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_Cmd(ADC1, ENABLE); + + ADC_BufferCmd(ADC1, DISABLE); //disable buffer + ADC_ResetCalibration(ADC1); + while(ADC_GetResetCalibrationStatus(ADC1)); + ADC_StartCalibration(ADC1); + while(ADC_GetCalibrationStatus(ADC1)); + Calibrattion_Val = Get_CalibrationValue(ADC1); + + ADC_TempSensorVrefintCmd(ENABLE); + +} + +/********************************************************************* + * @fn Get_ADC_Val + * + * @brief Returns ADCx conversion result data. + * + * @param ch - ADC channel. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return none + */ +u16 Get_ADC_Val(u8 ch) +{ + u16 val; + ADC_RegularChannelConfig( ADC1, ch, 1, ADC_SampleTime_239Cycles5 ); + ADC_SoftwareStartConvCmd(ADC1, ENABLE); + + while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC)); + + val = ADC_GetConversionValue(ADC1); + + return val; +} + +/********************************************************************* + * @fn Get_ConversionVal + * + * @brief Get Conversion Value. + * + * @param val - Sampling value + * + * @return val+Calibrattion_Val - Conversion Value. + */ +u16 Get_ConversionVal(s16 val) +{ + if((val + Calibrattion_Val) < 0) + return 0; + if((Calibrattion_Val + val) > 4095||val==4095) + return 4095; + return (val + Calibrattion_Val); +} + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) +{ + u16 adc_val,val_mv; + SystemCoreClockUpdate(); + Delay_Init(); + USART_Printf_Init(115200); + printf("SystemClk:%d\r\n", SystemCoreClock); + + ADC_Function_Init(); + printf("CalibrattionValue:%d\n", Calibrattion_Val); + + while(1) + { + adc_val = Get_ConversionVal(Get_ADC_Val(ADC_Channel_TempSensor)); + val_mv = (adc_val*3300/4096); + printf("mv-T-%d,%0d\n",val_mv ,TempSensor_Volt_To_Temper(val_mv)); + ADC_TempSensorVrefintCmd(DISABLE); + + adc_val = Get_ConversionVal(Get_ADC_Val(ADC_Channel_3)); + Delay_Us(80); + printf("ADC_val %04d\r\n",adc_val); + Delay_Ms(2); + ADC_TempSensorVrefintCmd(ENABLE); + Delay_Ms(500); + } +} + + + diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c new file mode 100644 index 0000000..37730a5 --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c @@ -0,0 +1,986 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Source File. + * For HSE = 32Mhz (CH32V208x/CH32V203RBT6) + * For HSE = 8Mhz (other CH32V203x) +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +//#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE( void ); +#elif defined SYSCLK_FREQ_144MHz_HSE +static void SetSysClockTo144_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI( void ); +#elif defined SYSCLK_FREQ_144MHz_HSI +static void SetSysClockTo144_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#if defined (CH32V20x_D8W) + if((RCC->CFGR0 & (3<<22)) == (3<<22)) + { + SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull; +#else + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; +#endif + } + else + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = (HSE_VALUE>>2) * pllmull; +#else + SystemCoreClock = HSE_VALUE * pllmull; +#endif + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source + * CH32V20x_D6 (HSE=8MHZ) + * CH32V20x_D8 (HSE=32MHZ) + * CH32V20x_D8W (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { +#if defined (CH32V20x_D8W) + RCC->CFGR0 |= (uint32_t)(3<<22); + /* HCLK = SYSCLK/2 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; +#else + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +#endif + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#endif diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.h b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.h new file mode 100644 index 0000000..aec0f3f --- /dev/null +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.h @@ -0,0 +1,29 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32v20x_H +#define __SYSTEM_ch32v20x_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V20x_SYSTEM_H */ diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c index f2598c2..13c75eb 100644 --- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c +++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c index 429a433..4ed544e 100644 --- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c +++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2023/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd. @@ -236,7 +236,7 @@ int main(void) u16 n = 0; u8 tempV = 0, tempI = 0, tempV0 = 0, tempI0 = 0, tempVmax = 0; u8 res = 0, ndo_select = 0, STATE_flag = 0; - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); Delay_Init(); USART_Printf_Init( 115200 ); CH223_Init(); diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c +++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c index ea6d338..ec99e9d 100644 --- a/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c +++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c index 6bcefe9..18625cd 100644 --- a/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c +++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -491,7 +491,7 @@ void led_example_2(void) int main(void) { uint16_t i = 0; - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); Delay_Init(); USART_Printf_Init(115200); printf("SystemClk:%d\r\n", SystemCoreClock); diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c +++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c b/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c index 9b35e0f..2dc80df 100644 --- a/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c +++ b/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_it.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main Interrupt Service Routines. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -24,6 +24,9 @@ void TAMPER_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void NMI_Handler(void) { + while (1) + { + } } /********************************************************************* diff --git a/EVT/EXAM/BKP/BKP/User/main.c b/EVT/EXAM/BKP/BKP/User/main.c index 16692d5..15fbb29 100644 --- a/EVT/EXAM/BKP/BKP/User/main.c +++ b/EVT/EXAM/BKP/BKP/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2023/12/29 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -70,7 +70,7 @@ void BKP_Tamper_Init(void) int main(void) { SystemCoreClockUpdate(); - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); USART_Printf_Init(115200); printf("SystemClk:%d\r\n", SystemCoreClock); printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() ); diff --git a/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c index 8d3a568..0de9dce 100644 --- a/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c +++ b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/BLE_UART/APP/peripheral.c b/EVT/EXAM/BLE/BLE_UART/APP/peripheral.c index e2307d0..dbd8377 100644 --- a/EVT/EXAM/BLE/BLE_UART/APP/peripheral.c +++ b/EVT/EXAM/BLE/BLE_UART/APP/peripheral.c @@ -207,9 +207,6 @@ void Peripheral_Init() GAPRole_SetParameter(GAPROLE_MAX_CONN_INTERVAL, sizeof(uint16_t), &desired_max_interval); } - // Set the GAP Characteristics - GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); - // Set advertising interval { uint16_t advInt = DEFAULT_ADVERTISING_INTERVAL; @@ -238,6 +235,9 @@ void Peripheral_Init() DevInfo_AddService(); // Device Information Service ble_uart_add_service(on_bleuartServiceEvt); + // Set the GAP Characteristics + GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); + // Init Connection Item peripheralInitConnItem(&peripheralConnList); diff --git a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbotg_device.c b/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c similarity index 64% rename from EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbotg_device.c rename to EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c index a178923..ed27840 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbotg_device.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c @@ -1,15 +1,15 @@ /********************************** (C) COPYRIGHT ******************************* - * File Name : ch32v30x_usbotg_device.c + * File Name : ch32v30x_usbfs_device.c * Author : WCH * Version : V1.0.0 * Date : 2021/06/06 - * Description : This file provides all the USBOTG firmware functions. + * Description : This file provides all the USBFS firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Attention: This software (modified or not) and binary are used for * microcontroller manufactured by Nanjing Qinheng Microelectronics. *******************************************************************************/ -#include "ch32v20x_usbotg_device.h" +#include "ch32v20x_usbfs_device.h" #include "CONFIG.h" #include "peripheral.h" #include "RingMem.h" @@ -46,27 +46,27 @@ PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64) PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64) const UINT8 *pDescr; -volatile UINT8 USBHD_Dev_SetupReqCode = 0xFF; /* USB2.0 full-speed device setup package command */ -volatile UINT16 USBHD_Dev_SetupReqLen = 0x00; /* USB2.0 full-speed device setup package length */ -volatile UINT8 USBHD_Dev_SetupReqValueH = 0x00; /* USB2.0 full-speed device setup package value high byte */ -volatile UINT8 USBHD_Dev_Config = 0x00; /* USB2.0 full-speed device configuration value */ -volatile UINT8 USBHD_Dev_Address = 0x00; /* USB2.0 full-speed device address value */ -volatile UINT8 USBHD_Dev_SleepStatus = 0x00; /* USB2.0 full-speed device sleep state */ -volatile UINT8 USBHD_Dev_EnumStatus = 0x00; /* USB2.0 full-speed device enumeration status */ -volatile UINT8 USBHD_Dev_Endp0_Tog = 0x01; /* USB2.0 Full-speed device endpoint 0 sync flag*/ -volatile UINT8 USBHD_Dev_Speed = 0x01; /* USB2.0 Full-speed device speed */ +volatile UINT8 USBFS_Dev_SetupReqCode = 0xFF; /* USB2.0 full-speed device setup package command */ +volatile UINT16 USBFS_Dev_SetupReqLen = 0x00; /* USB2.0 full-speed device setup package length */ +volatile UINT8 USBFS_Dev_SetupReqValueH = 0x00; /* USB2.0 full-speed device setup package value high byte */ +volatile UINT8 USBFS_Dev_Config = 0x00; /* USB2.0 full-speed device configuration value */ +volatile UINT8 USBFS_Dev_Address = 0x00; /* USB2.0 full-speed device address value */ +volatile UINT8 USBFS_Dev_SleepStatus = 0x00; /* USB2.0 full-speed device sleep state */ +volatile UINT8 USBFS_Dev_EnumStatus = 0x00; /* USB2.0 full-speed device enumeration status */ +volatile UINT8 USBFS_Dev_Endp0_Tog = 0x01; /* USB2.0 Full-speed device endpoint 0 sync flag*/ +volatile UINT8 USBFS_Dev_Speed = 0x01; /* USB2.0 Full-speed device speed */ -volatile UINT16 USBHD_Endp1_Up_Flag = 0x00; /* USB2.0 full-speed device endpoint 1 data upload status: 0: free; 1: upload; */ -volatile UINT8 USBHD_Endp1_Down_Flag = 0x00; /* USB2.0 full-speed device endpoint 1 Pass successful logo */ -volatile UINT8 USBHD_Endp1_Down_Len = 0x00; /* USB2.0 full-speed device endpoint 1 download length */ -volatile BOOL USBHD_Endp1_T_Tog = 0; /* USB2.0 full speed device endpoint 1 sends tog bit flip */ -volatile BOOL USBHD_Endp1_R_Tog = 0; +volatile UINT16 USBFS_Endp1_Up_Flag = 0x00; /* USB2.0 full-speed device endpoint 1 data upload status: 0: free; 1: upload; */ +volatile UINT8 USBFS_Endp1_Down_Flag = 0x00; /* USB2.0 full-speed device endpoint 1 Pass successful logo */ +volatile UINT8 USBFS_Endp1_Down_Len = 0x00; /* USB2.0 full-speed device endpoint 1 download length */ +volatile BOOL USBFS_Endp1_T_Tog = 0; /* USB2.0 full speed device endpoint 1 sends tog bit flip */ +volatile BOOL USBFS_Endp1_R_Tog = 0; -volatile UINT16 USBHD_Endp2_Up_Flag = 0x00; /* USB2.0 full-speed device endpoint 2 Data upload status: 0: free; 1: upload; */ -volatile UINT16 USBHD_Endp2_Up_LoadPtr = 0x00; /* USB2.0 full-speed device endpoint 2 Data upload loading offset */ -volatile UINT8 USBHD_Endp2_Down_Flag = 0x00; /* USB2.0 full-speed device endpoint 2 download success flag */ -volatile BOOL USBHD_Endp2_T_Tog = 0; /* USB2.0 full speed device endpoint 2 sends tog bit flip */ -volatile BOOL USBHD_Endp2_R_Tog = 0; +volatile UINT16 USBFS_Endp2_Up_Flag = 0x00; /* USB2.0 full-speed device endpoint 2 Data upload status: 0: free; 1: upload; */ +volatile UINT16 USBFS_Endp2_Up_LoadPtr = 0x00; /* USB2.0 full-speed device endpoint 2 Data upload loading offset */ +volatile UINT8 USBFS_Endp2_Down_Flag = 0x00; /* USB2.0 full-speed device endpoint 2 download success flag */ +volatile BOOL USBFS_Endp2_T_Tog = 0; /* USB2.0 full speed device endpoint 2 sends tog bit flip */ +volatile BOOL USBFS_Endp2_R_Tog = 0; volatile UINT32V Endp2_send_seq = 0x00; volatile UINT8 DevConfig; @@ -117,10 +117,10 @@ const uint8_t Return1[2] = {0x31, 0x00}; const uint8_t Return2[2] = {0xC3, 0x00}; const uint8_t Return3[2] = {0x9F, 0xEE}; -void USBHD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); /********************************************************************* - * @fn USBOTG_FS_DeviceInit + * @fn USBDeviceInit * * @brief Initializes USB device. * @@ -128,78 +128,78 @@ void USBHD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void USBDeviceInit(void) { - USBOTG_FS->BASE_CTRL = 0x00; + USBFSD->BASE_CTRL = 0x00; - USBOTG_FS->UEP4_1_MOD = USBHD_UEP4_RX_EN | USBHD_UEP4_TX_EN | USBHD_UEP1_RX_EN | USBHD_UEP1_TX_EN; - USBOTG_FS->UEP2_3_MOD = USBHD_UEP2_RX_EN | USBHD_UEP2_TX_EN | USBHD_UEP3_RX_EN | USBHD_UEP3_TX_EN; - USBOTG_FS->UEP5_6_MOD = USBHD_UEP5_RX_EN | USBHD_UEP5_TX_EN | USBHD_UEP6_RX_EN | USBHD_UEP6_TX_EN; - USBOTG_FS->UEP7_MOD = USBHD_UEP7_RX_EN | USBHD_UEP7_TX_EN; + USBFSD->UEP4_1_MOD = USBFS_UEP4_RX_EN | USBFS_UEP4_TX_EN | USBFS_UEP1_RX_EN | USBFS_UEP1_TX_EN; + USBFSD->UEP2_3_MOD = USBFS_UEP2_RX_EN | USBFS_UEP2_TX_EN | USBFS_UEP3_RX_EN | USBFS_UEP3_TX_EN; + USBFSD->UEP5_6_MOD = USBFS_UEP5_RX_EN | USBFS_UEP5_TX_EN | USBFS_UEP6_RX_EN | USBFS_UEP6_TX_EN; + USBFSD->UEP7_MOD = USBFS_UEP7_RX_EN | USBFS_UEP7_TX_EN; - USBOTG_FS->UEP0_DMA = (UINT32)pEP0_RAM_Addr; - USBOTG_FS->UEP1_DMA = (UINT32)pEP1_RAM_Addr; - USBOTG_FS->UEP2_DMA = (UINT32)pEP2_RAM_Addr; - USBOTG_FS->UEP3_DMA = (UINT32)pEP3_RAM_Addr; - USBOTG_FS->UEP4_DMA = (UINT32)pEP4_RAM_Addr; - USBOTG_FS->UEP5_DMA = (UINT32)pEP5_RAM_Addr; - USBOTG_FS->UEP6_DMA = (UINT32)pEP6_RAM_Addr; - USBOTG_FS->UEP7_DMA = (UINT32)pEP7_RAM_Addr; + USBFSD->UEP0_DMA = (UINT32)pEP0_RAM_Addr; + USBFSD->UEP1_DMA = (UINT32)pEP1_RAM_Addr; + USBFSD->UEP2_DMA = (UINT32)pEP2_RAM_Addr; + USBFSD->UEP3_DMA = (UINT32)pEP3_RAM_Addr; + USBFSD->UEP4_DMA = (UINT32)pEP4_RAM_Addr; + USBFSD->UEP5_DMA = (UINT32)pEP5_RAM_Addr; + USBFSD->UEP6_DMA = (UINT32)pEP6_RAM_Addr; + USBFSD->UEP7_DMA = (UINT32)pEP7_RAM_Addr; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP3_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP4_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP5_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP6_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP7_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP1_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP3_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP4_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP5_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP6_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP7_RX_CTRL = USBFS_UEP_R_RES_ACK; - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP1_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP2_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP3_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP4_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP5_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP6_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP7_TX_LEN = RepDataLoadLen; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP1_TX_LEN = RepDataLoadLen; + USBFSD->UEP2_TX_LEN = RepDataLoadLen; + USBFSD->UEP3_TX_LEN = RepDataLoadLen; + USBFSD->UEP4_TX_LEN = RepDataLoadLen; + USBFSD->UEP5_TX_LEN = RepDataLoadLen; + USBFSD->UEP6_TX_LEN = RepDataLoadLen; + USBFSD->UEP7_TX_LEN = RepDataLoadLen; - USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_ACK; - USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_ACK | USBHD_UEP_AUTO_TOG; - USBOTG_FS->UEP3_TX_CTRL = USBHD_UEP_T_RES_ACK | USBHD_UEP_AUTO_TOG; - USBOTG_FS->UEP4_TX_CTRL = USBHD_UEP_T_RES_ACK | USBHD_UEP_AUTO_TOG; - USBOTG_FS->UEP5_TX_CTRL = USBHD_UEP_T_RES_ACK | USBHD_UEP_AUTO_TOG; - USBOTG_FS->UEP6_TX_CTRL = USBHD_UEP_T_RES_ACK | USBHD_UEP_AUTO_TOG; - USBOTG_FS->UEP7_TX_CTRL = USBHD_UEP_T_RES_ACK | USBHD_UEP_AUTO_TOG; + USBFSD->UEP1_TX_CTRL = USBFS_UEP_T_RES_ACK; + USBFSD->UEP2_TX_CTRL = USBFS_UEP_T_RES_ACK | USBFS_UEP_AUTO_TOG; + USBFSD->UEP3_TX_CTRL = USBFS_UEP_T_RES_ACK | USBFS_UEP_AUTO_TOG; + USBFSD->UEP4_TX_CTRL = USBFS_UEP_T_RES_ACK | USBFS_UEP_AUTO_TOG; + USBFSD->UEP5_TX_CTRL = USBFS_UEP_T_RES_ACK | USBFS_UEP_AUTO_TOG; + USBFSD->UEP6_TX_CTRL = USBFS_UEP_T_RES_ACK | USBFS_UEP_AUTO_TOG; + USBFSD->UEP7_TX_CTRL = USBFS_UEP_T_RES_ACK | USBFS_UEP_AUTO_TOG; - USBOTG_FS->INT_FG = 0xFF; - USBOTG_FS->INT_EN = USBHD_UIE_SUSPEND | USBHD_UIE_BUS_RST | USBHD_UIE_TRANSFER; - USBOTG_FS->DEV_ADDR = 0x00; + USBFSD->INT_FG = 0xFF; + USBFSD->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER; + USBFSD->DEV_ADDR = 0x00; - USBOTG_FS->BASE_CTRL = USBHD_UC_DEV_PU_EN | USBHD_UC_INT_BUSY | USBHD_UC_DMA_EN; - USBOTG_FS->UDEV_CTRL = USBHD_UD_PD_DIS | USBHD_UD_PORT_EN; + USBFSD->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; + USBFSD->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN; } /********************************************************************* - * @fn USBOTG_RCC_Init + * @fn USBFS_RCC_Init * - * @brief Initializes the usbotg clock configuration. + * @brief Initializes the usbfs clock configuration. * * @return none */ -void USBOTG_RCC_Init(void) +void USBFS_RCC_Init(void) { - RCC->CFGR2 &= ~RCC_USBFS_CLK_SRC; //usbotg clock selection: 0 = systick, 1 = usb20_phy + RCC->CFGR2 &= ~RCC_USBFS_CLK_SRC; //usbfs clock selection: 0 = systick, 1 = usb20_phy RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div2); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE); } /********************************************************************* - * @fn USBOTG_Init + * @fn USBFS_Init * - * @brief Initializes the USBOTG full speed device. + * @brief Initializes the USBFS full speed device. * * @return none */ -void USBOTG_Init(void) +void USBFS_Init(void) { /* Endpoint buffer initialization */ pEP0_RAM_Addr = EP0_DatabufHD; @@ -211,37 +211,37 @@ void USBOTG_Init(void) pEP6_RAM_Addr = EP6_DatabufHD; pEP7_RAM_Addr = EP7_DatabufHD; /* Enable USB clock */ - USBOTG_RCC_Init(); + USBFS_RCC_Init(); Delay_Us(100); /* USB device initialization */ USBDeviceInit(); /* Enable USB interrupt */ - NVIC_EnableIRQ(USBHD_IRQn); + NVIC_EnableIRQ(USBFS_IRQn); } /********************************************************************* - * @fn USBHD_IRQHandler + * @fn USBFS_IRQHandler * - * @brief This function handles OTG_FS exception. + * @brief This function handles HD-FS exception. * * @return none */ -void USBHD_IRQHandler(void) +void USBFS_IRQHandler(void) { UINT8 len, chtype; UINT8 intflag, errflag = 0; - intflag = USBOTG_FS->INT_FG; + intflag = USBFSD->INT_FG; - if(intflag & USBHD_UIF_TRANSFER) + if(intflag & USBFS_UIF_TRANSFER) { - switch(USBOTG_FS->INT_ST & USBHD_UIS_TOKEN_MASK) + switch(USBFSD->INT_ST & USBFS_UIS_TOKEN_MASK) { /* Setup package processing */ - case USBHD_UIS_TOKEN_SETUP: + case USBFS_UIS_TOKEN_SETUP: - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG | USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG | USBHD_UEP_R_RES_ACK; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_NAK; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK; SetupReqLen = pSetupReqPakHD->wLength; SetupReqCode = pSetupReqPakHD->bRequest; chtype = pSetupReqPakHD->bRequestType; @@ -380,19 +380,19 @@ void USBHD_IRQHandler(void) switch((pSetupReqPakHD->wIndex) & 0xff) { case 0x82: - USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK; + USBFSD->UEP2_TX_CTRL = (USBFSD->UEP2_TX_CTRL & ~(USBFS_UEP_T_TOG | USBFS_UEP_T_RES_MASK)) | USBFS_UEP_T_RES_NAK; break; case 0x02: - USBOTG_FS->UEP2_RX_CTRL = (USBOTG_FS->UEP2_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK; + USBFSD->UEP2_RX_CTRL = (USBFSD->UEP2_RX_CTRL & ~(USBFS_UEP_R_TOG | USBFS_UEP_R_RES_MASK)) | USBFS_UEP_R_RES_ACK; break; case 0x81: - USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK; + USBFSD->UEP1_TX_CTRL = (USBFSD->UEP1_TX_CTRL & ~(USBFS_UEP_T_TOG | USBFS_UEP_T_RES_MASK)) | USBFS_UEP_T_RES_NAK; break; case 0x01: - USBOTG_FS->UEP1_RX_CTRL = (USBOTG_FS->UEP1_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK; + USBFSD->UEP1_RX_CTRL = (USBFSD->UEP1_RX_CTRL & ~(USBFS_UEP_R_TOG | USBFS_UEP_R_RES_MASK)) | USBFS_UEP_R_RES_ACK; break; default: @@ -414,7 +414,7 @@ void USBHD_IRQHandler(void) if(MyCfgDescrHD[7] & 0x20) { /* Set wake-up enable flag */ - USBHD_Dev_SleepStatus = 0x01; + USBFS_Dev_SleepStatus = 0x01; } else { @@ -436,25 +436,25 @@ void USBHD_IRQHandler(void) { case 0x82: /* Set endpoint 2 IN STALL */ - USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL; + USBFSD->UEP2_TX_CTRL = (USBFSD->UEP2_TX_CTRL &= ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_STALL; //USBHS->UEP2_CTRL = ( USBHS->UEP2_CTRL & ~USBHS_EP_T_RES_MASK ) | USBHS_EP_T_RES_STALL; break; case 0x02: /* Set endpoint 2 OUT Stall */ - USBOTG_FS->UEP2_RX_CTRL = (USBOTG_FS->UEP2_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL; + USBFSD->UEP2_RX_CTRL = (USBFSD->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_STALL; //USBHS->UEP2_CTRL = ( USBHS->UEP2_CTRL & ~USBHS_EP_R_RES_MASK ) | USBHS_EP_R_RES_STALL; break; case 0x81: /* Set endpoint 1 IN STALL */ - USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL; + USBFSD->UEP1_TX_CTRL = (USBFSD->UEP1_TX_CTRL &= ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_STALL; //USBHS->UEP1_CTRL = ( USBHS->UEP1_CTRL & ~USBHS_EP_T_RES_MASK ) | USBHS_EP_T_RES_STALL; break; case 0x01: /* Set endpoint 1 OUT STALL */ - USBOTG_FS->UEP1_RX_CTRL = (USBOTG_FS->UEP1_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL; + USBFSD->UEP1_RX_CTRL = (USBFSD->UEP1_RX_CTRL &= ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_STALL; //USBHS->UEP1_CTRL = ( USBHS->UEP1_CTRL & ~USBHS_EP_R_RES_MASK ) | USBHS_EP_R_RES_STALL; break; @@ -484,9 +484,9 @@ void USBHD_IRQHandler(void) case USB_SET_INTERFACE: /* Set interface */ EP0_DatabufHD[0] = 0x00; - if(USBHD_Dev_SetupReqLen > 1) + if(USBFS_Dev_SetupReqLen > 1) { - USBHD_Dev_SetupReqLen = 1; + USBFS_Dev_SetupReqLen = 1; } break; @@ -496,35 +496,35 @@ void USBHD_IRQHandler(void) EP0_DatabufHD[1] = 0x00; if(pMySetupReqPakHD->wIndex == 0x81) { - if((USBOTG_FS->UEP1_TX_CTRL & USBHD_UEP_T_RES_MASK) == USBHD_UEP_T_RES_STALL) + if((USBFSD->UEP1_TX_CTRL & USBFS_UEP_T_RES_MASK) == USBFS_UEP_T_RES_STALL) { EP0_DatabufHD[0] = 0x01; } } else if(pMySetupReqPakHD->wIndex == 0x01) { - if((USBOTG_FS->UEP1_RX_CTRL & USBHD_UEP_R_RES_MASK) == USBHD_UEP_R_RES_STALL) + if((USBFSD->UEP1_RX_CTRL & USBFS_UEP_R_RES_MASK) == USBFS_UEP_R_RES_STALL) { EP0_DatabufHD[0] = 0x01; } } else if(pMySetupReqPakHD->wIndex == 0x82) { - if((USBOTG_FS->UEP2_TX_CTRL & USBHD_UEP_T_RES_MASK) == USBHD_UEP_T_RES_STALL) + if((USBFSD->UEP2_TX_CTRL & USBFS_UEP_T_RES_MASK) == USBFS_UEP_T_RES_STALL) { EP0_DatabufHD[0] = 0x01; } } else if(pMySetupReqPakHD->wIndex == 0x02) { - if((USBOTG_FS->UEP2_RX_CTRL & USBHD_UEP_R_RES_MASK) == USBHD_UEP_R_RES_STALL) + if((USBFSD->UEP2_RX_CTRL & USBFS_UEP_R_RES_MASK) == USBFS_UEP_R_RES_STALL) { EP0_DatabufHD[0] = 0x01; } } - if(USBHD_Dev_SetupReqLen > 2) + if(USBFS_Dev_SetupReqLen > 2) { - USBHD_Dev_SetupReqLen = 2; + USBFS_Dev_SetupReqLen = 2; } break; @@ -535,8 +535,8 @@ void USBHD_IRQHandler(void) } if(errflag == 0xff) { - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG | USBHD_UEP_T_RES_STALL; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG | USBHD_UEP_R_RES_STALL; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL; } else { @@ -548,16 +548,16 @@ void USBHD_IRQHandler(void) else len = 0; - USBOTG_FS->UEP0_TX_LEN = len; - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG | USBHD_UEP_T_RES_ACK; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG | USBHD_UEP_R_RES_ACK; + USBFSD->UEP0_TX_LEN = len; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK; } break; - case USBHD_UIS_TOKEN_IN: - switch(USBOTG_FS->INT_ST & (USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK)) + case USBFS_UIS_TOKEN_IN: + switch(USBFSD->INT_ST & (USBFS_UIS_TOKEN_MASK | USBFS_UIS_ENDP_MASK)) { - case USBHD_UIS_TOKEN_IN: + case USBFS_UIS_TOKEN_IN: switch(SetupReqCode) { case USB_GET_DESCRIPTOR: @@ -565,58 +565,58 @@ void USBHD_IRQHandler(void) memcpy(pEP0_DataBuf, pDescr, len); SetupReqLen -= len; pDescr += len; - USBOTG_FS->UEP0_TX_LEN = len; - USBOTG_FS->UEP0_TX_CTRL ^= USBHD_UEP_T_TOG; + USBFSD->UEP0_TX_LEN = len; + USBFSD->UEP0_TX_CTRL ^= USBFS_UEP_T_TOG; break; case USB_SET_ADDRESS: - USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR & USBHD_UDA_GP_BIT) | SetupReqLen; - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBFSD->DEV_ADDR = (USBFSD->DEV_ADDR & USBFS_UDA_GP_BIT) | SetupReqLen; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK; break; default: - USBOTG_FS->UEP0_TX_LEN = 0; - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBFSD->UEP0_TX_LEN = 0; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK; break; } break; /* Back to NCK by default */ - case USBHD_UIS_TOKEN_IN | 1: - USBOTG_FS->UEP1_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + case USBFS_UIS_TOKEN_IN | 1: + USBFSD->UEP1_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP1_TX_CTRL = (USBFSD->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; - case USBHD_UIS_TOKEN_IN | 2: + case USBFS_UIS_TOKEN_IN | 2: - USBOTG_FS->UEP2_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + USBFSD->UEP2_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP2_TX_CTRL = (USBFSD->UEP2_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; - case USBHD_UIS_TOKEN_IN | 3: - USBOTG_FS->UEP3_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + case USBFS_UIS_TOKEN_IN | 3: + USBFSD->UEP3_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP3_TX_CTRL = (USBFSD->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; - case USBHD_UIS_TOKEN_IN | 4: - USBOTG_FS->UEP4_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + case USBFS_UIS_TOKEN_IN | 4: + USBFSD->UEP4_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP4_TX_CTRL = (USBFSD->UEP4_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; - case USBHD_UIS_TOKEN_IN | 5: - USBOTG_FS->UEP5_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + case USBFS_UIS_TOKEN_IN | 5: + USBFSD->UEP5_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP5_TX_CTRL = (USBFSD->UEP5_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; - case USBHD_UIS_TOKEN_IN | 6: - USBOTG_FS->UEP6_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + case USBFS_UIS_TOKEN_IN | 6: + USBFSD->UEP6_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP6_TX_CTRL = (USBFSD->UEP6_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; - case USBHD_UIS_TOKEN_IN | 7: - USBOTG_FS->UEP7_TX_CTRL ^= USBHD_UEP_T_TOG; - USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK; + case USBFS_UIS_TOKEN_IN | 7: + USBFSD->UEP7_TX_CTRL ^= USBFS_UEP_T_TOG; + USBFSD->UEP7_TX_CTRL = (USBFSD->UEP7_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK; break; default: @@ -624,116 +624,112 @@ void USBHD_IRQHandler(void) } break; - case USBHD_UIS_TOKEN_OUT: - switch(USBOTG_FS->INT_ST & (USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK)) + case USBFS_UIS_TOKEN_OUT: + switch(USBFSD->INT_ST & (USBFS_UIS_TOKEN_MASK | USBFS_UIS_ENDP_MASK)) { - case USBHD_UIS_TOKEN_OUT: - len = USBOTG_FS->RX_LEN; + case USBFS_UIS_TOKEN_OUT: + len = USBFSD->RX_LEN; break; - case USBHD_UIS_TOKEN_OUT | 1: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 1: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP1_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP1_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP1_OUT_Deal(len); } break; - case USBHD_UIS_TOKEN_OUT | 2: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 2: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP2_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP2_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP2_OUT_Deal(len); } break; - case USBHD_UIS_TOKEN_OUT | 3: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 3: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP3_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP3_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP3_OUT_Deal(len); } break; - case USBHD_UIS_TOKEN_OUT | 4: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 4: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP4_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP4_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP4_OUT_Deal(len); } break; - case USBHD_UIS_TOKEN_OUT | 5: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 5: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP5_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP5_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP5_OUT_Deal(len); } break; - case USBHD_UIS_TOKEN_OUT | 6: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 6: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP6_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP6_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP6_OUT_Deal(len); } break; - case USBHD_UIS_TOKEN_OUT | 7: - if(USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) + case USBFS_UIS_TOKEN_OUT | 7: + if(USBFSD->INT_ST & USBFS_UIS_TOG_OK) { - USBOTG_FS->UEP7_RX_CTRL ^= USBHD_UEP_R_TOG; - len = USBOTG_FS->RX_LEN; + USBFSD->UEP7_RX_CTRL ^= USBFS_UEP_R_TOG; + len = USBFSD->RX_LEN; DevEP7_OUT_Deal(len); } break; } break; - case USBHD_UIS_TOKEN_SOF: - - break; - default: break; } - USBOTG_FS->INT_FG = USBHD_UIF_TRANSFER; + USBFSD->INT_FG = USBFS_UIF_TRANSFER; } - else if(intflag & USBHD_UIF_BUS_RST) + else if(intflag & USBFS_UIF_BUS_RST) { - USBOTG_FS->DEV_ADDR = 0; + USBFSD->DEV_ADDR = 0; - USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP3_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP4_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP5_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP6_RX_CTRL = USBHD_UEP_R_RES_ACK; - USBOTG_FS->UEP7_RX_CTRL = USBHD_UEP_R_RES_ACK; + USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP1_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP3_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP4_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP5_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP6_RX_CTRL = USBFS_UEP_R_RES_ACK; + USBFSD->UEP7_RX_CTRL = USBFS_UEP_R_RES_ACK; - USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP3_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP4_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP5_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP6_TX_CTRL = USBHD_UEP_T_RES_NAK; - USBOTG_FS->UEP7_TX_CTRL = USBHD_UEP_T_RES_NAK; + USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP4_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP5_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP6_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFSD->UEP7_TX_CTRL = USBFS_UEP_T_RES_NAK; - USBOTG_FS->INT_FG |= USBHD_UIF_BUS_RST; + USBFSD->INT_FG |= USBFS_UIF_BUS_RST; } - else if(intflag & USBHD_UIF_SUSPEND) + else if(intflag & USBFS_UIF_SUSPEND) { - if(USBOTG_FS->MIS_ST & USBHD_UMS_SUSPEND) + if(USBFSD->MIS_ST & USBFS_UMS_SUSPEND) { ; } @@ -741,11 +737,11 @@ void USBHD_IRQHandler(void) { ; } - USBOTG_FS->INT_FG = USBHD_UIF_SUSPEND; + USBFSD->INT_FG = USBFS_UIF_SUSPEND; } else { - USBOTG_FS->INT_FG = intflag; + USBFSD->INT_FG = intflag; } } @@ -758,7 +754,7 @@ void USBHD_IRQHandler(void) */ uint8_t USBSendData(void) { - if(USBOTG_FS->UEP2_TX_CTRL & USBHD_UEP_T_RES_MASK == USBHD_UEP_T_RES_ACK) + if(USBFSD->UEP2_TX_CTRL & USBFS_UEP_T_RES_MASK == USBFS_UEP_T_RES_ACK) { return FAILURE; } @@ -787,8 +783,8 @@ uint8_t USBSendData(void) */ void DevEP1_IN_Deal(UINT8 l) { - USBOTG_FS->UEP1_TX_LEN = l; - USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP1_TX_LEN = l; + USBFSD->UEP1_TX_CTRL = (USBFSD->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* @@ -802,8 +798,8 @@ void DevEP1_IN_Deal(UINT8 l) */ void DevEP2_IN_Deal(UINT8 l) { - USBOTG_FS->UEP2_TX_LEN = l; - USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP2_TX_LEN = l; + USBFSD->UEP2_TX_CTRL = (USBFSD->UEP2_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* @@ -817,8 +813,8 @@ void DevEP2_IN_Deal(UINT8 l) */ void DevEP3_IN_Deal(UINT8 l) { - USBOTG_FS->UEP3_TX_LEN = l; - USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP3_TX_LEN = l; + USBFSD->UEP3_TX_CTRL = (USBFSD->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* @@ -832,8 +828,8 @@ void DevEP3_IN_Deal(UINT8 l) */ void DevEP4_IN_Deal(UINT8 l) { - USBOTG_FS->UEP4_TX_LEN = l; - USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP4_TX_LEN = l; + USBFSD->UEP4_TX_CTRL = (USBFSD->UEP4_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* @@ -847,8 +843,8 @@ void DevEP4_IN_Deal(UINT8 l) */ void DevEP5_IN_Deal(UINT8 l) { - USBOTG_FS->UEP5_TX_LEN = l; - USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP5_TX_LEN = l; + USBFSD->UEP5_TX_CTRL = (USBFSD->UEP5_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* @@ -862,8 +858,8 @@ void DevEP5_IN_Deal(UINT8 l) */ void DevEP6_IN_Deal(UINT8 l) { - USBOTG_FS->UEP6_TX_LEN = l; - USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP6_TX_LEN = l; + USBFSD->UEP6_TX_CTRL = (USBFSD->UEP6_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* @@ -877,8 +873,8 @@ void DevEP6_IN_Deal(UINT8 l) */ void DevEP7_IN_Deal(UINT8 l) { - USBOTG_FS->UEP7_TX_LEN = l; - USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK; + USBFSD->UEP7_TX_LEN = l; + USBFSD->UEP7_TX_CTRL = (USBFSD->UEP7_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK; } /********************************************************************* diff --git a/EVT/EXAM/BLE/BLE_USB/APP/include/ch32v20x_usbotg_device.h b/EVT/EXAM/BLE/BLE_USB/APP/include/ch32v20x_usbfs_device.h similarity index 69% rename from EVT/EXAM/BLE/BLE_USB/APP/include/ch32v20x_usbotg_device.h rename to EVT/EXAM/BLE/BLE_USB/APP/include/ch32v20x_usbfs_device.h index ba775ed..1cf359c 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/include/ch32v20x_usbotg_device.h +++ b/EVT/EXAM/BLE/BLE_USB/APP/include/ch32v20x_usbfs_device.h @@ -1,17 +1,17 @@ /********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v20x_usbotg_device.h +* File Name : ch32v20x_usbfs_device.h * Author : WCH * Version : V1.0.0 * Date : 2021/06/06 * Description : This file contains all the functions prototypes for the -* USBOTG firmware library. +* USBFS firmware library. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Attention: This software (modified or not) and binary are used for * microcontroller manufactured by Nanjing Qinheng Microelectronics. *******************************************************************************/ -#ifndef __CH32V20X_USBOTG_DEVICE_H_ -#define __CH32V20X_USBOTG_DEVICE_H_ +#ifndef __CH32V20X_USBFS_DEVICE_H_ +#define __CH32V20X_USBFS_DEVICE_H_ #include "debug.h" #include "string.h" @@ -390,19 +390,19 @@ typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */ /* 控制性宏定义 */ #define USE_SYS_CLK 0 -//#define USBHD_HOST 0 +//#define USBFS_HOST 0 //#define USB_OTG 0 /******************************************************************************/ -/* USBOTG_FS DEVICE USB_CONTROL */ +/* USBFS DEVICE USB_CONTROL */ /* BASE USB_CTRL */ -#define USBHD_BASE_CTRL (USBOTG_FS->BASE_CTRL) // USB base control -#define USBHD_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode -#define USBHD_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps -#define USBHD_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable -#define USBHD_UC_SYS_CTRL1 0x20 // USB system control high bit -#define USBHD_UC_SYS_CTRL0 0x10 // USB system control low bit -#define USBHD_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control +#define USBFS_BASE_CTRL (USBFSD_FS->BASE_CTRL) // USB base control +#define USBFS_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define USBFS_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define USBFS_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define USBFS_UC_SYS_CTRL1 0x20 // USB system control high bit +#define USBFS_UC_SYS_CTRL0 0x10 // USB system control low bit +#define USBFS_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control // UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control // 0 00: disable USB device and disable internal pullup resistance // 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance @@ -411,79 +411,79 @@ typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */ // 1 01: enable USB host and force UDP/UDM output SE0 state // 1 10: enable USB host and force UDP/UDM output J state // 1 11: enable USB host and force UDP/UDM output resume or K state -#define USBHD_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid -#define USBHD_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear -#define USBHD_UC_CLR_ALL 0x02 // force clear FIFO and count of USB -#define USBHD_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB +#define USBFS_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define USBFS_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define USBFS_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define USBFS_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB /* DEVICE USB_CTRL */ -#define USBHD_UDEV_CTRL (USBOTG_FS->UDEV_CTRL) // USB device physical prot control -#define USBHD_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable -#define USBHD_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level -#define USBHD_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level -#define USBHD_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed -#define USBHD_UD_GP_BIT 0x02 // general purpose bit -#define USBHD_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable +#define USBFS_UDEV_CTRL (USBFSD_FS->UDEV_CTRL) // USB device physical prot control +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable /* USB INT EN */ -#define USBHD_INT_EN (USBOTG_FS->INT_EN) // USB interrupt enable -#define USBHD_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode -#define USBHD_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode -#define USBHD_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow -#define USBHD_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode -#define USBHD_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event -#define USBHD_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion -#define USBHD_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode -#define USBHD_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode +#define USBFS_INT_EN (USBFSD_FS->INT_EN) // USB interrupt enable +#define USBFS_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define USBFS_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define USBFS_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define USBFS_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define USBFS_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define USBFS_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define USBFS_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define USBFS_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode /* USB_DEV_ADDR */ -#define USBHD_DEV_ADDR (USBOTG_FS->DEV_ADDR) // USB device address -#define USBHD_UDA_GP_BIT 0x80 // general purpose bit -#define USBHD_USB_ADDR_MASK 0x7F // bit mask for USB device address -/* USBOTG_FS DEVICE USB_STATUS */ +#define USBFS_DEV_ADDR (USBFSD_FS->DEV_ADDR) // USB device address +#define USBFS_UDA_GP_BIT 0x80 // general purpose bit +#define USBFS_USB_ADDR_MASK 0x7F // bit mask for USB device address +/* USBFSD_FS DEVICE USB_STATUS */ /* USB_MIS_ST */ -#define USBHD_MIS_ST (USBOTG_FS->MIS_ST) // USB miscellaneous status -#define USBHD_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status -#define USBHD_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host -#define USBHD_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status -#define USBHD_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) -#define USBHD_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status -#define USBHD_UMS_SUSPEND 0x04 // RO, indicate USB suspend status -#define USBHD_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host -#define USBHD_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host +#define USBFS_MIS_ST (USBFSD_FS->MIS_ST) // USB miscellaneous status +#define USBFS_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define USBFS_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define USBFS_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define USBFS_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define USBFS_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define USBFS_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define USBFS_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host /* USB_INT_FG */ -#define USBHD_INT_FG (USBOTG_FS->INT_FG) // USB interrupt flag -#define USBHD_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received -#define USBHD_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK -#define USBHD_U_SIE_FREE 0x20 // RO, indicate USB SIE free status -#define USBHD_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear -#define USBHD_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear -#define USBHD_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear -#define USBHD_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear -#define USBHD_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear -#define USBHD_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear +#define USBFS_INT_FG (USBFSD_FS->INT_FG) // USB interrupt flag +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear /* USB_INT_ST */ -#define USBHD_INT_ST (USBOTG_FS->INT_ST) // USB interrupt flag -#define USBHD_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode -#define USBHD_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode -#define USBHD_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK -#define USBHD_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode -#define USBHD_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode -#define USBHD_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode -#define USBHD_UIS_TOKEN_OUT 0x00 -#define USBHD_UIS_TOKEN_SOF 0x10 -#define USBHD_UIS_TOKEN_IN 0x20 -#define USBHD_UIS_TOKEN_SETUP 0x30 +#define USBFS_INT_ST (USBFSD_FS->INT_ST) // USB interrupt flag +#define USBFS_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define USBFS_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 // UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode // 00: OUT token PID received // 01: SOF token PID received // 10: IN token PID received // 11: SETUP token PID received -#define USBHD_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode /* USB_RX_LEN */ -#define USBHD_RX_LEN (USBOTG_FS->Rx_Len) // USB receiving length +#define USBFS_RX_LEN (USBFSD_FS->Rx_Len) // USB receiving length /* USB_BUF_MOD */ -#define USBHD_UEP4_1_MOD (USBOTG_FS->UEP4_1_MOD) // endpoint 4/1 mode -#define USBHD_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) -#define USBHD_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) -#define USBHD_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_1_MOD (USBFSD_FS->UEP4_1_MOD) // endpoint 4/1 mode +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 // UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA // 0 0 x: disable endpoint and disable buffer // 1 0 0: 64 bytes buffer for receiving (OUT endpoint) @@ -492,8 +492,8 @@ typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */ // 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes // 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes // 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes -#define USBHD_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) -#define USBHD_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) // UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA // 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) // 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes @@ -501,152 +501,152 @@ typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */ // 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) // + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes -#define USBHD_UEP2_3_MOD (USBOTG_FS->UEP2_3_MOD) // endpoint 2/3 mode -#define USBHD_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) -#define USBHD_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) -#define USBHD_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 -#define USBHD_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) -#define USBHD_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) -#define USBHD_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 +#define USBFS_UEP2_3_MOD (USBFSD_FS->UEP2_3_MOD) // endpoint 2/3 mode +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 -#define USBHD_UEP5_6_MOD (USBOTG_FS->UEP5_6_MOD) // endpoint 5/6 mode -#define USBHD_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) -#define USBHD_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) -#define USBHD_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 -#define USBHD_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) -#define USBHD_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) -#define USBHD_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 +#define USBFS_UEP5_6_MOD (USBFSD_FS->UEP5_6_MOD) // endpoint 5/6 mode +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 -#define USBHD_UEP7_MOD (USBOTG_FS->UEP7_MOD) // endpoint 7 mode -#define USBHD_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) -#define USBHD_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) -#define USBHD_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 +#define USBFS_UEP7_MOD (USBFSD_FS->UEP7_MOD) // endpoint 7 mode +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 /* USB_DMA */ -#define USBHD_UEP0_DMA (USBOTG_FS->UEP0_DMA) // endpoint 0 DMA buffer address -#define USBHD_UEP1_DMA (USBOTG_FS->UEP1_DMA) // endpoint 1 DMA buffer address -#define USBHD_UEP2_DMA (USBOTG_FS->UEP2_DMA) // endpoint 2 DMA buffer address -#define USBHD_UEP3_DMA (USBOTG_FS->UEP3_DMA) // endpoint 3 DMA buffer address -#define USBHD_UEP4_DMA (USBOTG_FS->UEP4_DMA) // endpoint 4 DMA buffer address -#define USBHD_UEP5_DMA (USBOTG_FS->UEP5_DMA) // endpoint 5 DMA buffer address -#define USBHD_UEP6_DMA (USBOTG_FS->UEP6_DMA) // endpoint 6 DMA buffer address -#define USBHD_UEP7_DMA (USBOTG_FS->UEP7_DMA) // endpoint 7 DMA buffer address +#define USBFS_UEP0_DMA (USBFSD_FS->UEP0_DMA) // endpoint 0 DMA buffer address +#define USBFS_UEP1_DMA (USBFSD_FS->UEP1_DMA) // endpoint 1 DMA buffer address +#define USBFS_UEP2_DMA (USBFSD_FS->UEP2_DMA) // endpoint 2 DMA buffer address +#define USBFS_UEP3_DMA (USBFSD_FS->UEP3_DMA) // endpoint 3 DMA buffer address +#define USBFS_UEP4_DMA (USBFSD_FS->UEP4_DMA) // endpoint 4 DMA buffer address +#define USBFS_UEP5_DMA (USBFSD_FS->UEP5_DMA) // endpoint 5 DMA buffer address +#define USBFS_UEP6_DMA (USBFSD_FS->UEP6_DMA) // endpoint 6 DMA buffer address +#define USBFS_UEP7_DMA (USBFSD_FS->UEP7_DMA) // endpoint 7 DMA buffer address /* USB_EP_CTRL */ -#define USBHD_UEP0_T_LEN (USBOTG_FS->UEP0_TX_LEN) // endpoint 0 transmittal length -#define USBHD_UEP0_TX_CTRL (USBOTG_FS->UEP0_TX_CTRL) // endpoint 0 control -#define USBHD_UEP0_RX_CTRL (USBOTG_FS->UEP0_RX_CTRL) // endpoint 0 control +#define USBFS_UEP0_T_LEN (USBFSD_FS->UEP0_TX_LEN) // endpoint 0 transmittal length +#define USBFS_UEP0_TX_CTRL (USBFSD_FS->UEP0_TX_CTRL) // endpoint 0 control +#define USBFS_UEP0_RX_CTRL (USBFSD_FS->UEP0_RX_CTRL) // endpoint 0 control -#define USBHD_UEP1_T_LEN (USBOTG_FS->UEP1_TX_LEN) // endpoint 1 transmittal length -#define USBHD_UEP1_TX_CTRL (USBOTG_FS->UEP1_TX_CTRL) // endpoint 1 control -#define USBHD_UEP1_RX_CTRL (USBOTG_FS->UEP1_RX_CTRL) // endpoint 1 control +#define USBFS_UEP1_T_LEN (USBFSD_FS->UEP1_TX_LEN) // endpoint 1 transmittal length +#define USBFS_UEP1_TX_CTRL (USBFSD_FS->UEP1_TX_CTRL) // endpoint 1 control +#define USBFS_UEP1_RX_CTRL (USBFSD_FS->UEP1_RX_CTRL) // endpoint 1 control -#define USBHD_UEP2_T_LEN (USBOTG_FS->UEP2_TX_LEN) // endpoint 2 transmittal length -#define USBHD_UEP2_TX_CTRL (USBOTG_FS->UEP2_TX_CTRL) // endpoint 2 control -#define USBHD_UEP2_RX_CTRL (USBOTG_FS->UEP2_RX_CTRL) // endpoint 2 control +#define USBFS_UEP2_T_LEN (USBFSD_FS->UEP2_TX_LEN) // endpoint 2 transmittal length +#define USBFS_UEP2_TX_CTRL (USBFSD_FS->UEP2_TX_CTRL) // endpoint 2 control +#define USBFS_UEP2_RX_CTRL (USBFSD_FS->UEP2_RX_CTRL) // endpoint 2 control -#define USBHD_UEP3_T_LEN (USBOTG_FS->UEP3_TX_LEN) // endpoint 3 transmittal length -#define USBHD_UEP3_TX_CTRL (USBOTG_FS->UEP3_TX_CTRL) // endpoint 3 control -#define USBHD_UEP3_RX_CTRL (USBOTG_FS->UEP3_RX_CTRL) // endpoint 3 control +#define USBFS_UEP3_T_LEN (USBFSD_FS->UEP3_TX_LEN) // endpoint 3 transmittal length +#define USBFS_UEP3_TX_CTRL (USBFSD_FS->UEP3_TX_CTRL) // endpoint 3 control +#define USBFS_UEP3_RX_CTRL (USBFSD_FS->UEP3_RX_CTRL) // endpoint 3 control -#define USBHD_UEP4_T_LEN (USBOTG_FS->UEP4_TX_LEN) // endpoint 4 transmittal length -#define USBHD_UEP4_TX_CTRL (USBOTG_FS->UEP4_TX_CTRL) // endpoint 4 control -#define USBHD_UEP4_RX_CTRL (USBOTG_FS->UEP4_RX_CTRL) // endpoint 4 control +#define USBFS_UEP4_T_LEN (USBFSD_FS->UEP4_TX_LEN) // endpoint 4 transmittal length +#define USBFS_UEP4_TX_CTRL (USBFSD_FS->UEP4_TX_CTRL) // endpoint 4 control +#define USBFS_UEP4_RX_CTRL (USBFSD_FS->UEP4_RX_CTRL) // endpoint 4 control -#define USBHD_UEP5_T_LEN (USBOTG_FS->UEP5_TX_LEN) // endpoint 5 transmittal length -#define USBHD_UEP5_TX_CTRL (USBOTG_FS->UEP5_TX_CTRL) // endpoint 5 control -#define USBHD_UEP5_RX_CTRL (USBOTG_FS->UEP5_RX_CTRL) // endpoint 5 control +#define USBFS_UEP5_T_LEN (USBFSD_FS->UEP5_TX_LEN) // endpoint 5 transmittal length +#define USBFS_UEP5_TX_CTRL (USBFSD_FS->UEP5_TX_CTRL) // endpoint 5 control +#define USBFS_UEP5_RX_CTRL (USBFSD_FS->UEP5_RX_CTRL) // endpoint 5 control -#define USBHD_UEP6_T_LEN (USBOTG_FS->UEP6_TX_LEN) // endpoint 6 transmittal length -#define USBHD_UEP6_TX_CTRL (USBOTG_FS->UEP6_TX_CTRL) // endpoint 6 control -#define USBHD_UEP6_RX_CTRL (USBOTG_FS->UEP6_RX_CTRL) // endpoint 6 control +#define USBFS_UEP6_T_LEN (USBFSD_FS->UEP6_TX_LEN) // endpoint 6 transmittal length +#define USBFS_UEP6_TX_CTRL (USBFSD_FS->UEP6_TX_CTRL) // endpoint 6 control +#define USBFS_UEP6_RX_CTRL (USBFSD_FS->UEP6_RX_CTRL) // endpoint 6 control -#define USBHD_UEP7_T_LEN (USBOTG_FS->UEP7_TX_LEN) // endpoint 7 transmittal length -#define USBHD_UEP7_TX_CTRL (USBOTG_FS->UEP7_TX_CTRL) // endpoint 7 control -#define USBHD_UEP7_RX_CTRL (USBOTG_FS->UEP7_RX_CTRL) // endpoint 7 control +#define USBFS_UEP7_T_LEN (USBFSD_FS->UEP7_TX_LEN) // endpoint 7 transmittal length +#define USBFS_UEP7_TX_CTRL (USBFSD_FS->UEP7_TX_CTRL) // endpoint 7 control +#define USBFS_UEP7_RX_CTRL (USBFSD_FS->UEP7_RX_CTRL) // endpoint 7 control -#define USBHD_UEP_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle -#define USBHD_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 -#define USBHD_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 -#define USBHD_UEP_R_RES1 0x02 // handshake response type high bit for USB endpoint X receiving (OUT) -#define USBHD_UEP_R_RES0 0x01 // handshake response type low bit for USB endpoint X receiving (OUT) -#define USBHD_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) -#define USBHD_UEP_R_RES_ACK 0x00 -#define USBHD_UEP_R_RES_TOUT 0x01 -#define USBHD_UEP_R_RES_NAK 0x02 -#define USBHD_UEP_R_RES_STALL 0x03 +#define USBFS_UEP_R_RES1 0x02 // handshake response type high bit for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES0 0x01 // handshake response type low bit for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_TOUT 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 // RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) // 00: ACK (ready) // 01: no response, time out to host, for non-zero endpoint isochronous transactions // 10: NAK (busy) // 11: STALL (error) -#define USBHD_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) -#define USBHD_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) -#define USBHD_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) -#define USBHD_UEP_T_RES_ACK 0x00 -#define USBHD_UEP_T_RES_TOUT 0x01 -#define USBHD_UEP_T_RES_NAK 0x02 -#define USBHD_UEP_T_RES_STALL 0x03 +#define USBFS_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_TOUT 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 // bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) // 00: DATA0 or DATA1 then expecting ACK (ready) // 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions // 10: NAK (busy) // 11: TALL (error) -#ifdef USBHD_HOST -/* USBOTG_FS HOST CONTROL&CFG */ +#ifdef USBFS_HOST +/* USBFSD_FS HOST CONTROL&CFG */ /* HOST USB_CTRL */ -#define USBHD_UHOST_CTRL (USBOTG_FS->UDEV_CTRL) // USB host physical prot control -#define USBHD_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable -#define USBHD_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level -#define USBHD_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level -#define USBHD_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed -#define USBHD_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset -#define USBHD_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached +#define USBFS_UHOST_CTRL (USBFSD_FS->UDEV_CTRL) // USB host physical prot control +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached /* USB_INT_ST */ -#define USBHD_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received /* USB_BUF_MOD */ -#define USBHD_UH_EP_MOD USBHD_UEP2_3_MOD //host endpoint mode -#define USBHD__UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal -#define USBHD__UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +#define USBFS_UH_EP_MOD USBFS_UEP2_3_MOD //host endpoint mode +#define USBFS__UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS__UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint // UH_EP_TX_EN & UH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA // 0 x: disable endpoint and disable buffer // 1 0: 64 bytes buffer for transmittal (OUT endpoint) // 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes -#define USBHD_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving -#define USBHD_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint // UH_EP_RX_EN & UH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA // 0 x: disable endpoint and disable buffer // 1 0: 64 bytes buffer for receiving (IN endpoint) // 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes /* USB_DMA */ -#define USBHD_UH_RX_DMA USBHD_UEP2_DMA // host rx endpoint buffer high address -#define USBHD_UH_TX_DMA USBHD_UEP3_DMA // host tx endpoint buffer high address +#define USBFS_UH_RX_DMA USBFS_UEP2_DMA // host rx endpoint buffer high address +#define USBFS_UH_TX_DMA USBFS_UEP3_DMA // host tx endpoint buffer high address /* USB_HOST_SETUP */ -#define USBHD_UH_SETUP (*((PUINT16V)(0x50000036))) // host aux setup -#define USBHD_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub -#define USBHD_UH_SOF_EN 0x04 // USB host automatic SOF enable -#define USBHD_UH_EP_PID USBHD_UEP2_T_LEN // host endpoint and PID -#define USBHD_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer -#define USBHD_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer +#define USBFS_UH_SETUP (*((PUINT16V)(0x50000036))) // host aux setup +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x04 // USB host automatic SOF enable +#define USBFS_UH_EP_PID USBFS_UEP2_T_LEN // host endpoint and PID +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer -#define USBHD_UH_RX_CTRL USBHD_UEP2_RX_CTRL // host receiver endpoint control -#define USBHD_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define USBHD_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 -#define USBHD_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions +#define USBFS_UH_RX_CTRL USBFS_UEP2_RX_CTRL // host receiver endpoint control +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions -#define USBHD_UH_RX_CTRL USBHD_UEP2_RX_CTRL // host receiver endpoint control -#define USBHD_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define USBHD_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 -#define USBHD_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions -#define USBHD_UH_TX_LEN USBHD_UEP3_T_LEN // host transmittal endpoint transmittal length +#define USBFS_UH_RX_CTRL USBFS_UEP2_RX_CTRL // host receiver endpoint control +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions +#define USBFS_UH_TX_LEN USBFS_UEP3_T_LEN // host transmittal endpoint transmittal length -#define USBHD_UH_TX_CTRL USBHD_UEP3_TX_CTRL // host transmittal endpoint control -#define USBHD_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle -#define USBHD_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 -#define USBHD_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions +#define USBFS_UH_TX_CTRL USBFS_UEP3_TX_CTRL // host transmittal endpoint control +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions #endif #ifdef USB_OTG -#define USB_OTG_CR (USBOTG_FS->OTG_CR) // usb otg control +#define USB_OTG_CR (USBFSD_FS->OTG_CR) // usb otg control #define USB_OTG_CR_SESS 0x20 // usb otg control,会话电平使能 #define USB_OTG_CR_VBUS 0x10 // usb otg control,VBUS电平使能 #define USB_OTG_CR_OTG_EN 0x08 // usb otg control,OTG功能使能 @@ -654,7 +654,7 @@ typedef struct __PACKED _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */ #define USB_OTG_CR_CHARGEVBUS 0x02 // usb otg control,VBUS充电 #define USB_OTG_CR_DISCHARGEVBUS 0x01 // usb otg control,VBUS放电 -#define USB_OTG_SR (USBOTG_FS->OTG_CR) // usb otg status +#define USB_OTG_SR (USBFSD_FS->OTG_CR) // usb otg status #define USB_OTG_SR_VBUS_VLD 0x01 // usb otg status,A设备VBUS输入电平有效 #define USB_OTG_SR_SESS_VLD 0x02 // usb otg status,会话有效电平有效标志 #define USB_OTG_SR_SESS_END 0x04 // usb otg status,会话结束电平有效标志 @@ -734,15 +734,15 @@ extern PUINT8 pEP5_RAM_Addr; / extern PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64) extern PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64) -extern volatile UINT16 USBHD_Endp1_Up_Flag; /* USB2.0高速设备端点1数据上传状态: 0:空闲; 1:正在上传; */ -extern volatile UINT8 USBHD_Endp1_Down_Flag; /* USB2.0高速设备端点1下传成功标志 */ -extern volatile UINT8 USBHD_Endp1_Down_Len; /* USB2.0高速设备端点1下传长度 */ -extern volatile BOOL USBHD_Endp1_T_Tog; /* USB2.0高速设备端点1发送tog位翻转 */ -extern volatile BOOL USBHD_Endp1_R_Tog; +extern volatile UINT16 USBFS_Endp1_Up_Flag; /* USB2.0高速设备端点1数据上传状态: 0:空闲; 1:正在上传; */ +extern volatile UINT8 USBFS_Endp1_Down_Flag; /* USB2.0高速设备端点1下传成功标志 */ +extern volatile UINT8 USBFS_Endp1_Down_Len; /* USB2.0高速设备端点1下传长度 */ +extern volatile BOOL USBFS_Endp1_T_Tog; /* USB2.0高速设备端点1发送tog位翻转 */ +extern volatile BOOL USBFS_Endp1_R_Tog; -extern volatile UINT16 USBHD_Endp2_Up_Flag; /* USB2.0高速设备端点2数据上传状态: 0:空闲; 1:正在上传; */ -extern volatile UINT16 USBHD_Endp2_Up_LoadPtr; /* USB2.0高速设备端点2数据上传装载偏移 */ -extern volatile UINT8 USBHD_Endp2_Down_Flag; /* USB2.0高速设备端点2下传成功标志 */ +extern volatile UINT16 USBFS_Endp2_Up_Flag; /* USB2.0高速设备端点2数据上传状态: 0:空闲; 1:正在上传; */ +extern volatile UINT16 USBFS_Endp2_Up_LoadPtr; /* USB2.0高速设备端点2数据上传装载偏移 */ +extern volatile UINT8 USBFS_Endp2_Down_Flag; /* USB2.0高速设备端点2下传成功标志 */ /******************************************************************************/ /* DMA地址和缓冲区相关宏定义 */ @@ -791,7 +791,7 @@ extern void DevEP6_IN_Deal( UINT8 l ); extern void DevEP7_IN_Deal( UINT8 l ); extern void USBDeviceInit( void ); -extern void USBOTG_Init( void ); +extern void USBFS_Init( void ); extern uint8_t USBSendData(void); diff --git a/EVT/EXAM/BLE/BLE_USB/APP/peripheral.c b/EVT/EXAM/BLE/BLE_USB/APP/peripheral.c index a0618d9..b69c71d 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/peripheral.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/peripheral.c @@ -16,12 +16,12 @@ /********************************************************************* * INCLUDES */ +#include #include "CONFIG.h" #include "devinfoservice.h" #include "gattprofile.h" #include "peripheral.h" #include "ble_usb_service.h" -#include "ch32v20x_usbotg_device.h" /********************************************************************* * MACROS @@ -214,9 +214,6 @@ void Peripheral_Init() GAPRole_SetParameter(GAPROLE_MAX_CONN_INTERVAL, sizeof(uint16_t), &desired_max_interval); } - // Set the GAP Characteristics - GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); - { uint16_t advInt = DEFAULT_ADVERTISING_INTERVAL; @@ -249,6 +246,9 @@ void Peripheral_Init() SimpleProfile_AddService(GATT_ALL_SERVICES); // Simple GATT Profile ble_usb_add_service(ble_usb_ServiceEvt); + // Set the GAP Characteristics + GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); + // Setup the SimpleProfile Characteristic Values { uint8_t charValue1[SIMPLEPROFILE_CHAR1_LEN] = {1}; diff --git a/EVT/EXAM/BLE/BLE_USB/APP/peripheral_main.c b/EVT/EXAM/BLE/BLE_USB/APP/peripheral_main.c index a7db6b5..020257c 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/peripheral_main.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/peripheral_main.c @@ -12,11 +12,11 @@ /******************************************************************************/ /* Header file contains */ +#include #include "CONFIG.h" #include "HAL.h" #include "gattprofile.h" #include "peripheral.h" -#include "ch32v20x_usbotg_device.h" /********************************************************************* * GLOBAL TYPEDEFS @@ -63,7 +63,7 @@ int main(void) HAL_Init(); GAPRole_PeripheralInit(); Peripheral_Init(); - USBOTG_Init( ); + USBFS_Init( ); Main_Circulation(); } diff --git a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c index 4c5042c..c61911b 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/peripheral.c b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/peripheral.c index 769bdaf..73cba73 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/peripheral.c +++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/peripheral.c @@ -238,9 +238,6 @@ void Peripheral_Init() //GAPRole_PeripheralRegisterAppCBs( (gapRolesParamUpdateCB_t *)&PeripheralParamUpdate ); } - // Set the GAP Characteristics - GGS_SetParameter(GGS_DEVICE_NAME_ATT, GAP_DEVICE_NAME_LEN, attDeviceName); - // Set advertising interval { uint16_t advInt = DEFAULT_ADVERTISING_INTERVAL; @@ -270,6 +267,9 @@ void Peripheral_Init() SimpleProfile_AddService(GATT_ALL_SERVICES); // Simple GATT Profile OTAProfile_AddService(GATT_ALL_SERVICES); + // Set the GAP Characteristics + GGS_SetParameter(GGS_DEVICE_NAME_ATT, GAP_DEVICE_NAME_LEN, attDeviceName); + // Setup the SimpleProfile Characteristic Values { uint8_t charValue1 = 1; diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/CentPeri/APP/central.c b/EVT/EXAM/BLE/CentPeri/APP/central.c index 0288402..7673ded 100644 --- a/EVT/EXAM/BLE/CentPeri/APP/central.c +++ b/EVT/EXAM/BLE/CentPeri/APP/central.c @@ -245,8 +245,6 @@ void Central_Init() GAP_SetParamValue(TGAP_CONN_EST_INT_MAX, DEFAULT_MAX_CONNECTION_INTERVAL); GAP_SetParamValue(TGAP_CONN_EST_SUPERV_TIMEOUT, DEFAULT_CONNECTION_TIMEOUT); - GGS_SetParameter(GGS_DEVICE_NAME_ATT, GAP_DEVICE_NAME_LEN, (uint8_t *)centralDeviceName); - // Setup the GAP Bond Manager { uint32_t passkey = DEFAULT_PASSCODE; @@ -270,6 +268,8 @@ void Central_Init() GGS_AddService(GATT_ALL_SERVICES); // GAP GATTServApp_AddService(GATT_ALL_SERVICES); // GATT attributes + GGS_SetParameter(GGS_DEVICE_NAME_ATT, GAP_DEVICE_NAME_LEN, (uint8_t *)centralDeviceName); + // Setup a delayed profile startup tmos_set_event(centralTaskId, START_DEVICE_EVT); } diff --git a/EVT/EXAM/BLE/CentPeri/APP/peripheral.c b/EVT/EXAM/BLE/CentPeri/APP/peripheral.c index 32e75bd..7261b47 100644 --- a/EVT/EXAM/BLE/CentPeri/APP/peripheral.c +++ b/EVT/EXAM/BLE/CentPeri/APP/peripheral.c @@ -210,9 +210,6 @@ void Peripheral_Init() GAPRole_SetParameter(GAPROLE_MAX_CONN_INTERVAL, sizeof(uint16_t), &desired_max_interval); } - // Set the GAP Characteristics - GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); - // Set advertising interval { uint16_t advInt = DEFAULT_ADVERTISING_INTERVAL; @@ -241,6 +238,9 @@ void Peripheral_Init() DevInfo_AddService(); // Device Information Service SimpleProfile_AddService(GATT_ALL_SERVICES); // Simple GATT Profile + // Set the GAP Characteristics + GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); + // Setup the SimpleProfile Characteristic Values { uint8_t charValue1[SIMPLEPROFILE_CHAR1_LEN] = {1}; diff --git a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/CyclingSensor/APP/cyclingsensor.c b/EVT/EXAM/BLE/CyclingSensor/APP/cyclingsensor.c index 9c1e85c..cbd6e04 100644 --- a/EVT/EXAM/BLE/CyclingSensor/APP/cyclingsensor.c +++ b/EVT/EXAM/BLE/CyclingSensor/APP/cyclingsensor.c @@ -239,9 +239,6 @@ void CyclingSensor_Init() GAPRole_SetParameter(GAPROLE_ADVERT_DATA, sizeof(advertData), advertData); } - // Set the GAP Characteristics - GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); - // Setup the GAP Bond Manager { uint32_t passkey = 0; // passkey "000000" @@ -265,6 +262,9 @@ void CyclingSensor_Init() Cycling_AddService(GATT_ALL_SERVICES); DevInfo_AddService(); + // Set the GAP Characteristics + GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName); + // Register for cycling service callback Cycling_Register(SensorCB); diff --git a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c index 8a8fa40..ba76bfd 100644 --- a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c @@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void ); void SystemInit (void) { RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; RCC->INTR = 0x009F0000; SetSysClock(); } diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/.cproject b/EVT/EXAM/BLE/Direct_Test_Mode/.cproject index 8f24b5f..f11ab4d 100644 --- a/EVT/EXAM/BLE/Direct_Test_Mode/.cproject +++ b/EVT/EXAM/BLE/Direct_Test_Mode/.cproject @@ -69,6 +69,7 @@