diff --git a/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c b/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c index 2bff14d..195d97f 100644 --- a/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/ADC_DMA/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c b/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c index bd24a08..b79e575 100644 --- a/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/AnalogWatchdog/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c b/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c index e5cb1c5..a25b69f 100644 --- a/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Auto_Injection/User/ch32v20x_it.c @@ -36,6 +36,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c b/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c index 2bff14d..195d97f 100644 --- a/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Discontinuous_mode/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c index 2bff14d..195d97f 100644 --- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c index 7e07e5f..ef29929 100644 --- a/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c b/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Internal_Temperature/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c index a804336..c475192 100644 --- a/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c index 37730a5..ac15402 100644 --- a/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c +++ b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c +++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c +++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c +++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c b/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c index 2dc80df..aca61ec 100644 --- a/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c +++ b/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c +++ b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/BLE_UART/APP/ch32v20x_it.c b/EVT/EXAM/BLE/BLE_UART/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/BLE_UART/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/BLE_UART/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_it.c b/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c b/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c index ed27840..01bfb11 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c @@ -185,11 +185,29 @@ void USBDeviceInit(void) * * @return none */ -void USBFS_RCC_Init(void) +void USBFS_RCC_Init( void ) { - RCC->CFGR2 &= ~RCC_USBFS_CLK_SRC; //usbfs clock selection: 0 = systick, 1 = usb20_phy - RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div2); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE); + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); + } + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); + } + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); + } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } /********************************************************************* diff --git a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/ch32v20x_it.c b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/ch32v20x_it.c index f16a877..c932620 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/ch32v20x_it.c @@ -42,6 +42,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c index c61911b..be44e43 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/Ld/Link.ld b/EVT/EXAM/BLE/BackupUpgrade_IAP/Ld/Link.ld index bf36849..5caa183 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_IAP/Ld/Link.ld +++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/Ld/Link.ld @@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size ); MEMORY { -/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/BLE/BackupUpgrade_IAP/Startup/startup_ch32v20x_D8W.S index dafff92..840d949 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_IAP/Startup/startup_ch32v20x_D8W.S +++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/Startup/startup_ch32v20x_D8W.S @@ -93,8 +93,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -158,8 +158,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BB */ @@ -220,8 +220,8 @@ USART3_IRQHandler: 1: j 1b EXTI15_10_IRQHandler: 1: j 1b RTCAlarm_IRQHandler: 1: j 1b USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b ETH_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler: 1: j 1b BB_IRQHandler: 1: j 1b diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/ch32v20x_it.c b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/Ld/Link.ld b/EVT/EXAM/BLE/BackupUpgrade_OTA/Ld/Link.ld index 373914c..a567225 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_OTA/Ld/Link.ld +++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/Ld/Link.ld @@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size ); MEMORY { -/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/BLE/BackupUpgrade_OTA/Startup/startup_ch32v20x_D8W.S index decd64c..848687b 100644 --- a/EVT/EXAM/BLE/BackupUpgrade_OTA/Startup/startup_ch32v20x_D8W.S +++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/Startup/startup_ch32v20x_D8W.S @@ -93,8 +93,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -158,8 +158,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BB */ @@ -220,8 +220,8 @@ USART3_IRQHandler: 1: j 1b EXTI15_10_IRQHandler: 1: j 1b RTCAlarm_IRQHandler: 1: j 1b USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b ETH_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler: 1: j 1b BB_IRQHandler: 1: j 1b diff --git a/EVT/EXAM/BLE/Broadcaster/APP/ch32v20x_it.c b/EVT/EXAM/BLE/Broadcaster/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/Broadcaster/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/Broadcaster/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/CentPeri/APP/ch32v20x_it.c b/EVT/EXAM/BLE/CentPeri/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/CentPeri/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/CentPeri/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/Central/APP/ch32v20x_it.c b/EVT/EXAM/BLE/Central/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/Central/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/Central/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/CyclingSensor/APP/ch32v20x_it.c b/EVT/EXAM/BLE/CyclingSensor/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/CyclingSensor/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/CyclingSensor/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_it.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_it.c index 463960b..b882fff 100644 --- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c index e6bc41b..a75f67b 100644 --- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c @@ -53,18 +53,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c index 8a8fa40..2e5ce73 100644 --- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/HAL/Link.ld b/EVT/EXAM/BLE/HAL/Link.ld index 1646bf1..1cbe6a9 100644 --- a/EVT/EXAM/BLE/HAL/Link.ld +++ b/EVT/EXAM/BLE/HAL/Link.ld @@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size ); MEMORY { -/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K diff --git a/EVT/EXAM/BLE/HID_Consumer/APP/ch32v20x_it.c b/EVT/EXAM/BLE/HID_Consumer/APP/ch32v20x_it.c index 463960b..b882fff 100644 --- a/EVT/EXAM/BLE/HID_Consumer/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/HID_Consumer/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/HID_Keyboard/APP/ch32v20x_it.c b/EVT/EXAM/BLE/HID_Keyboard/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/HID_Keyboard/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/HID_Keyboard/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/HID_Mouse/APP/ch32v20x_it.c b/EVT/EXAM/BLE/HID_Mouse/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/HID_Mouse/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/HID_Mouse/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/HID_Touch/APP/ch32v20x_it.c b/EVT/EXAM/BLE/HID_Touch/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/HID_Touch/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/HID_Touch/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/HeartRate/APP/ch32v20x_it.c b/EVT/EXAM/BLE/HeartRate/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/HeartRate/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/HeartRate/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/LWNS/APP/ch32v20x_it.c b/EVT/EXAM/BLE/LWNS/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/LWNS/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/LWNS/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c b/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/app_main.c index 3bac7de..19806d1 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/app_main.c @@ -95,6 +95,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/app_main.c index c1f9f5c..609632f 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/app_main.c @@ -95,6 +95,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/app_main.c index c1f9f5c..609632f 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/app_main.c @@ -95,6 +95,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/app_main.c index c1f9f5c..609632f 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/app_main.c @@ -95,6 +95,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/app_main.c index c1f9f5c..609632f 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/app_main.c @@ -95,6 +95,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_proxy/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/adv_proxy/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_proxy/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_proxy/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_proxy/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_proxy/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_vendor/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_vendor/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_vendor/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/ch32v20x_it.c index 57016d9..884a8e8 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/ch32v20x_it.c @@ -42,6 +42,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Ld/Link.ld b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Ld/Link.ld index a17ebb7..11af8df 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Ld/Link.ld +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Ld/Link.ld @@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size ); MEMORY { -/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Startup/startup_ch32v20x_D8W.S index dafff92..840d949 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Startup/startup_ch32v20x_D8W.S +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Startup/startup_ch32v20x_D8W.S @@ -93,8 +93,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -158,8 +158,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BB */ @@ -220,8 +220,8 @@ USART3_IRQHandler: 1: j 1b EXTI15_10_IRQHandler: 1: j 1b RTCAlarm_IRQHandler: 1: j 1b USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b ETH_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler: 1: j 1b BB_IRQHandler: 1: j 1b diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/app_main.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Ld/Link.ld b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Ld/Link.ld index 9810bec..77da80f 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Ld/Link.ld +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Ld/Link.ld @@ -1 +1,202 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 152K RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K } PROVIDE( __global_pointer$ = 0x20004000 ); SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) KEEP(*(.ImageFlag)) KEEP(*(.ImageFlag.*)) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); KEEP(*(SORT_NONE(.handle_reset))) } >FLASH AT>FLASH .highcode : { . = ALIGN(4); *(.highcode); *(.highcode.*); . = ALIGN(4); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.sdata2.*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); /*PROVIDE( __global_pointer$ = . + 0x800 );*/ *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM */ .stack ORIGIN(RAM)+LENGTH(RAM) : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_eusrstack = . ); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 152K + RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K + +} + + PROVIDE( __global_pointer$ = 0x20004000 ); + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + KEEP(*(.ImageFlag)) + KEEP(*(.ImageFlag.*)) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + KEEP(*(SORT_NONE(.handle_reset))) + } >FLASH AT>FLASH + + .highcode : + { + . = ALIGN(4); + *(.highcode); + *(.highcode.*); + . = ALIGN(4); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.sdata2.*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + /*PROVIDE( __global_pointer$ = . + 0x800 );*/ + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM */ + + .stack ORIGIN(RAM)+LENGTH(RAM) : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_eusrstack = . ); + } >RAM +} diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Startup/startup_ch32v20x_D8W.S index a117923..923c5db 100644 --- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Startup/startup_ch32v20x_D8W.S +++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Startup/startup_ch32v20x_D8W.S @@ -93,8 +93,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -158,8 +158,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BB */ @@ -220,8 +220,8 @@ USART3_IRQHandler: 1: j 1b EXTI15_10_IRQHandler: 1: j 1b RTCAlarm_IRQHandler: 1: j 1b USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b ETH_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler: 1: j 1b BB_IRQHandler: 1: j 1b diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/app_main.c b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/app_main.c b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/app_main.c index cf7d38b..1433a03 100644 --- a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/app_main.c +++ b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/app_main.c @@ -97,6 +97,7 @@ int main(void) USART_Printf_Init( 115200 ); #endif PRINT("%s\n", VER_LIB); + PRINT("%s\n", VER_MESH_LIB); WCHBLE_Init(); HAL_Init(); bt_mesh_lib_init(); diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MultiCentPeri/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MultiCentPeri/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MultiCentPeri/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MultiCentPeri/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/MultiCentral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/MultiCentral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/MultiCentral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/MultiCentral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/Observer/APP/ch32v20x_it.c b/EVT/EXAM/BLE/Observer/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/Observer/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/Observer/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/ch32v20x_it.c b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Ld/Link.ld b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Ld/Link.ld index 59ce3ae..116cc10 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Ld/Link.ld +++ b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Ld/Link.ld @@ -1 +1,199 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K } PROVIDE( __global_pointer$ = 0x20004000 ); SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); KEEP(*(SORT_NONE(.handle_reset))) } >FLASH AT>FLASH .highcode : { . = ALIGN(4); *(.highcode); *(.highcode.*); . = ALIGN(4); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.sdata2.*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM */ .stack ORIGIN(RAM)+LENGTH(RAM) : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_eusrstack = . ); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K + RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K +} + + PROVIDE( __global_pointer$ = 0x20004000 ); + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + KEEP(*(SORT_NONE(.handle_reset))) + } >FLASH AT>FLASH + + .highcode : + { + . = ALIGN(4); + *(.highcode); + *(.highcode.*); + . = ALIGN(4); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.sdata2.*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM */ + + .stack ORIGIN(RAM)+LENGTH(RAM) : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_eusrstack = . ); + } >RAM +} diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Startup/startup_ch32v20x_D8W.S index 559e24c..52bf9fb 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Startup/startup_ch32v20x_D8W.S +++ b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/Startup/startup_ch32v20x_D8W.S @@ -93,8 +93,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -158,8 +158,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BB */ @@ -220,8 +220,8 @@ USART3_IRQHandler: 1: j 1b EXTI15_10_IRQHandler: 1: j 1b RTCAlarm_IRQHandler: 1: j 1b USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b ETH_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler: 1: j 1b BB_IRQHandler: 1: j 1b diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Ld/Link.ld b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Ld/Link.ld index d8b2231..6553a5b 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Ld/Link.ld +++ b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Ld/Link.ld @@ -1 +1,201 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00004000, LENGTH = 240K RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K } PROVIDE( __global_pointer$ = 0x20004000 ); SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) KEEP(*(.ImageFlag)) KEEP(*(.ImageFlag.*)) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); KEEP(*(SORT_NONE(.handle_reset))) } >FLASH AT>FLASH .highcode : { . = ALIGN(4); *(.highcode); *(.highcode.*); . = ALIGN(4); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.sdata2.*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); /*PROVIDE( __global_pointer$ = . + 0x800 );*/ *(.sdata .sdata.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM */ .stack ORIGIN(RAM)+LENGTH(RAM) : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_eusrstack = . ); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00004000, LENGTH = 240K + RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K +} + + PROVIDE( __global_pointer$ = 0x20004000 ); + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + KEEP(*(.ImageFlag)) + KEEP(*(.ImageFlag.*)) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + KEEP(*(SORT_NONE(.handle_reset))) + } >FLASH AT>FLASH + + .highcode : + { + . = ALIGN(4); + *(.highcode); + *(.highcode.*); + . = ALIGN(4); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.sdata2.*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + /*PROVIDE( __global_pointer$ = . + 0x800 );*/ + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM */ + + .stack ORIGIN(RAM)+LENGTH(RAM) : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_eusrstack = . ); + } >RAM +} diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Startup/startup_ch32v20x_D8W.S index 8714610..f0f887e 100644 --- a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Startup/startup_ch32v20x_D8W.S +++ b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Startup/startup_ch32v20x_D8W.S @@ -93,8 +93,8 @@ _vector_base: .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ - .word USBHD_IRQHandler /* USBHD Break */ - .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ + .word USBFS_IRQHandler /* USBFS Break */ + .word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */ .word ETH_IRQHandler /* ETH global */ .word ETHWakeUp_IRQHandler /* ETH Wake up */ .word BB_IRQHandler /* BLE BB */ @@ -158,8 +158,8 @@ _vector_base: .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ - .weak USBHD_IRQHandler /* USBHD */ - .weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */ .weak ETH_IRQHandler /* ETH global */ .weak ETHWakeUp_IRQHandler /* ETHWakeUp */ .weak BB_IRQHandler /* BB */ @@ -220,8 +220,8 @@ USART3_IRQHandler: 1: j 1b EXTI15_10_IRQHandler: 1: j 1b RTCAlarm_IRQHandler: 1: j 1b USBWakeUp_IRQHandler: 1: j 1b -USBHD_IRQHandler: 1: j 1b -USBHDWakeUp_IRQHandler: 1: j 1b +USBFS_IRQHandler: 1: j 1b +USBFSWakeUp_IRQHandler: 1: j 1b ETH_IRQHandler: 1: j 1b ETHWakeUp_IRQHandler: 1: j 1b BB_IRQHandler: 1: j 1b diff --git a/EVT/EXAM/BLE/PAwR_ADV/APP/ch32v20x_it.c b/EVT/EXAM/BLE/PAwR_ADV/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/PAwR_ADV/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/PAwR_ADV/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c b/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/PAwR_RSP/APP/ch32v20x_it.c b/EVT/EXAM/BLE/PAwR_RSP/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/PAwR_RSP/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/PAwR_RSP/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/Peripheral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/Peripheral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/Peripheral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/Peripheral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/Peripheral_ETH/APP/ch32v20x_it.c b/EVT/EXAM/BLE/Peripheral_ETH/APP/ch32v20x_it.c index 8ec1051..8358b13 100644 --- a/EVT/EXAM/BLE/Peripheral_ETH/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/Peripheral_ETH/APP/ch32v20x_it.c @@ -47,6 +47,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c index 648b3b0..f073ad1 100644 --- a/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/RF_PHY/APP/ch32v20x_it.c b/EVT/EXAM/BLE/RF_PHY/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/RF_PHY/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/RF_PHY/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/RF_PHY_Auto/APP/ch32v20x_it.c b/EVT/EXAM/BLE/RF_PHY_Auto/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/RF_PHY_Auto/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/RF_PHY_Auto/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/RF_PHY_Hop/APP/ch32v20x_it.c b/EVT/EXAM/BLE/RF_PHY_Hop/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/RF_PHY_Hop/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/RF_PHY_Hop/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/RunningSensor/APP/ch32v20x_it.c b/EVT/EXAM/BLE/RunningSensor/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/RunningSensor/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/RunningSensor/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/SYNC_ADV/APP/ch32v20x_it.c b/EVT/EXAM/BLE/SYNC_ADV/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/SYNC_ADV/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/SYNC_ADV/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/SYNC_SCAN/APP/ch32v20x_it.c b/EVT/EXAM/BLE/SYNC_SCAN/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/SYNC_SCAN/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/SYNC_SCAN/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/SpeedTest_Central/APP/ch32v20x_it.c b/EVT/EXAM/BLE/SpeedTest_Central/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/SpeedTest_Central/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/SpeedTest_Central/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/ch32v20x_it.c b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/ch32v20x_it.c +++ b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c +++ b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/BLE/peripheral_ancs_client/app/ch32v20x_it.c b/EVT/EXAM/BLE/peripheral_ancs_client/app/ch32v20x_it.c index f84a128..b3e5374 100644 --- a/EVT/EXAM/BLE/peripheral_ancs_client/app/ch32v20x_it.c +++ b/EVT/EXAM/BLE/peripheral_ancs_client/app/ch32v20x_it.c @@ -43,6 +43,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c b/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c index ba76bfd..d226b03 100644 --- a/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c +++ b/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/CAN/Networking/User/ch32v20x_it.c b/EVT/EXAM/CAN/Networking/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/CAN/Networking/User/ch32v20x_it.c +++ b/EVT/EXAM/CAN/Networking/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/CAN/Networking/User/main.c b/EVT/EXAM/CAN/Networking/User/main.c index 413033e..479495c 100644 --- a/EVT/EXAM/CAN/Networking/User/main.c +++ b/EVT/EXAM/CAN/Networking/User/main.c @@ -252,8 +252,8 @@ int main(void) printf("Rx Mode\r\n"); #endif - /* Bps = 333Kbps */ - CAN_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 12, CAN_Mode_Normal); + /* Bps = 250Kbps */ + CAN_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 16, CAN_Mode_Normal); while(1) { diff --git a/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c b/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c +++ b/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/CAN/TestMode/User/ch32v20x_it.c b/EVT/EXAM/CAN/TestMode/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/CAN/TestMode/User/ch32v20x_it.c +++ b/EVT/EXAM/CAN/TestMode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/CAN/TestMode/User/main.c b/EVT/EXAM/CAN/TestMode/User/main.c index fc22768..3506d5a 100644 --- a/EVT/EXAM/CAN/TestMode/User/main.c +++ b/EVT/EXAM/CAN/TestMode/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2024/04/06 + * Date : 2024/10/25 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -190,17 +190,17 @@ int main(void) printf("SystemClk:%d\r\n", SystemCoreClock); printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() ); -/* Bps = 333Kbps */ +/* Bps = 250Kbps */ #if(TEST_MODE == SILENT_MODE) - CAN_Test_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 12, CAN_Mode_Silent); + CAN_Test_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 16, CAN_Mode_Silent); printf("Slient Mode\r\n"); #elif(TEST_MODE == LOOPBACK_MODE) - CAN_Test_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 12, CAN_Mode_LoopBack); + CAN_Test_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 16, CAN_Mode_LoopBack); printf("LoopBack Mode\r\n"); #elif(TEST_MODE == SILENT_LOOPBACK_MODE) - CAN_Test_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 12, CAN_Mode_Silent_LoopBack); + CAN_Test_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 16, CAN_Mode_Silent_LoopBack); printf("Silent_LoopBack Mode\r\n"); #endif diff --git a/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c b/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c +++ b/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/CAN/Time-triggered/User/ch32v20x_it.c b/EVT/EXAM/CAN/Time-triggered/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/CAN/Time-triggered/User/ch32v20x_it.c +++ b/EVT/EXAM/CAN/Time-triggered/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/CAN/Time-triggered/User/main.c b/EVT/EXAM/CAN/Time-triggered/User/main.c index 9a6a0d8..d2ba43c 100644 --- a/EVT/EXAM/CAN/Time-triggered/User/main.c +++ b/EVT/EXAM/CAN/Time-triggered/User/main.c @@ -280,8 +280,8 @@ int main(void) printf("SystemClk:%d\r\n", SystemCoreClock); printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() ); - /* Bps = 333Kbps */ - CAN_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 12, CAN_Mode_Normal); + /* Bps = 250Kbps */ + CAN_Mode_Init(CAN_SJW_1tq, CAN_BS2_5tq, CAN_BS1_6tq, 16, CAN_Mode_Normal); #if(CAN_MODE == TX_MODE) printf("TX Mode\r\n"); diff --git a/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c b/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c +++ b/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/CRC/CRC_Calculation/User/ch32v20x_it.c b/EVT/EXAM/CRC/CRC_Calculation/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/CRC/CRC_Calculation/User/ch32v20x_it.c +++ b/EVT/EXAM/CRC/CRC_Calculation/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c b/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c +++ b/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/User/ch32v20x_it.c b/EVT/EXAM/DMA/DMA_MEM2MEM/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/DMA/DMA_MEM2MEM/User/ch32v20x_it.c +++ b/EVT/EXAM/DMA/DMA_MEM2MEM/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c b/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c +++ b/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/DHCP/Ld/Link.ld b/EVT/EXAM/ETH/DHCP/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/DHCP/Ld/Link.ld +++ b/EVT/EXAM/ETH/DHCP/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/DHCP/User/ch32v20x_it.c b/EVT/EXAM/ETH/DHCP/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/DHCP/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/DHCP/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c b/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/DNS/Ld/Link.ld b/EVT/EXAM/ETH/DNS/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/DNS/Ld/Link.ld +++ b/EVT/EXAM/ETH/DNS/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/DNS/User/ch32v20x_it.c b/EVT/EXAM/ETH/DNS/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/DNS/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/DNS/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c b/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/ETH_CFG/Ld/Link.ld b/EVT/EXAM/ETH/ETH_CFG/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/ETH_CFG/Ld/Link.ld +++ b/EVT/EXAM/ETH/ETH_CFG/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/ETH_CFG/User/ch32v20x_it.c b/EVT/EXAM/ETH/ETH_CFG/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/ETH_CFG/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/ETH_CFG/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/ETH_IAP/Ld/Link.ld b/EVT/EXAM/ETH/ETH_IAP/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/ETH_IAP/Ld/Link.ld +++ b/EVT/EXAM/ETH/ETH_IAP/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/ETH_IAP/User/ch32v20x_it.c b/EVT/EXAM/ETH/ETH_IAP/User/ch32v20x_it.c index 4c6ce21..0d63673 100644 --- a/EVT/EXAM/ETH/ETH_IAP/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/ETH_IAP/User/ch32v20x_it.c @@ -43,6 +43,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/ETH_UART/Ld/Link.ld b/EVT/EXAM/ETH/ETH_UART/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/ETH_UART/Ld/Link.ld +++ b/EVT/EXAM/ETH/ETH_UART/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/ETH_UART/User/ch32v20x_it.c b/EVT/EXAM/ETH/ETH_UART/User/ch32v20x_it.c index 9420e98..8aaad9c 100644 --- a/EVT/EXAM/ETH/ETH_UART/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/ETH_UART/User/ch32v20x_it.c @@ -44,6 +44,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/IPRaw_PING/Ld/Link.ld b/EVT/EXAM/ETH/IPRaw_PING/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/IPRaw_PING/Ld/Link.ld +++ b/EVT/EXAM/ETH/IPRaw_PING/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/IPRaw_PING/User/ch32v20x_it.c b/EVT/EXAM/ETH/IPRaw_PING/User/ch32v20x_it.c index fa18303..4ec6cd1 100644 --- a/EVT/EXAM/ETH/IPRaw_PING/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/IPRaw_PING/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c b/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/MAC_RAW/Ld/Link.ld b/EVT/EXAM/ETH/MAC_RAW/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/MAC_RAW/Ld/Link.ld +++ b/EVT/EXAM/ETH/MAC_RAW/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/MAC_RAW/User/ch32v20x_it.c b/EVT/EXAM/ETH/MAC_RAW/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/MAC_RAW/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/MAC_RAW/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c b/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/MQTT/Ld/Link.ld b/EVT/EXAM/ETH/MQTT/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/MQTT/Ld/Link.ld +++ b/EVT/EXAM/ETH/MQTT/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/MQTT/User/ch32v20x_it.c b/EVT/EXAM/ETH/MQTT/User/ch32v20x_it.c index 1fe91ad..7944432 100644 --- a/EVT/EXAM/ETH/MQTT/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/MQTT/User/ch32v20x_it.c @@ -43,6 +43,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c b/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/Mail/Ld/Link.ld b/EVT/EXAM/ETH/Mail/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/Mail/Ld/Link.ld +++ b/EVT/EXAM/ETH/Mail/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/Mail/User/ch32v20x_it.c b/EVT/EXAM/ETH/Mail/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/Mail/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/Mail/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c b/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/NetLib/libwchnet.a b/EVT/EXAM/ETH/NetLib/libwchnet.a index 9eee482..1a77f93 100644 Binary files a/EVT/EXAM/ETH/NetLib/libwchnet.a and b/EVT/EXAM/ETH/NetLib/libwchnet.a differ diff --git a/EVT/EXAM/ETH/NetLib/wchnet.h b/EVT/EXAM/ETH/NetLib/wchnet.h index 0e2764a..f1c124c 100644 --- a/EVT/EXAM/ETH/NetLib/wchnet.h +++ b/EVT/EXAM/ETH/NetLib/wchnet.h @@ -21,7 +21,7 @@ extern "C" { #endif -#define WCHNET_LIB_VER 0x19 //the library version number +#define WCHNET_LIB_VER 0x1A //the library version number #define WCHNET_CFG_VALID 0x12345678 //Configuration value valid flag /* LED state @LED_STAT */ diff --git a/EVT/EXAM/ETH/TcpClient/Ld/Link.ld b/EVT/EXAM/ETH/TcpClient/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/TcpClient/Ld/Link.ld +++ b/EVT/EXAM/ETH/TcpClient/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/TcpClient/User/ch32v20x_it.c b/EVT/EXAM/ETH/TcpClient/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/TcpClient/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/TcpClient/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c b/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/TcpServer/Ld/Link.ld b/EVT/EXAM/ETH/TcpServer/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/TcpServer/Ld/Link.ld +++ b/EVT/EXAM/ETH/TcpServer/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/TcpServer/User/ch32v20x_it.c b/EVT/EXAM/ETH/TcpServer/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/TcpServer/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/TcpServer/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/UdpClient/Ld/Link.ld b/EVT/EXAM/ETH/UdpClient/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/UdpClient/Ld/Link.ld +++ b/EVT/EXAM/ETH/UdpClient/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/UdpClient/User/ch32v20x_it.c b/EVT/EXAM/ETH/UdpClient/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/UdpClient/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/UdpClient/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c b/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/UdpServer/Ld/Link.ld b/EVT/EXAM/ETH/UdpServer/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/UdpServer/Ld/Link.ld +++ b/EVT/EXAM/ETH/UdpServer/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/UdpServer/User/ch32v20x_it.c b/EVT/EXAM/ETH/UdpServer/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/UdpServer/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/UdpServer/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/ETH/WebServer/Ld/Link.ld b/EVT/EXAM/ETH/WebServer/Ld/Link.ld index 33563df..ca5b867 100644 --- a/EVT/EXAM/ETH/WebServer/Ld/Link.ld +++ b/EVT/EXAM/ETH/WebServer/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ + +/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/ETH/WebServer/User/ch32v20x_it.c b/EVT/EXAM/ETH/WebServer/User/ch32v20x_it.c index b527796..19d997a 100644 --- a/EVT/EXAM/ETH/WebServer/User/ch32v20x_it.c +++ b/EVT/EXAM/ETH/WebServer/User/ch32v20x_it.c @@ -42,6 +42,7 @@ void HardFault_Handler(void) printf("mcause:%08x\r\n",__get_MCAUSE()); printf("mtval:%08x\r\n",__get_MTVAL()); printf("mepc:%08x\r\n",__get_MEPC()); + NVIC_SystemReset(); while (1); } diff --git a/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c index 9371fd2..6405f25 100644 --- a/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c +++ b/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/EXTI/EXTI0/User/ch32v20x_it.c b/EVT/EXAM/EXTI/EXTI0/User/ch32v20x_it.c index a2e0cdc..0eb2511 100644 --- a/EVT/EXAM/EXTI/EXTI0/User/ch32v20x_it.c +++ b/EVT/EXAM/EXTI/EXTI0/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c b/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c +++ b/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/FLASH/FLASH_Program/User/ch32v20x_it.c b/EVT/EXAM/FLASH/FLASH_Program/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/FLASH/FLASH_Program/User/ch32v20x_it.c +++ b/EVT/EXAM/FLASH/FLASH_Program/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c b/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c +++ b/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Ld/Link.ld b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Ld/Link.ld index edd38b2..6b68650 100644 --- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Ld/Link.ld +++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Ld/Link.ld @@ -1 +1,190 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /**/ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); __freertos_irq_stack_top = .; } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/**/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K + + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K + + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +*/ +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + __freertos_irq_stack_top = .; + } >RAM + +} + + + diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S index d70b5fd..aaa76c5 100644 --- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S +++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S @@ -3,7 +3,7 @@ ;* Author : WCH ;* Version : V1.0.1 ;* Date : 2024/01/31 -;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 +;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 ;* vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/ch32v20x_it.c b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/ch32v20x_it.c index c5abc83..5c90e86 100644 --- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/ch32v20x_it.c +++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c +++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/GPIO/GPIO_Toggle/User/ch32v20x_it.c b/EVT/EXAM/GPIO/GPIO_Toggle/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/GPIO/GPIO_Toggle/User/ch32v20x_it.c +++ b/EVT/EXAM/GPIO/GPIO_Toggle/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c b/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c +++ b/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S index d70b5fd..aaa76c5 100644 --- a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S +++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S @@ -3,7 +3,7 @@ ;* Author : WCH ;* Version : V1.0.1 ;* Date : 2024/01/31 -;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 +;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 ;* vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c b/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c index da23971..a71dec8 100644 --- a/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c +++ b/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/I2C/I2C_10bit_Mode/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_10bit_Mode/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/I2C/I2C_10bit_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/I2C/I2C_10bit_Mode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c index 72f8547..253dedb 100644 --- a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/I2C/I2C_7bit_Mode/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_7bit_Mode/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/I2C/I2C_7bit_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/I2C/I2C_7bit_Mode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/I2C/I2C_DMA/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_DMA/User/ch32v20x_it.c index 85f3e41..7d11824 100644 --- a/EVT/EXAM/I2C/I2C_DMA/User/ch32v20x_it.c +++ b/EVT/EXAM/I2C/I2C_DMA/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c +++ b/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/I2C/I2C_EEPROM/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_EEPROM/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/I2C/I2C_EEPROM/User/ch32v20x_it.c +++ b/EVT/EXAM/I2C/I2C_EEPROM/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c +++ b/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/I2C/I2C_PEC/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_PEC/User/ch32v20x_it.c index 03cf4cc..9b91e1c 100644 --- a/EVT/EXAM/I2C/I2C_PEC/User/ch32v20x_it.c +++ b/EVT/EXAM/I2C/I2C_PEC/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c +++ b/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/ch32v20x_it.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/ch32v20x_it.c index 2bff14d..195d97f 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/ch32v20x_it.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/CONFIG/hw_config.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/CONFIG/hw_config.c index 333a6b4..d90ceae 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/CONFIG/hw_config.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/CONFIG/hw_config.c @@ -56,8 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div2); - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); + } + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); + } + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); + } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_it.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_it.c index 883175c..638303f 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_it.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_usbfs_device.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_usbfs_device.c index 3e5b1be..a38a9af 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/ch32v20x_usbfs_device.c @@ -93,13 +93,32 @@ void USBDeviceInit( void ) /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Initializes the USB clock configuration. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init(void) { - RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div2); + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); + } + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); + } + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); + } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c index 1c72e34..6107356 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c @@ -73,17 +73,20 @@ u8 RecData_Deal(void) break; case CMD_IAP_VERIFY: - if (Verity_Star_flag == 0) { - Verity_Star_flag = 1; - - for (i = 0; i < (256 - CodeLen); i++) { + if (Verity_Star_flag == 0) + { + Verity_Star_flag = 1; + if(CodeLen != 0) + { + for (i = 0; i < (256 - CodeLen); i++) + { Fast_Program_Buf[CodeLen + i] = 0xff; } - FLASH_ErasePage_Fast(Program_addr); CH32_IAP_Program(Program_addr, (u32*) Fast_Program_Buf); CodeLen = 0; - } + } + } s = ERR_SCUESS; for (i = 0; i < Lenth; i++) { diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c +++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/INT/Interrupt_VTF/User/ch32v20x_it.c b/EVT/EXAM/INT/Interrupt_VTF/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/INT/Interrupt_VTF/User/ch32v20x_it.c +++ b/EVT/EXAM/INT/Interrupt_VTF/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c b/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c +++ b/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.c b/EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.c +++ b/EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c b/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c +++ b/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.c b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.c index 23795de..70f99d3 100644 --- a/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.c +++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while(1) { } diff --git a/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c index 4040756..6607582 100644 --- a/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c +++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PMP/PMP/User/main.c b/EVT/EXAM/PMP/PMP/User/main.c index 02f2d51..9a51fba 100644 --- a/EVT/EXAM/PMP/PMP/User/main.c +++ b/EVT/EXAM/PMP/PMP/User/main.c @@ -182,7 +182,7 @@ int main(void) for (uint32_t z = (uint32_t)&ProtectSec[sizeof(ProtectSec) / sizeof(*ProtectSec) - 1]; z > (uint32_t)ProtectSec; z -= 1) { - FinalOprateAddress = z; + FinalOprateAddress = *(uint8_t *)z; *(uint8_t *)z = 0; } diff --git a/EVT/EXAM/PMP/PMP/User/system_ch32v20x.c b/EVT/EXAM/PMP/PMP/User/system_ch32v20x.c index 4040756..6607582 100644 --- a/EVT/EXAM/PMP/PMP/User/system_ch32v20x.c +++ b/EVT/EXAM/PMP/PMP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/PVD_VoltageJudger/User/ch32v20x_it.c b/EVT/EXAM/PWR/PVD_VoltageJudger/User/ch32v20x_it.c index 10e82a3..554d95f 100644 --- a/EVT/EXAM/PWR/PVD_VoltageJudger/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/PVD_VoltageJudger/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/PVD_VoltageJudger/User/main.c b/EVT/EXAM/PWR/PVD_VoltageJudger/User/main.c index 466f235..b3559a2 100644 --- a/EVT/EXAM/PWR/PVD_VoltageJudger/User/main.c +++ b/EVT/EXAM/PWR/PVD_VoltageJudger/User/main.c @@ -60,7 +60,7 @@ void PVD_Init(void) NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - PWR_PVDLevelConfig(PWR_PVDLevel_2V9); + PWR_PVDLevelConfig(PWR_PVDLevel_MODE7); PWR_PVDCmd(ENABLE); } diff --git a/EVT/EXAM/PWR/PVD_VoltageJudger/User/system_ch32v20x.c b/EVT/EXAM/PWR/PVD_VoltageJudger/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/PVD_VoltageJudger/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/PVD_VoltageJudger/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/PVD_Wakeup/User/ch32v20x_it.c b/EVT/EXAM/PWR/PVD_Wakeup/User/ch32v20x_it.c index 10e82a3..554d95f 100644 --- a/EVT/EXAM/PWR/PVD_Wakeup/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/PVD_Wakeup/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/PVD_Wakeup/User/main.c b/EVT/EXAM/PWR/PVD_Wakeup/User/main.c index f7e0911..d99f7f0 100644 --- a/EVT/EXAM/PWR/PVD_Wakeup/User/main.c +++ b/EVT/EXAM/PWR/PVD_Wakeup/User/main.c @@ -60,7 +60,7 @@ void PVD_Init(void) NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - PWR_PVDLevelConfig(PWR_PVDLevel_2V2); + PWR_PVDLevelConfig(PWR_PVDLevel_MODE0); PWR_PVDCmd(ENABLE); } diff --git a/EVT/EXAM/PWR/PVD_Wakeup/User/system_ch32v20x.c b/EVT/EXAM/PWR/PVD_Wakeup/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/PVD_Wakeup/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/PVD_Wakeup/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/Sleep_Mode/User/ch32v20x_it.c b/EVT/EXAM/PWR/Sleep_Mode/User/ch32v20x_it.c index 10e82a3..554d95f 100644 --- a/EVT/EXAM/PWR/Sleep_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/Sleep_Mode/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/Standby_Mode/User/ch32v20x_it.c b/EVT/EXAM/PWR/Standby_Mode/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/PWR/Standby_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/Standby_Mode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/Standby_RAM_Application/.cproject b/EVT/EXAM/PWR/Standby_RAM_Application/.cproject new file mode 100644 index 0000000..2c64938 --- /dev/null +++ b/EVT/EXAM/PWR/Standby_RAM_Application/.cproject @@ -0,0 +1,141 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EVT/EXAM/PWR/Standby_RAM_Application/.project b/EVT/EXAM/PWR/Standby_RAM_Application/.project new file mode 100644 index 0000000..5308b5d --- /dev/null +++ b/EVT/EXAM/PWR/Standby_RAM_Application/.project @@ -0,0 +1,65 @@ + + + Standby_RAM_Application + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Core + 2 + PARENT-2-PROJECT_LOC/SRC/Core + + + Debug + 2 + PARENT-2-PROJECT_LOC/SRC/Debug + + + Peripheral + 2 + PARENT-2-PROJECT_LOC/SRC/Peripheral + + + Startup + 2 + PARENT-2-PROJECT_LOC/SRC/Startup + + + + + 0 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + + + copy_PARENT + $%7BPARENT-3-ECLIPSE_HOME%7D/%E5%B7%A5%E4%BD%9C/302%E6%B5%8B%E8%AF%955.19/%E6%88%91%E7%9A%84%E6%B5%8B%E8%AF%95%E5%8F%AF%E7%94%A8/SS_RAM_LV + + + diff --git a/EVT/EXAM/PWR/Standby_RAM_Application/.template b/EVT/EXAM/PWR/Standby_RAM_Application/.template new file mode 100644 index 0000000..f089c41 --- /dev/null +++ b/EVT/EXAM/PWR/Standby_RAM_Application/.template @@ -0,0 +1,18 @@ +Mcu Type=CH32V20x +Address=0x08000000 +Target Path=obj\Standby_RAM_Application.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32V203 +Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. + +PeripheralVersion=1.0 +MCU=CH32V203RBT6 +SDIPrintf=true +CLKSpeed=1 diff --git a/EVT/EXAM/PWR/Standby_RAM_Application/Ld/Link.ld b/EVT/EXAM/PWR/Standby_RAM_Application/Ld/Link.ld new file mode 100644 index 0000000..6aa9898 --- /dev/null +++ b/EVT/EXAM/PWR/Standby_RAM_Application/Ld/Link.ld @@ -0,0 +1,203 @@ +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K +*/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 144K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K + +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .keep_2kram ORIGIN(RAM) (NOLOAD):{ + . = ALIGN(4); + *(.keep_2kram.*) + *(.keep_2kram) + ASSERT(SIZEOF(.keep_2kram) <= 2048, "keep_2kram too large!"); + . = ALIGN(4); + }>RAM + + .keep_30kram ORIGIN(RAM)+2048 (NOLOAD):{ + . = ALIGN(4); + *(.keep_30kram.*) + *(.keep_30kram) + ASSERT(SIZEOF(.keep_30kram) <= 30720, "keep_30kram too large!"); + . = ALIGN(4); + }>RAM + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/PWR/Standby_RAM_Application/Standby_RAM_Application.wvproj b/EVT/EXAM/PWR/Standby_RAM_Application/Standby_RAM_Application.wvproj new file mode 100644 index 0000000..2cd99d9 --- /dev/null +++ b/EVT/EXAM/PWR/Standby_RAM_Application/Standby_RAM_Application.wvproj @@ -0,0 +1,2 @@ +iCZ ?"ǁrF<.ſ?/XOĿChQN$*EBk!2t+buhnUb]xll| ++"CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) + { + SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull; +#else + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; +#endif + } + else + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = (HSE_VALUE>>2) * pllmull; +#else + SystemCoreClock = HSE_VALUE * pllmull; +#endif + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source + * CH32V20x_D6 (HSE=8MHZ) + * CH32V20x_D8 (HSE=32MHZ) + * CH32V20x_D8W (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { +#if defined (CH32V20x_D8W) + RCC->CFGR0 |= (uint32_t)(3<<22); + /* HCLK = SYSCLK/2 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; +#else + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +#endif + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#endif diff --git a/EVT/EXAM/PWR/Standby_RAM_Application/User/system_ch32v20x.h b/EVT/EXAM/PWR/Standby_RAM_Application/User/system_ch32v20x.h new file mode 100644 index 0000000..9c8a3f7 --- /dev/null +++ b/EVT/EXAM/PWR/Standby_RAM_Application/User/system_ch32v20x.h @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32v20x_H +#define __SYSTEM_ch32v20x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V20x_SYSTEM_H */ + + + diff --git a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/ch32v20x_it.c b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/ch32v20x_it.c index 90af425..9abce2f 100644 --- a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/main.c b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/main.c index c28d8d7..bd8765a 100644 --- a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/main.c +++ b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/main.c @@ -12,10 +12,12 @@ /* *@Note - * when LV is enabled in standby mode, RAM 2k and 30K low-power data holding routines: - * This routine demonstrates writing data at the specified location of 2K RAM and 30K RAM, - * then WFI enters STANDBY sleep mode and turns on LV,Input high level through PA0 (wakeup) pin - * to exit standby mode, print RAM data after waking up, and test whether RAM holds data. + * when LV is enabled in standby mode, RAM 2k and 30K low-power data holding routines: + * This routine demonstrates writing data at the specified location of 2K RAM and 30K RAM(Applicable to + * CH32V20x_D8 and CH32V20x_D8W,CH32V20x_D6 has a 20K RAM data holding option),then WFI enters STANDBY + * sleep mode and turns on LV,Input high level through PA0 (wakeup) pin to exit standby mode, print RAM + * data after waking up, and test whether RAM holds data. + * */ #include "debug.h" @@ -27,7 +29,7 @@ /********************************************************************* * @fn TestDataWrite * - * @brief Write 0x11111111 to certain address of 2K RAM and 30K RAM. + * @brief Write data to certain address of 2K RAM and 30K RAM. * * @return none */ @@ -53,7 +55,7 @@ void TestDataWrite(void) { *(uint32_t volatile *)(myAddr2 + (i << 2)) = 0x44444444; } - for(i = 0; i < 10; i++) //Check 30K RAM + for(i = 0; i < 10; i++) //Check 2K RAM { if((*(uint32_t volatile *)(myAddr2 + (i << 2))) != 0x44444444) { @@ -120,14 +122,11 @@ int main(void) /* Delay 1.5s to avoid entering low power mode immediately after reset*/ Delay_Ms(1500); - while(1) - { - TestDataRead(); - printf("4.Standby Mode RAM LV Test\r\n"); - TestDataWrite(); - PWR_WakeUpPinCmd(ENABLE); - PWR_EnterSTANDBYMode_RAM_LV(); - printf("\r\n4.Out \r\n"); - printf("\r\n ########## \r\n"); - } + + TestDataRead(); + printf("Standby RAM LV Mode Test\r\n"); + TestDataWrite(); + PWR_WakeUpPinCmd(ENABLE); + PWR_EnterSTANDBYMode_RAM_LV(); + while(1); } diff --git a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/Standby_RAM_Mode/User/ch32v20x_it.c b/EVT/EXAM/PWR/Standby_RAM_Mode/User/ch32v20x_it.c index 90af425..9abce2f 100644 --- a/EVT/EXAM/PWR/Standby_RAM_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/Standby_RAM_Mode/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/Standby_RAM_Mode/User/main.c b/EVT/EXAM/PWR/Standby_RAM_Mode/User/main.c index d6db93a..33e91d3 100644 --- a/EVT/EXAM/PWR/Standby_RAM_Mode/User/main.c +++ b/EVT/EXAM/PWR/Standby_RAM_Mode/User/main.c @@ -12,11 +12,11 @@ /* *@Note - *when LV is not enabled in standby mode, RAM 2k and 30K low-power data holding routines: - *This routine demonstrates writing data at the specified location of 2K RAM and 30K RAM, - *and then WFI enters STANDBY sleep mode, through the PA0 (wakeup) pin Input high level - *to exit standby mode, print RAM data after waking up, and test whether RAM is maintained - *data. + * when LV is not enabled in standby mode, RAM 2k and 30K data holding routines: + * This routine demonstrates writing data at the specified location of 2K RAM and 30K RAM(Applicable to + * CH32V20x_D8 and CH32V20x_D8W,CH32V20x_D6 has a 20K RAM data holding option),then WFI enters STANDBY + * sleep mode, through the PA0 (wakeup) pin Input high level to exit standby mode, print RAM data after + * waking up, and test whether RAM is maintained data. * */ @@ -29,7 +29,7 @@ /********************************************************************* * @fn TestDataWrite * - * @brief Write 0x11111111 to certain address of 2K RAM and 30K RAM. + * @brief Write data to certain address of 2K RAM and 30K RAM. * * @return none */ @@ -55,7 +55,7 @@ void TestDataWrite(void) { *(uint32_t volatile *)(myAddr2+(i<<2)) = 0x33333333; } - for(i=0;i<10;i++)//Check 30K RAM + for(i=0;i<10;i++)//Check 2K RAM { if((*(uint32_t volatile *)(myAddr2+(i<<2))) != 0x33333333) { @@ -126,16 +126,12 @@ int main(void) /* Delay 1.5s to avoid entering low power mode immediately after reset*/ Delay_Ms(1500); - while(1) - { - TestDataRead(); - printf("3.Stop RAM LV Mode Test\r\n"); - TestDataWrite(); - PWR_WakeUpPinCmd(ENABLE); - PWR_EnterSTANDBYMode_RAM(); - printf("\r\n3.Out \r\n"); - printf("\r\n ########## \r\n"); - } + TestDataRead(); + printf("Standby RAM Mode Test\r\n"); + TestDataWrite(); + PWR_WakeUpPinCmd(ENABLE); + PWR_EnterSTANDBYMode_RAM(); + while(1); } diff --git a/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/PWR/Stop_Mode/User/ch32v20x_it.c b/EVT/EXAM/PWR/Stop_Mode/User/ch32v20x_it.c index ceba22b..a7a9a78 100644 --- a/EVT/EXAM/PWR/Stop_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/PWR/Stop_Mode/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RCC/Get_CLK/User/ch32v20x_it.c b/EVT/EXAM/RCC/Get_CLK/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/RCC/Get_CLK/User/ch32v20x_it.c +++ b/EVT/EXAM/RCC/Get_CLK/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c b/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c index c100ab0..f21c0af 100644 --- a/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c +++ b/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c @@ -114,8 +114,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.c b/EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.c +++ b/EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RCC/HSE_CLK/User/main.c b/EVT/EXAM/RCC/HSE_CLK/User/main.c index 9e4874d..fbff9c9 100644 --- a/EVT/EXAM/RCC/HSE_CLK/User/main.c +++ b/EVT/EXAM/RCC/HSE_CLK/User/main.c @@ -14,8 +14,8 @@ *@Note *HSE frequency check routine: *Checking the frequency value of HSE by using of HSI. - * When HSE is 3 ~ 25M,the HSE clock is effective ,When CH32F20x_D8 and CH32F20x_D6 used. - * When HSE is 32M,the HSE clock is effective ,When CH32F20x_D8C and CH32F20x_D8W used. + * When HSE is 3 ~ 25M,the HSE clock is effective ,When CH32V20x_D6 used. + * When HSE is 32M,the HSE clock is effective ,When CH32V20x_D8 and CH32V20x_D8W used. *HSE value -the frequency of HSE *MCO(PA8) - outputs the HSE clock * diff --git a/EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.c b/EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.c index 49e44df..dda1cbd 100644 --- a/EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.c +++ b/EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.c @@ -6,9 +6,11 @@ * Description : CH32V20x Device Peripheral Access Layer System Source File. * For HSE = 32Mhz (CH32V208x/CH32V203RBT6) * For HSE = 8Mhz (other CH32V203x) + ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - *********************************************************************************/ + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ #include "ch32v20x.h" /* @@ -75,14 +77,19 @@ void SystemCoreClockUpdate(void) { if (pllsource == 0x00) { SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } else { - if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t) RESET) { + } + else + { + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t) RESET) + { #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) SystemCoreClock = ((HSE_VALUE >> 2) >> 1) * pllmull; #else SystemCoreClock = (HSE_VALUE >> 1) * pllmull; #endif - } else { + } + else + { #if defined (CH32V20x_D8) || defined (CH32V20x_D8W) SystemCoreClock = (HSE_VALUE >> 2) * pllmull; #else diff --git a/EVT/EXAM/RCC/HSI_Calibration/User/ch32v20x_it.c b/EVT/EXAM/RCC/HSI_Calibration/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/RCC/HSI_Calibration/User/ch32v20x_it.c +++ b/EVT/EXAM/RCC/HSI_Calibration/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RCC/HSI_Calibration/User/system_ch32v20x.c b/EVT/EXAM/RCC/HSI_Calibration/User/system_ch32v20x.c index 490795d..d2f11d4 100644 --- a/EVT/EXAM/RCC/HSI_Calibration/User/system_ch32v20x.c +++ b/EVT/EXAM/RCC/HSI_Calibration/User/system_ch32v20x.c @@ -114,8 +114,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RCC/HSI_PLL_Source/User/ch32v20x_it.c b/EVT/EXAM/RCC/HSI_PLL_Source/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/RCC/HSI_PLL_Source/User/ch32v20x_it.c +++ b/EVT/EXAM/RCC/HSI_PLL_Source/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RCC/HSI_PLL_Source/User/main.c b/EVT/EXAM/RCC/HSI_PLL_Source/User/main.c index 943ab23..da4c6cb 100644 --- a/EVT/EXAM/RCC/HSI_PLL_Source/User/main.c +++ b/EVT/EXAM/RCC/HSI_PLL_Source/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2024/06/26 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -22,12 +22,6 @@ */ #include "debug.h" -#define HSI 0 //HSI -#define HSI_1_2 1 //HSI/2 - -#define PLL_Source HSI -//#define PLL_Source HSI_1_2 - /********************************************************************* * @fn main * diff --git a/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c b/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c index 0c052bc..d0a1366 100644 --- a/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c +++ b/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c @@ -2,7 +2,7 @@ * File Name : system_ch32v20x.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2024/06/26 * Description : CH32V20x Device Peripheral Access Layer System Source File. * For HSE = 32Mhz (CH32V208x/CH32V203RBT6) * For HSE = 8Mhz (other CH32V203x) @@ -102,8 +102,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.h b/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.h index 9c8a3f7..5263983 100644 --- a/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.h +++ b/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.h @@ -2,7 +2,7 @@ * File Name : system_ch32v20x.h * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2024/06/26 * Description : CH32V20x Device Peripheral Access Layer System Header File. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -16,6 +16,12 @@ extern "C" { #endif +#define HSI 0 //HSI +#define HSI_1_2 1 //HSI/2 + +//#define PLL_Source HSI +#define PLL_Source HSI_1_2 + extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ /* System_Exported_Functions */ diff --git a/EVT/EXAM/RCC/MCO/User/ch32v20x_it.c b/EVT/EXAM/RCC/MCO/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/RCC/MCO/User/ch32v20x_it.c +++ b/EVT/EXAM/RCC/MCO/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c b/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c +++ b/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S index 8439c58..f4e18e1 100644 --- a/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S +++ b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S @@ -3,7 +3,7 @@ ;* Author : WCH ;* Version : V1.0.1 ;* Date : 2024/01/31 -;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 +;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 ;* vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. diff --git a/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c b/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c index c574996..5462329 100644 --- a/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c +++ b/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.c b/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.c index 57010ec..d837684 100644 --- a/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.c +++ b/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RTC/RTC_Calendar/User/main.c b/EVT/EXAM/RTC/RTC_Calendar/User/main.c index e184c96..108f688 100644 --- a/EVT/EXAM/RTC/RTC_Calendar/User/main.c +++ b/EVT/EXAM/RTC/RTC_Calendar/User/main.c @@ -78,7 +78,8 @@ u8 RTC_Init(void) u8 temp = 0; RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); PWR_BackupAccessCmd(ENABLE); - + RTC_ClearITPendingBit(RTC_IT_ALR); + RTC_ClearITPendingBit(RTC_IT_SEC); /* Is it the first configuration */ BKP_DeInit(); @@ -247,7 +248,6 @@ u8 RTC_Get(void) temp -= 366; else { - temp1++; break; } } diff --git a/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c b/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c +++ b/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/RTC/RTC_Calibrations/User/ch32v20x_it.c b/EVT/EXAM/RTC/RTC_Calibrations/User/ch32v20x_it.c index 3b3fb88..e07ee20 100644 --- a/EVT/EXAM/RTC/RTC_Calibrations/User/ch32v20x_it.c +++ b/EVT/EXAM/RTC/RTC_Calibrations/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/RTC/RTC_Calibrations/User/main.c b/EVT/EXAM/RTC/RTC_Calibrations/User/main.c index efd5e7f..f7829b8 100644 --- a/EVT/EXAM/RTC/RTC_Calibrations/User/main.c +++ b/EVT/EXAM/RTC/RTC_Calibrations/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2024/02/22 + * Date : 2024/07/18 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -185,6 +185,7 @@ u8 RTC_Init(void) u8 temp = 0; RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); PWR_BackupAccessCmd(ENABLE); + RTC_ClearITPendingBit(RTC_IT_SEC); /* Is it the first configuration */ @@ -358,7 +359,6 @@ u8 RTC_Get(void) temp -= 366; else { - temp1++; break; } } diff --git a/EVT/EXAM/RTC/RTC_Calibrations/User/system_ch32v20x.c b/EVT/EXAM/RTC/RTC_Calibrations/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/RTC/RTC_Calibrations/User/system_ch32v20x.c +++ b/EVT/EXAM/RTC/RTC_Calibrations/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/User/ch32v20x_it.c b/EVT/EXAM/SDI_Printf/SDI_Printf/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/SDI_Printf/SDI_Printf/User/ch32v20x_it.c +++ b/EVT/EXAM/SDI_Printf/SDI_Printf/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c b/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c +++ b/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/1Lines_half-duplex/User/ch32v20x_it.c b/EVT/EXAM/SPI/1Lines_half-duplex/User/ch32v20x_it.c index 6df2d60..9f863f1 100644 --- a/EVT/EXAM/SPI/1Lines_half-duplex/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/1Lines_half-duplex/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c b/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/2Lines_FullDuplex/User/ch32v20x_it.c b/EVT/EXAM/SPI/2Lines_FullDuplex/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/SPI/2Lines_FullDuplex/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/2Lines_FullDuplex/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c b/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/FullDuplex_HardNSS/User/ch32v20x_it.c b/EVT/EXAM/SPI/FullDuplex_HardNSS/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/SPI/FullDuplex_HardNSS/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/FullDuplex_HardNSS/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c b/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/SPI_CRC/User/ch32v20x_it.c b/EVT/EXAM/SPI/SPI_CRC/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/SPI/SPI_CRC/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/SPI_CRC/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/SPI_DMA/User/ch32v20x_it.c b/EVT/EXAM/SPI/SPI_DMA/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/SPI/SPI_DMA/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/SPI_DMA/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/SPI_FLASH/User/ch32v20x_it.c b/EVT/EXAM/SPI/SPI_FLASH/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/SPI/SPI_FLASH/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/SPI_FLASH/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c +++ b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c index 5c62152..7ad0c33 100644 --- a/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c +++ b/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/SRC/Ld/Link.ld b/EVT/EXAM/SRC/Ld/Link.ld index ff81899..0385dbb 100644 --- a/EVT/EXAM/SRC/Ld/Link.ld +++ b/EVT/EXAM/SRC/Ld/Link.ld @@ -1 +1,187 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /**/ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/**/ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K + + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K + + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +*/ +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h index fc5c540..0d41fc5 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h @@ -2,7 +2,7 @@ * File Name : ch32v20x.h * Author : WCH * Version : V1.0.0 - * Date : 2024/01/31 + * Date : 2024/07/04 * Description : CH32V20x Device Peripheral Access Layer Header File. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -17,7 +17,7 @@ extern "C" { #endif #if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6) -#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/ +#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/ //#define CH32V20x_D8 /* CH32V203RBT6 */ //#define CH32V20x_D8W /* CH32V208 */ @@ -26,10 +26,12 @@ extern "C" { #define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#if defined(CH32V20x_D8) || defined(CH32V20x_D8W) - #define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */ -#else - #define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#ifndef HSE_VALUE + #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) + #define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ + #endif #endif /* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ @@ -39,7 +41,7 @@ extern "C" { /* CH32V20x Standard Peripheral Library version number */ #define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ -#define __CH32V20x_STDPERIPH_VERSION_SUB (0x01) /* [7:0] sub version */ +#define __CH32V20x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */ #define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\ |(__CH32V20x_STDPERIPH_VERSION_SUB << 0)) @@ -53,7 +55,7 @@ typedef enum IRQn Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ - SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ Software_IRQn = 14, /* 14 software Interrupt */ /****** RISC-V specific Interrupt Numbers *********************************************************/ @@ -132,7 +134,7 @@ typedef enum IRQn #define HardFault_IRQn EXC_IRQn #define ADC1_2_IRQn ADC_IRQn - +#define SysTicK_IRQn SysTick_IRQn #define USBHD_IRQn USBFS_IRQn #define USBHDWakeUp_IRQn USBFSWakeUp_IRQn @@ -3168,7 +3170,6 @@ typedef struct #define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ #define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ #define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ -#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ #define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ /******************* Bit definition for FLASH_ADDR register *******************/ @@ -3853,14 +3854,23 @@ typedef struct #define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ #define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ -#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ -#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ -#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ -#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ -#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ -#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ -#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ -#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0 +#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1 +#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2 +#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3 +#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4 +#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5 +#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6 +#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7 #define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h index e92130d..ecd1fb2 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h @@ -33,38 +33,38 @@ typedef enum } FLASH_Status; /* Write Protect */ -#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ -#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */ #define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ @@ -124,7 +124,6 @@ void FLASH_Unlock_Fast(void); void FLASH_Lock_Fast(void); void FLASH_ErasePage_Fast(uint32_t Page_Address); void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); -void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf); void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); void FLASH_Enhance_Mode(FunctionalState NewState); diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h index 04dfb51..658ce11 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h @@ -2,7 +2,7 @@ * File Name : ch32v20x_gpio.h * Author : WCH * Version : V1.0.0 - * Date : 2024/03/02 + * Date : 2024/07/23 * Description : This file contains all the functions prototypes for the * GPIO firmware library. ********************************************************************************* @@ -97,7 +97,7 @@ typedef enum #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */ #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ @@ -112,6 +112,7 @@ typedef enum to TIM2 Internal Trigger 1 for calibration \ (only for Connectivity line devices) */ #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ +#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1 /* PCFR2 */ #define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_pwr.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_pwr.h index 8758788..99014ca 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_pwr.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_pwr.h @@ -20,14 +20,24 @@ extern "C" { #include "ch32v20x.h" /* PVD_detection_level */ -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) + +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + +#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7 /* Regulator_state_is_STOP_mode */ #define PWR_Regulator_ON ((uint32_t)0x00000000) diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h index 343006c..33cc90e 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h @@ -92,7 +92,7 @@ typedef struct #define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01) #define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02) -#ifdef CH32V20x_D8W +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) #define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03) #endif @@ -250,6 +250,7 @@ void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); void RCC_ADCCLKADJcmd(FunctionalState NewState); +FlagStatus RCC_USB5PRE_JUDGE(); #if defined(CH32V20x_D8) || defined(CH32V20x_D8W) void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div); diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_dbgmcu.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_dbgmcu.c index 13f08d7..2b2aef9 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_dbgmcu.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_dbgmcu.c @@ -109,7 +109,6 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * CH32V203C8T6-0x203105x0 * CH32V203K8T6-0x203205x0 * CH32V203C6T6-0x203305x0 - * CH32V203K6T6-0x203505x0 * CH32V203G6U6-0x203605x0 * CH32V203G8R6-0x203B05x0 * CH32V203F8U6-0x203E05x0 diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c index c5e3182..2bb2914 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c @@ -28,7 +28,6 @@ #define CR_PAGE_PG ((uint32_t)0x00010000) #define CR_PAGE_ER ((uint32_t)0x00020000) #define CR_BER32 ((uint32_t)0x00040000) -#define CR_BER64 ((uint32_t)0x00080000) #define CR_PG_STRT ((uint32_t)0x00200000) /* FLASH Status Register bits */ @@ -521,6 +520,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint uint32_t Addr = 0x1FFFF800; __IO uint8_t i; uint16_t pbuf[8]; + uint16_t temp; FLASH->OBKEYR = FLASH_KEY1; FLASH->OBKEYR = FLASH_KEY2; @@ -533,6 +533,8 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint pbuf[i] = *(uint16_t *)(Addr + 2 * i); } + temp=pbuf[1]&(~0x7); + /* Erase optionbytes */ FLASH->CTLR |= CR_OPTER_Set; FLASH->CTLR |= CR_STRT_Set; @@ -540,7 +542,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint FLASH->CTLR &= ~CR_OPTER_Set; /* Write optionbytes */ - pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)temp))); FLASH->CTLR |= CR_OPTPG_Set; for(i = 0; i < 8; i++){ @@ -864,26 +866,6 @@ void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) FLASH->CTLR &= ~CR_BER32; } -/********************************************************************* - * @fn FLASH_EraseBlock_64K_Fast - * - * @brief Erases a specified FLASH Block (1Block = 64KByte). - * - * @param Block_Address - The block address to be erased. - * - * @return none - */ -void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address) -{ - Block_Address &= 0xFFFF0000; - - FLASH->CTLR |= CR_BER64; - FLASH->ADDR = Block_Address; - FLASH->CTLR |= CR_STRT_Set; - while(FLASH->STATR & SR_BSY); - FLASH->CTLR &= ~CR_BER64; -} - /********************************************************************* * @fn FLASH_ProgramPage_Fast * diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c index 675552e..47956e3 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c @@ -509,7 +509,7 @@ void GPIO_EventOutputCmd(FunctionalState NewState) * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping @@ -840,34 +840,6 @@ void GPIO_IPD_Unused(void) GPIO_Init(GPIOD, &GPIO_InitStructure); break; } - case 0x20350500: //CH32V203K6T6 - { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_11\ - |GPIO_Pin_12|GPIO_Pin_13\ - |GPIO_Pin_14|GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ - |GPIO_Pin_2|GPIO_Pin_3\ - |GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6|GPIO_Pin_7\ - |GPIO_Pin_8|GPIO_Pin_9\ - |GPIO_Pin_10|GPIO_Pin_11\ - |GPIO_Pin_12|GPIO_Pin_13\ - |GPIO_Pin_14|GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ - |GPIO_Pin_4|GPIO_Pin_5\ - |GPIO_Pin_6; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOD, &GPIO_InitStructure); - break; - } case 0x20320500: //CH32V203K8T6 { GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_pwr.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_pwr.c index e97c6ba..f984d79 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_pwr.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_pwr.c @@ -81,14 +81,14 @@ void PWR_PVDCmd(FunctionalState NewState) * Detector(PVD). * * @param PWR_PVDLevel - specifies the PVD detection level - * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V - * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V - * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V - * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V - * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V - * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V - * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V - * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. * * @return none */ diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rcc.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rcc.c index 12bb140..2de8bc4 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rcc.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rcc.c @@ -585,8 +585,8 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>1)) * pllmull; } @@ -1028,5 +1028,34 @@ void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div) RCC->CFGR0 |= RCC_ETHPRE_Div<<28; } +/********************************************************************* + * @fn RCC_USB5PRE_JUDGE() + * + * @brief Judge MCU supports PLLCLK/5 for USB. + * + * @param FlagStatus - SET or RESET. + * SET - support + * RESET - not support + * @return none + */ +FlagStatus RCC_USB5PRE_JUDGE() +{ + +#if defined (CH32V20x_D8W) + return SET; +#elif defined (CH32V20x_D8) + RCC->AHBPCENR |= (1<<17); + *(vu32*)0x400250A0 = 0x55aaaa55; + if(*(vu32*)0x400250A0 == 0x55aaaa55) + { + return SET; + } + else + { + return RESET; + } +#endif + return RESET; +} diff --git a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S index f0895e2..d723a5d 100644 --- a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S +++ b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S @@ -3,7 +3,7 @@ ;* Author : WCH ;* Version : V1.0.1 ;* Date : 2024/01/31 -;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 +;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 ;* vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. diff --git a/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/ch32v20x_it.c b/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/ch32v20x_it.c +++ b/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c b/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c +++ b/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/Clock_Select/User/ch32v20x_it.c b/EVT/EXAM/TIM/Clock_Select/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/TIM/Clock_Select/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/Clock_Select/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c b/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/ch32v20x_it.c b/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c b/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/Encoder/User/ch32v20x_it.c b/EVT/EXAM/TIM/Encoder/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/TIM/Encoder/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/Encoder/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/Encoder/User/system_ch32v20x.c b/EVT/EXAM/TIM/Encoder/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/Encoder/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/Encoder/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/ch32v20x_it.c b/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c b/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c b/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c index de6cc37..cc73870 100644 --- a/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c b/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/One_Pulse/User/ch32v20x_it.c b/EVT/EXAM/TIM/One_Pulse/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/TIM/One_Pulse/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/One_Pulse/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c b/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/Output_Compare_Mode/User/ch32v20x_it.c b/EVT/EXAM/TIM/Output_Compare_Mode/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/TIM/Output_Compare_Mode/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/Output_Compare_Mode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c b/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/PWM_Output/User/ch32v20x_it.c b/EVT/EXAM/TIM/PWM_Output/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/TIM/PWM_Output/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/PWM_Output/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c b/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/Synchro_ExtTrigger/User/ch32v20x_it.c b/EVT/EXAM/TIM/Synchro_ExtTrigger/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/TIM/Synchro_ExtTrigger/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/Synchro_ExtTrigger/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c b/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/Synchro_Timer/User/ch32v20x_it.c b/EVT/EXAM/TIM/Synchro_Timer/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/TIM/Synchro_Timer/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/Synchro_Timer/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c b/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/TIM_DMA/User/ch32v20x_it.c b/EVT/EXAM/TIM/TIM_DMA/User/ch32v20x_it.c index 2b99375..40c8927 100644 --- a/EVT/EXAM/TIM/TIM_DMA/User/ch32v20x_it.c +++ b/EVT/EXAM/TIM/TIM_DMA/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c b/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c +++ b/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TIM/TIM_INT/.cproject b/EVT/EXAM/TIM/TIM_INT/.cproject new file mode 100644 index 0000000..731e1b5 --- /dev/null +++ b/EVT/EXAM/TIM/TIM_INT/.cproject @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EVT/EXAM/TIM/TIM_INT/.project b/EVT/EXAM/TIM/TIM_INT/.project new file mode 100644 index 0000000..f405a26 --- /dev/null +++ b/EVT/EXAM/TIM/TIM_INT/.project @@ -0,0 +1,61 @@ + + + TIM_INT + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + + + Core + 2 + PARENT-2-PROJECT_LOC/SRC/Core + + + Debug + 2 + PARENT-2-PROJECT_LOC/SRC/Debug + + + Ld + 2 + PARENT-2-PROJECT_LOC/SRC/Ld + + + Peripheral + 2 + PARENT-2-PROJECT_LOC/SRC/Peripheral + + + Startup + 2 + PARENT-2-PROJECT_LOC/SRC/Startup + + + diff --git a/EVT/EXAM/TIM/TIM_INT/.template b/EVT/EXAM/TIM/TIM_INT/.template new file mode 100644 index 0000000..5aa87d5 --- /dev/null +++ b/EVT/EXAM/TIM/TIM_INT/.template @@ -0,0 +1,18 @@ +Vendor=WCH +Toolchain=RISC-V +Series=CH32V203 +RTOS=NoneOS +MCU=CH32V203RBT6 +Link=WCH-Link +PeripheralVersion==1.0 +Description==ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. +Mcu Type=CH32V20x +Address=0x08000000 +Target Path=obj\TIM_INT.hex +CLKSpeed=1 +DebugInterfaceMode=-1 +Erase All=true +Program=true +Verify=true +Reset=true +SDIPrintf=false diff --git a/EVT/EXAM/TIM/TIM_INT/TIM_INT.wvproj b/EVT/EXAM/TIM/TIM_INT/TIM_INT.wvproj new file mode 100644 index 0000000..2cd99d9 --- /dev/null +++ b/EVT/EXAM/TIM/TIM_INT/TIM_INT.wvproj @@ -0,0 +1,2 @@ +iCZ ?"ǁrF<.ſ?/XOĿChQN$*EBk!2t+buhnUb]xll| ++"CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF0FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) + { + SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull; +#else + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; +#endif + } + else + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = (HSE_VALUE>>2) * pllmull; +#else + SystemCoreClock = HSE_VALUE * pllmull; +#endif + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source + * CH32V20x_D6 (HSE=8MHZ) + * CH32V20x_D8 (HSE=32MHZ) + * CH32V20x_D8W (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { +#if defined (CH32V20x_D8W) + RCC->CFGR0 |= (uint32_t)(3<<22); + /* HCLK = SYSCLK/2 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; +#else + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +#endif + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#endif diff --git a/EVT/EXAM/TIM/TIM_INT/User/system_ch32v20x.h b/EVT/EXAM/TIM/TIM_INT/User/system_ch32v20x.h new file mode 100644 index 0000000..9c8a3f7 --- /dev/null +++ b/EVT/EXAM/TIM/TIM_INT/User/system_ch32v20x.h @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32v20x_H +#define __SYSTEM_ch32v20x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V20x_SYSTEM_H */ + + + diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c +++ b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c b/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c +++ b/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S index d70b5fd..aaa76c5 100644 --- a/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S +++ b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S @@ -3,7 +3,7 @@ ;* Author : WCH ;* Version : V1.0.1 ;* Date : 2024/01/31 -;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 +;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8 ;* vector table for eclipse toolchain. ;********************************************************************************* ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. diff --git a/EVT/EXAM/TencentOS/TencentOS/User/ch32v20x_it.c b/EVT/EXAM/TencentOS/TencentOS/User/ch32v20x_it.c index af2b89a..76aada1 100644 --- a/EVT/EXAM/TencentOS/TencentOS/User/ch32v20x_it.c +++ b/EVT/EXAM/TencentOS/TencentOS/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c b/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c +++ b/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_DMA/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_DMA/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_DMA/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_DMA/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_HalfDuplex/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_HalfDuplex/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_HalfDuplex/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_HalfDuplex/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_HardwareFlowControl/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_HardwareFlowControl/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_HardwareFlowControl/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_HardwareFlowControl/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c index 897db0f..391ff26 100644 --- a/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_Interrupt/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_Interrupt/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_Interrupt/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_Interrupt/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_Polling/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_Polling/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_Polling/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_Polling/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_Printf/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_Printf/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_Printf/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_Printf/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c index f2598c2..c0d0fdf 100644 --- a/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c @@ -34,6 +34,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_SmartCard/User/main.c b/EVT/EXAM/USART/USART_SmartCard/User/main.c index 6044a5a..b02429e 100644 --- a/EVT/EXAM/USART/USART_SmartCard/User/main.c +++ b/EVT/EXAM/USART/USART_SmartCard/User/main.c @@ -341,7 +341,7 @@ int main(void) { uint8_t recvbuf[ATR_MAX_SIZE] = {0}; uint16_t recvpos = 0; - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); SystemCoreClockUpdate(); Delay_Init(); USART_Printf_Init(115200); diff --git a/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c index 2846805..22439f4 100644 --- a/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USART/USART_SynchronousMode/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_SynchronousMode/User/ch32v20x_it.c index 13c75eb..e3dff91 100644 --- a/EVT/EXAM/USART/USART_SynchronousMode/User/ch32v20x_it.c +++ b/EVT/EXAM/USART/USART_SynchronousMode/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c +++ b/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/hw_config.c index 1f6e82f..39f3763 100644 --- a/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/hw_config.c @@ -55,19 +55,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/CH372/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/CH372/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBD/CH372/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/CH372/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/CH372/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/CH372/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBD/CH372/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/CH372/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/hw_config.c index d0f68d1..c0873bc 100644 --- a/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/hw_config.c @@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/CompatibilityHID/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/CompatibilityHID/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBD/CompatibilityHID/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/CompatibilityHID/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/CompatibilityHID/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/CompatibilityHID/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBD/CompatibilityHID/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/CompatibilityHID/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c index 89b9f9e..7843538 100644 --- a/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c @@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/CompositeKM/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/CompositeKM/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBD/CompositeKM/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/CompositeKM/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/CompositeKM/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/CompositeKM/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBD/CompositeKM/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/CompositeKM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/hw_config.c index 680d676..96c6b9f 100644 --- a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/hw_config.c @@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/system_ch32v20x.c index 358bdc6..b52c4ee 100644 --- a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/hw_config.c index 680d676..96c6b9f 100644 --- a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/hw_config.c @@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/hw_config.c index dd14a22..ea1b47d 100644 --- a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/hw_config.c @@ -55,19 +55,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/ch32v20x_it.c index dc61129..c6a7c85 100644 --- a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/ch32v20x_it.c @@ -55,6 +55,7 @@ void TIM2_IRQHandler( void ) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/hw_config.c index dd14a22..ea1b47d 100644 --- a/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/hw_config.c +++ b/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/hw_config.c @@ -55,19 +55,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void) */ void Set_USBConfig( ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); } /******************************************************************************* diff --git a/EVT/EXAM/USB/USBD/SimulateCDC/User/ch32v20x_it.c b/EVT/EXAM/USB/USBD/SimulateCDC/User/ch32v20x_it.c index dc61129..c6a7c85 100644 --- a/EVT/EXAM/USB/USBD/SimulateCDC/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBD/SimulateCDC/User/ch32v20x_it.c @@ -55,6 +55,7 @@ void TIM2_IRQHandler( void ) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBD/SimulateCDC/User/system_ch32v20x.c b/EVT/EXAM/USB/USBD/SimulateCDC/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBD/SimulateCDC/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBD/SimulateCDC/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject index d1fcf8a..221f63f 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject +++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject @@ -1,143 +1,541 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.project b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.project index 2e6259b..0d68afe 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.project +++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.project @@ -20,42 +20,41 @@ org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + Core + 2 + PARENT-4-PROJECT_LOC/SRC/Core + + + Debug + 2 + PARENT-4-PROJECT_LOC/SRC/Debug + + + Ld + 2 + PARENT-4-PROJECT_LOC/SRC/Ld + + + Peripheral + 2 + PARENT-4-PROJECT_LOC/SRC/Peripheral + + + Startup + 2 + PARENT-4-PROJECT_LOC/SRC/Startup + + - 1595986042669 - 22 + 6 org.eclipse.ui.ide.multiFilter 1.0-name-matches-false-false-*.wvproj - - - Core - 2 - PARENT-4-PROJECT_LOC/SRC/Core - - - Debug - 2 - PARENT-4-PROJECT_LOC/SRC/Debug - - - Ld - 2 - PARENT-4-PROJECT_LOC/SRC/Ld - - - Peripheral - 2 - PARENT-4-PROJECT_LOC/SRC/Peripheral - - - Startup - 2 - PARENT-4-PROJECT_LOC/SRC/Startup - - - + \ No newline at end of file diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.template b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.template index ac7eac3..6019f23 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.template +++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.template @@ -1,16 +1,23 @@ +Vendor=WCH +Toolchain=RISC-V +Series=CH32V203 +RTOS=NoneOS +MCU=CH32V203RBT6 +Link=WCH-Link +PeripheralVersion=1.0 +Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. Mcu Type=CH32V20x Address=0x08000000 Target Path=obj/CH372Device.hex +Exe Path= +Exe Arguments= +CLKSpeed=1 +DebugInterfaceMode=0 Erase All=true Program=true Verify=true Reset=true - -Vendor=WCH -Link=WCH-Link -Toolchain=RISC-V -Series=CH32V203 -Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. - -PeripheralVersion=1.0 -MCU=CH32V203RBT6 +SDIPrintf=false +Disable Power Output=false +Clear CodeFlash=false +Disable Code-Protect=false \ No newline at end of file diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/CH372Device.wvproj b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/CH372Device.wvproj index 2cd99d9..cfda910 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/CH372Device.wvproj +++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/CH372Device.wvproj @@ -1,2 +1,709 @@ -iCZ ?"ǁrF<.ſ?/XOĿChQN$*EBk!2t+buhnUb]xll| -+"CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } @@ -624,7 +624,7 @@ static void SetSysClockTo120_HSE(void) if(HSEStatus == (uint32_t)0x01) { -#if defined (CH32V20x_D8W) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) RCC->CFGR0 |= (uint32_t)(3<<22); /* HCLK = SYSCLK/2 */ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c index e779575..cd51cdb 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c @@ -54,24 +54,32 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Set USB clock. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c index 02ec433..d8d0b92 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c @@ -54,24 +54,32 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Set USB clock. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c index 343266f..f4c8a06 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c @@ -51,18 +51,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_it.c index e010214..83b49c8 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c index 64408f2..4e2f6fa 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c @@ -51,18 +51,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c index 5ac64b5..1648e1f 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c @@ -61,18 +61,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/ch32v20x_it.c index be7bd33..61a992b 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/ch32v20x_it.c @@ -60,6 +60,7 @@ void TIM2_IRQHandler( void ) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c index 9869a55..3bdb315 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c @@ -52,18 +52,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/ch32v20x_it.c index be7bd33..61a992b 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/ch32v20x_it.c @@ -60,6 +60,7 @@ void TIM2_IRQHandler( void ) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/APP/Ld_APP/Link.ld b/EVT/EXAM/USB/USBFS/HOST_IAP/APP/Ld_APP/Link.ld index e8ab385..984b85d 100644 --- a/EVT/EXAM/USB/USBFS/HOST_IAP/APP/Ld_APP/Link.ld +++ b/EVT/EXAM/USB/USBFS/HOST_IAP/APP/Ld_APP/Link.ld @@ -1 +1,192 @@ -ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K */ /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /**/ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ FLASH (rx) : ORIGIN = 0x00005000, LENGTH = 44K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K +*/ + +/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ +/**/ +/* + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +*/ + FLASH (rx) : ORIGIN = 0x00005000, LENGTH = 44K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K + +/* CH32V20x_D8 - CH32V203RB + CH32V20x_D8W - CH32V208x + FLASH + RAM supports the following configuration + FLASH-128K + RAM-64K + FLASH-144K + RAM-48K + FLASH-160K + RAM-32K + + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +*/ +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/ch32v20x_it.c index ac07483..3dddda0 100644 --- a/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/ch32v20x_it.c @@ -36,6 +36,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/USB_Host/ch32v20x_usbfs_host.c b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/USB_Host/ch32v20x_usbfs_host.c index a567de4..df3327f 100644 --- a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/USB_Host/ch32v20x_usbfs_host.c +++ b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/USB_Host/ch32v20x_usbfs_host.c @@ -23,24 +23,32 @@ __attribute__((aligned(4))) uint8_t TxBuffer[ MAX_PACKET_SIZE ]; // O /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Set USB port clock. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } /********************************************************************* diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_it.c index 6a23626..2c83414 100644 --- a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_it.c @@ -38,6 +38,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c b/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c index 931a505..b0c6a45 100644 --- a/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c +++ b/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c @@ -23,26 +23,32 @@ __attribute__((aligned(4))) uint8_t USBFS_TX_Buf[ USBFS_MAX_PACKET_SIZE ]; /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Set USB port clock. - * Note: If the SystemCoreClock is selected as the USB clock source, - * only the frequency specified below can be used. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } /********************************************************************* diff --git a/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_it.c index ac07483..3dddda0 100644 --- a/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_it.c @@ -36,6 +36,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/HOST_KM/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/HOST_KM/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/HOST_KM/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/HOST_KM/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c index 931a505..b0c6a45 100644 --- a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c +++ b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c @@ -23,26 +23,32 @@ __attribute__((aligned(4))) uint8_t USBFS_TX_Buf[ USBFS_MAX_PACKET_SIZE ]; /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Set USB port clock. - * Note: If the SystemCoreClock is selected as the USB clock source, - * only the frequency specified below can be used. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } /********************************************************************* diff --git a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_it.c index ac07483..3dddda0 100644 --- a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_it.c @@ -36,6 +36,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/USB_Host/ch32v20x_usbfs_host.c b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/USB_Host/ch32v20x_usbfs_host.c index a567de4..df3327f 100644 --- a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/USB_Host/ch32v20x_usbfs_host.c +++ b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/USB_Host/ch32v20x_usbfs_host.c @@ -23,24 +23,32 @@ __attribute__((aligned(4))) uint8_t TxBuffer[ MAX_PACKET_SIZE ]; // O /********************************************************************* * @fn USBFS_RCC_Init * - * @brief Set USB port clock. + * @brief Initializes the usbfs clock configuration. * * @return none */ void USBFS_RCC_Init( void ) { - if( SystemCoreClock == 144000000 ) + RCC_ClocksTypeDef RCC_ClocksStatus={0}; + RCC_GetClocksFreq(&RCC_ClocksStatus); + if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 ); } - else if( SystemCoreClock == 96000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 ); } - else if( SystemCoreClock == 48000000 ) + else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) { RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 ); } +#if defined(CH32V20x_D8W) || defined(CH32V20x_D8) + else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET ) + { + RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 ); + } +#endif RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE ); } /********************************************************************* diff --git a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_it.c b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_it.c index ac07483..3dddda0 100644 --- a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_it.c +++ b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_it.c @@ -36,6 +36,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/system_ch32v20x.c b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/system_ch32v20x.c index 913d4d9..19aa375 100644 --- a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/system_ch32v20x.c +++ b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; } diff --git a/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.c b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.c index 3d10863..8fcb613 100644 --- a/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.c +++ b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.c @@ -37,6 +37,7 @@ void NMI_Handler(void) */ void HardFault_Handler(void) { + NVIC_SystemReset(); while (1) { } diff --git a/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c b/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c index 0de9dce..7ffbdb4 100644 --- a/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c +++ b/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c @@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void) } else { -#if defined (CH32V20x_D8W) - if((RCC->CFGR0 & (3<<22)) == (3<<22)) +#if defined (CH32V20x_D8W) || defined (CH32V20x_D8) + if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET)) { SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; }