update 1.8
This commit is contained in:
qiyongshuang
@@ -0,0 +1,239 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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|
||||
<entry excluding="Startup/startup_ch32v20x_D6.S|Startup/startup_ch32v20x_D8.S|Startup/startup_ch32v20x.S|LiteOS/components/cppsupport|User/task_sample.c|LiteOS/kal|LiteOS/third_party/cmsis/CMSIS/Core|LiteOS/components/exchook|LiteOS/third_party/cmsis|User/task_sample.h|LiteOS/components/net|LiteOS/testsuits|LiteOS/components/fs" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
|
||||
</cproject>
|
||||
@@ -0,0 +1,59 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<projectDescription>
|
||||
<name>MAC_RAW</name>
|
||||
<comment/>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>Core</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/SRC/Core</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Debug</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/SRC/Debug</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Peripheral</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/SRC/Peripheral</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Startup</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/SRC/Startup</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>1595986042669</id>
|
||||
<name/>
|
||||
<type>22</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
</filteredResources>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,16 @@
|
||||
Mcu Type=CH32V20x
|
||||
Address=0x08000000
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=true
|
||||
Reset=true
|
||||
|
||||
Vendor=WCH
|
||||
Link=WCH-Link
|
||||
Toolchain=RISC-V
|
||||
Series=CH32V203
|
||||
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||
|
||||
PeripheralVersion=1.0
|
||||
MCU=CH32V203RBT6
|
||||
Target Path=obj/MAC_RAW.hex
|
||||
@@ -0,0 +1,633 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : eth_driver.c
|
||||
* Author : WCH
|
||||
* Version : V1.3.0
|
||||
* Date : 2022/05/26
|
||||
* Description : eth program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "string.h"
|
||||
#include "eth_driver.h"
|
||||
|
||||
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
|
||||
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
|
||||
|
||||
__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
|
||||
__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
|
||||
|
||||
ETH_DMADESCTypeDef *pDMARxSet;
|
||||
ETH_DMADESCTypeDef *pDMATxSet;
|
||||
ETH_DMADESCTypeDef *DMATxDescToSet;
|
||||
ETH_DMADESCTypeDef *DMARxDescToGet;
|
||||
|
||||
volatile uint8_t LinkSta = 0; //0: No valid link established 1:Valid link establishe
|
||||
volatile uint8_t phyLinkReset;
|
||||
volatile uint32_t phyLinkTime;
|
||||
volatile uint32_t LocalTime;
|
||||
uint8_t phyPN = 0x01;
|
||||
uint8_t phyStatus = 0;
|
||||
uint8_t phySucCnt = 0;
|
||||
uint8_t phyLinkCnt = 0;
|
||||
uint8_t phyRetryCnt = 0;
|
||||
uint8_t CRCErrPktCnt = 0;
|
||||
uint8_t phyLinkStatus = 0;
|
||||
uint8_t phyPNChangeCnt = 0;
|
||||
uint8_t PhyPolarityDetect = 0;
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_GetMacAddr
|
||||
*
|
||||
* @brief Get MAC address
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void WCHNET_GetMacAddr( uint8_t *p )
|
||||
{
|
||||
uint8_t i;
|
||||
uint8_t *macaddr=(uint8_t *)(ROM_CFG_USERADR_ID+5);
|
||||
|
||||
for(i=0;i<6;i++)
|
||||
{
|
||||
*p = *macaddr;
|
||||
p++;
|
||||
macaddr--;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_TimeIsr
|
||||
*
|
||||
* @brief
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void WCHNET_TimeIsr( uint16_t timperiod )
|
||||
{
|
||||
LocalTime += timperiod;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WritePHYReg
|
||||
*
|
||||
* @brief MCU write PHY register.
|
||||
*
|
||||
* @param reg_add - PHY address,
|
||||
* reg_val - value you want to write.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WritePHYReg(uint8_t reg_add,uint16_t reg_val)
|
||||
{
|
||||
R32_ETH_MIWR = (reg_add & RB_ETH_MIREGADR_MIRDL) | (1<<8) | (reg_val<<16);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ReadPHYReg
|
||||
*
|
||||
* @brief MCU read PHY register.
|
||||
*
|
||||
* @param reg_add - PHY address.
|
||||
*
|
||||
* @return value you want to get.
|
||||
*/
|
||||
uint16_t ReadPHYReg(uint8_t reg_add)
|
||||
{
|
||||
R8_ETH_MIREGADR = reg_add; // write address
|
||||
return R16_ETH_MIRD; // get data
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_LinkProcess
|
||||
*
|
||||
* @brief link process.
|
||||
*
|
||||
* @param none.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void WCHNET_LinkProcess( void )
|
||||
{
|
||||
uint16_t phy_anlpar, phy_bmcr, phy_bmsr;
|
||||
|
||||
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
|
||||
phy_bmsr = ReadPHYReg(PHY_BMSR);
|
||||
|
||||
if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) )
|
||||
{
|
||||
if( !(phyLinkStatus&PHY_LINK_WAIT_SUC) )
|
||||
{
|
||||
if( (phyPN&0x0C) == PHY_PN_SWITCH_P )
|
||||
{
|
||||
phySucCnt = 0;
|
||||
phyLinkCnt = 0;
|
||||
phyLinkStatus = PHY_LINK_WAIT_SUC;
|
||||
}
|
||||
else
|
||||
{
|
||||
if( !(phyLinkStatus&PHY_LINK_SUC_N) )
|
||||
{
|
||||
phyRetryCnt = 0;
|
||||
phyLinkStatus |= PHY_LINK_SUC_N;
|
||||
phyPN &= ~PHY_PN_SWITCH_N;
|
||||
phy_bmcr = ReadPHYReg(PHY_BMCR);
|
||||
phy_bmcr |= 1<<9;
|
||||
WritePHYReg(PHY_BMCR, phy_bmcr);
|
||||
WritePHYReg(PHY_MDIX, phyPN);
|
||||
}
|
||||
else
|
||||
{
|
||||
phySucCnt = 0;
|
||||
phyLinkCnt = 0;
|
||||
phyLinkStatus = PHY_LINK_WAIT_SUC;
|
||||
}
|
||||
}
|
||||
}
|
||||
else{
|
||||
if((phySucCnt++ == 5) && ((phy_bmsr&(1<<5)) == 0))
|
||||
{
|
||||
phySucCnt = 0;
|
||||
phyRetryCnt = 0;
|
||||
phyPNChangeCnt = 0;
|
||||
phyLinkStatus = PHY_LINK_INIT;
|
||||
phy_bmcr = ReadPHYReg(PHY_BMCR);
|
||||
phy_bmcr |= 1<<9;
|
||||
WritePHYReg(PHY_BMCR, phy_bmcr);
|
||||
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
|
||||
{
|
||||
phyPN |= PHY_PN_SWITCH_N;
|
||||
}
|
||||
else {
|
||||
phyPN &= ~PHY_PN_SWITCH_N;
|
||||
}
|
||||
WritePHYReg(PHY_MDIX, phyPN);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if( phyLinkStatus == PHY_LINK_WAIT_SUC )
|
||||
{
|
||||
if(phyLinkCnt++ == 10)
|
||||
{
|
||||
phyLinkCnt = 0;
|
||||
phyRetryCnt = 0;
|
||||
phyPNChangeCnt = 0;
|
||||
phyLinkStatus = PHY_LINK_INIT;
|
||||
}
|
||||
}
|
||||
else if(phyLinkStatus == PHY_LINK_INIT)
|
||||
{
|
||||
if(phyPNChangeCnt++ == 10)
|
||||
{
|
||||
phyPNChangeCnt = 0;
|
||||
phyPN = ReadPHYReg(PHY_MDIX);
|
||||
phyPN &= ~0x0c;
|
||||
phyPN ^= 0x03;
|
||||
WritePHYReg(PHY_MDIX, phyPN);
|
||||
}
|
||||
else{
|
||||
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
|
||||
{
|
||||
phyPN |= PHY_PN_SWITCH_N;
|
||||
}
|
||||
else {
|
||||
phyPN &= ~PHY_PN_SWITCH_N;
|
||||
}
|
||||
WritePHYReg(PHY_MDIX, phyPN);
|
||||
}
|
||||
}
|
||||
else if(phyLinkStatus == PHY_LINK_SUC_N)
|
||||
{
|
||||
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
|
||||
{
|
||||
phyPN |= PHY_PN_SWITCH_N;
|
||||
phy_bmcr = ReadPHYReg(PHY_BMCR);
|
||||
phy_bmcr |= 1<<9;
|
||||
WritePHYReg(PHY_BMCR, phy_bmcr);
|
||||
Delay_Us(10);
|
||||
WritePHYReg(PHY_MDIX, phyPN);
|
||||
}
|
||||
else{
|
||||
if(phyRetryCnt++ == 15)
|
||||
{
|
||||
phyRetryCnt = 0;
|
||||
phyPNChangeCnt = 0;
|
||||
phyLinkStatus = PHY_LINK_INIT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_PhyPNProcess
|
||||
*
|
||||
* @brief Phy PN Polarity related processing
|
||||
*
|
||||
* @param none.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void WCHNET_PhyPNProcess(void)
|
||||
{
|
||||
uint32_t PhyVal;
|
||||
|
||||
phyLinkTime = LocalTime;
|
||||
if(CRCErrPktCnt >= 3)
|
||||
{
|
||||
PhyVal = ReadPHYReg(PHY_MDIX);
|
||||
if((PhyVal >> 2) & 0x01)
|
||||
PhyVal &= ~(3 << 2); //change PHY PN Polarity to normal
|
||||
else
|
||||
PhyVal |= 1 << 2; //change PHY PN Polarity to reverse
|
||||
WritePHYReg(PHY_MDIX, PhyVal);
|
||||
CRCErrPktCnt = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_HandlePhyNegotiation
|
||||
*
|
||||
* @brief Handle PHY Negotiation.
|
||||
*
|
||||
* @param none.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void WCHNET_HandlePhyNegotiation(void)
|
||||
{
|
||||
if(phyLinkReset) /* After the PHY link is disconnected, wait 500ms before turning on the PHY clock*/
|
||||
{
|
||||
if( LocalTime - phyLinkTime >= 500 )
|
||||
{
|
||||
phyLinkReset = 0;
|
||||
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
|
||||
WritePHYReg(PHY_BMCR, PHY_Reset);
|
||||
PHY_NEGOTIATION_PARAM_INIT();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if( !phyStatus ) /* Handling PHY Negotiation Exceptions */
|
||||
{
|
||||
if( LocalTime - phyLinkTime >= PHY_LINK_TASK_PERIOD ) /* 50ms cycle timing call */
|
||||
{
|
||||
phyLinkTime = LocalTime;
|
||||
WCHNET_LinkProcess( );
|
||||
}
|
||||
}
|
||||
else{
|
||||
if(PhyPolarityDetect)
|
||||
{
|
||||
if( LocalTime - phyLinkTime >= 2 * PHY_LINK_TASK_PERIOD )
|
||||
{
|
||||
WCHNET_PhyPNProcess();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RecDataPolling
|
||||
*
|
||||
* @brief process received data.
|
||||
*
|
||||
* @param none.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void RecDataPolling(void)
|
||||
{
|
||||
uint32_t length, buffer;
|
||||
|
||||
while(!(pDMARxSet->Status & ETH_DMARxDesc_OWN))
|
||||
{
|
||||
if( !(pDMARxSet->Status & ETH_DMARxDesc_ES) &&\
|
||||
(pDMARxSet->Status & ETH_DMARxDesc_LS) &&\
|
||||
(pDMARxSet->Status & ETH_DMARxDesc_FS) )
|
||||
{
|
||||
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
||||
length = ((pDMARxSet->Status & ETH_DMARxDesc_FL) >> 16) - 4;
|
||||
/* Get the addrees of the actual buffer */
|
||||
buffer = pDMARxSet->Buffer1Addr;
|
||||
|
||||
/* Do something*/
|
||||
printf("rec data:%d bytes\r\n",length);
|
||||
printf("data:%x\r\n",*((uint8_t *)buffer));
|
||||
}
|
||||
pDMARxSet->Status = ETH_DMARxDesc_OWN;
|
||||
pDMARxSet = (ETH_DMADESCTypeDef *)pDMARxSet->Buffer2NextDescAddr;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_MainTask
|
||||
*
|
||||
* @brief library main task function
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void WCHNET_MainTask(void)
|
||||
{
|
||||
WCHNET_HandlePhyNegotiation( );
|
||||
RecDataPolling();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_DMATxDescChainInit
|
||||
*
|
||||
* @brief Initializes the DMA Tx descriptors in chain mode.
|
||||
*
|
||||
* @param DMATxDescTab - Pointer on the first Tx desc list
|
||||
* TxBuff - Pointer on the first TxBuffer list
|
||||
* TxBuffCount - Number of the used Tx desc in the list
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
|
||||
{
|
||||
ETH_DMADESCTypeDef *DMATxDesc;
|
||||
|
||||
DMATxDescToSet = DMATxDescTab;
|
||||
DMATxDesc = DMATxDescTab;
|
||||
DMATxDesc->Status = 0;
|
||||
DMATxDesc->Buffer1Addr = (uint32_t)TxBuff;
|
||||
DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_DMARxDescChainInit
|
||||
*
|
||||
* @brief Initializes the DMA Rx descriptors in chain mode.
|
||||
*
|
||||
* @param DMARxDescTab - Pointer on the first Rx desc list.
|
||||
* RxBuff - Pointer on the first RxBuffer list.
|
||||
* RxBuffCount - Number of the used Rx desc in the list.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
ETH_DMADESCTypeDef *DMARxDesc;
|
||||
|
||||
DMARxDescToGet = DMARxDescTab;
|
||||
for(i = 0; i < RxBuffCount; i++)
|
||||
{
|
||||
DMARxDesc = DMARxDescTab + i;
|
||||
DMARxDesc->Status = ETH_DMARxDesc_OWN;
|
||||
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]);
|
||||
|
||||
if(i < (RxBuffCount - 1))
|
||||
{
|
||||
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_Start
|
||||
*
|
||||
* @brief Enables ENET MAC and DMA reception/transmission.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_Start(void)
|
||||
{
|
||||
R16_ETH_ERXST = DMARxDescToGet->Buffer1Addr;
|
||||
R8_ETH_ECON1 |= RB_ETH_ECON1_RXEN; //receive enable
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_SetClock
|
||||
*
|
||||
* @brief Set ETH Clock(60MHz).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_SetClock(void)
|
||||
{
|
||||
/* ETH initialization */
|
||||
RCC_ETHDIVConfig(RCC_ETHCLK_Div2); // 120M/2 = 60MHz
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_Configuration
|
||||
*
|
||||
* @brief Ethernet configure.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_Configuration( uint8_t *macAddr )
|
||||
{
|
||||
ETH_SetClock( );
|
||||
R8_ETH_EIE = 0;
|
||||
R8_ETH_EIE |= RB_ETH_EIE_INTIE |
|
||||
RB_ETH_EIE_RXIE|
|
||||
RB_ETH_EIE_LINKIE|
|
||||
RB_ETH_EIE_TXIE |
|
||||
RB_ETH_EIE_TXERIE|
|
||||
RB_ETH_EIE_RXERIE; //Turn on all interrupts
|
||||
|
||||
R8_ETH_EIE |= RB_ETH_EIE_R_EN50; //Turn on 50 ohm pull-up
|
||||
|
||||
R8_ETH_EIR = 0xff; //clear interrupt flag
|
||||
R8_ETH_ESTAT |= RB_ETH_ESTAT_INT | RB_ETH_ESTAT_BUFER; //clear state
|
||||
|
||||
R8_ETH_ECON1 |= (RB_ETH_ECON1_TXRST|RB_ETH_ECON1_RXRST); //Transceiver module reset
|
||||
R8_ETH_ECON1 &= ~(RB_ETH_ECON1_TXRST|RB_ETH_ECON1_RXRST);
|
||||
|
||||
//Filter mode, received packet type
|
||||
R8_ETH_ERXFCON = 0;
|
||||
R8_ETH_MAADRL1 = macAddr[5]; // MAC assignment
|
||||
R8_ETH_MAADRL2 = macAddr[4];
|
||||
R8_ETH_MAADRL3 = macAddr[3];
|
||||
R8_ETH_MAADRL4 = macAddr[2];
|
||||
R8_ETH_MAADRL5 = macAddr[1];
|
||||
R8_ETH_MAADRL6 = macAddr[0];
|
||||
|
||||
//Filter mode, limit packet type
|
||||
R8_ETH_MACON1 |= RB_ETH_MACON1_MARXEN; //MAC receive enable
|
||||
R8_ETH_MACON2 &= ~RB_ETH_MACON2_PADCFG;
|
||||
R8_ETH_MACON2 |= PADCFG_AUTO_3; //All short packets are automatically padded to 60 bytes
|
||||
R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN; //Hardware padded CRC
|
||||
R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN; //Jumbo frames are not received
|
||||
R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
|
||||
|
||||
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn MACRAW_Tx
|
||||
*
|
||||
* @brief Ethernet sends data frames in chain mode.
|
||||
*
|
||||
* @param buff send buffer pointer
|
||||
* len Send data length
|
||||
*
|
||||
* @return Send status.
|
||||
*/
|
||||
uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||
if( DMATxDescToSet->Status & ETH_DMATxDesc_OWN )
|
||||
{
|
||||
/* Return ERROR: OWN bit set */
|
||||
return ETH_ERROR;
|
||||
}
|
||||
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||||
R16_ETH_ETXLN = len;
|
||||
R16_ETH_ETXST = (uint32_t)buff;
|
||||
R8_ETH_ECON1 |= RB_ETH_ECON1_TXRTS; //start sending
|
||||
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||||
/* Chained Mode */
|
||||
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||||
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||||
/* Return SUCCESS */
|
||||
return ETH_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_PHYLink
|
||||
*
|
||||
* @brief
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_PHYLink( void )
|
||||
{
|
||||
uint32_t phy_stat, phy_anlpar;
|
||||
|
||||
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
|
||||
phy_stat = ReadPHYReg(PHY_BMSR); //Read PHY Status Register
|
||||
|
||||
if((phy_stat&(PHY_Linked_Status))&&(phy_anlpar == 0)){ //restart negotiation
|
||||
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
|
||||
phyLinkReset = 1;
|
||||
phyLinkTime = LocalTime;
|
||||
return;
|
||||
}
|
||||
|
||||
if( (phy_stat&(PHY_Linked_Status)) && (phy_stat&PHY_AutoNego_Complete) )
|
||||
{
|
||||
printf("Link Suc\r\n");
|
||||
if( phy_anlpar&(1<<6) )
|
||||
{
|
||||
R8_ETH_MACON2 |= RB_ETH_MACON2_FULDPX;
|
||||
}
|
||||
else
|
||||
{
|
||||
R8_ETH_MACON2 &= ~RB_ETH_MACON2_FULDPX;
|
||||
}
|
||||
/* Receive CRC error packets */
|
||||
R8_ETH_ERXFCON |= RB_ETH_ERXFCON_CRCEN;
|
||||
CRCErrPktCnt = 0;
|
||||
PhyPolarityDetect = 1;
|
||||
phyLinkTime = LocalTime;
|
||||
phyStatus = PHY_Linked_Status;
|
||||
ETH_Start( );
|
||||
LinkSta = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
LinkSta = 0;
|
||||
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
|
||||
phyLinkReset = 1;
|
||||
phyLinkTime = LocalTime;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_ETHIsr
|
||||
*
|
||||
* @brief
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_ETHIsr( void )
|
||||
{
|
||||
uint8_t eth_irq_flag, estat_regval;
|
||||
|
||||
eth_irq_flag = R8_ETH_EIR;
|
||||
if(eth_irq_flag&RB_ETH_EIR_RXIF) //Receive complete
|
||||
{
|
||||
R8_ETH_EIR = RB_ETH_EIR_RXIF;
|
||||
/* Check if the descriptor is owned by the ETHERNET DMA */
|
||||
if( DMARxDescToGet->Status & ETH_DMARxDesc_OWN )
|
||||
{
|
||||
estat_regval = R8_ETH_ESTAT;
|
||||
if(estat_regval & \
|
||||
(RB_ETH_ESTAT_BUFER | RB_ETH_ESTAT_RXCRCER | RB_ETH_ESTAT_RXNIBBLE | RB_ETH_ESTAT_RXMORE))
|
||||
{
|
||||
return;
|
||||
}
|
||||
if( ((ETH_DMADESCTypeDef*)(DMARxDescToGet->Buffer2NextDescAddr))->Status& ETH_DMARxDesc_OWN )
|
||||
{
|
||||
DMARxDescToGet->Status &= ~ETH_DMARxDesc_OWN;
|
||||
DMARxDescToGet->Status &= ~ETH_DMARxDesc_ES;
|
||||
DMARxDescToGet->Status |= (ETH_DMARxDesc_FS|ETH_DMARxDesc_LS);
|
||||
DMARxDescToGet->Status &= ~ETH_DMARxDesc_FL;
|
||||
DMARxDescToGet->Status |= ((R16_ETH_ERXLN+4)<<ETH_DMARxDesc_FrameLengthShift);
|
||||
|
||||
/* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
|
||||
/* Selects the next DMA Rx descriptor list for next buffer to read */
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
||||
R16_ETH_ERXST = DMARxDescToGet->Buffer1Addr;
|
||||
}
|
||||
}
|
||||
if(PhyPolarityDetect)
|
||||
{
|
||||
PhyPolarityDetect = 0;
|
||||
/* Discard CRC error packet */
|
||||
R8_ETH_ERXFCON &= ~RB_ETH_ERXFCON_CRCEN;
|
||||
}
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_TXIF) //send completed
|
||||
{
|
||||
DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
|
||||
R8_ETH_EIR = RB_ETH_EIR_TXIF;
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_LINKIF) //Link change
|
||||
{
|
||||
ETH_PHYLink();
|
||||
R8_ETH_EIR = RB_ETH_EIR_LINKIF;
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_TXERIF) //send error
|
||||
{
|
||||
DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
|
||||
R8_ETH_EIR = RB_ETH_EIR_TXERIF;
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_RXERIF) //receive error
|
||||
{
|
||||
if(PhyPolarityDetect) CRCErrPktCnt++;
|
||||
R8_ETH_EIR = RB_ETH_EIR_RXERIF;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_Init
|
||||
*
|
||||
* @brief Ethernet initialization.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_Init( uint8_t *macAddr )
|
||||
{
|
||||
Delay_Ms(100);
|
||||
ETH_Configuration( macAddr );
|
||||
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||
pDMARxSet = DMARxDscrTab;
|
||||
pDMATxSet = DMATxDscrTab;
|
||||
NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
|
||||
/******************************** endfile @ eth_driver ******************************/
|
||||
@@ -0,0 +1,107 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : eth_driver.h
|
||||
* Author : WCH
|
||||
* Version : V1.3.0
|
||||
* Date : 2022/05/27
|
||||
* Description : This file contains the headers of the ETH Driver.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __ETH_DRIVER__
|
||||
#define __ETH_DRIVER__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
#define ROM_CFG_USERADR_ID 0x1FFFF7E8
|
||||
|
||||
#define PHY_LINK_TASK_PERIOD 50
|
||||
|
||||
#define PHY_ANLPAR_SELECTOR_FIELD 0x1F
|
||||
#define PHY_ANLPAR_SELECTOR_VALUE 0x01 /* 5B'00001 */
|
||||
|
||||
#define PHY_LINK_INIT 0x00
|
||||
#define PHY_LINK_SUC_P (1<<0)
|
||||
#define PHY_LINK_SUC_N (1<<1)
|
||||
#define PHY_LINK_WAIT_SUC (1<<7)
|
||||
|
||||
#define PHY_PN_SWITCH_P (0<<2)
|
||||
#define PHY_PN_SWITCH_N (1<<2)
|
||||
#define PHY_PN_SWITCH_AUTO (2<<2)
|
||||
|
||||
#ifndef WCHNETTIMERPERIOD
|
||||
#define WCHNETTIMERPERIOD 10 /* Timer period, in Ms. */
|
||||
#endif
|
||||
|
||||
#define PHY_NEGOTIATION_PARAM_INIT() do{\
|
||||
phySucCnt = 0;\
|
||||
phyStatus = 0;\
|
||||
phyLinkCnt = 0;\
|
||||
phyRetryCnt = 0;\
|
||||
phyPNChangeCnt = 0;\
|
||||
phyLinkStatus = PHY_LINK_INIT;\
|
||||
}while(0)
|
||||
|
||||
/* definition for Ethernet frame */
|
||||
#define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
|
||||
#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
|
||||
#define ETH_CRC 4 /* Ethernet CRC */
|
||||
#define ETH_EXTRA 2 /* Extra bytes in some cases */
|
||||
#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
|
||||
#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */
|
||||
#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */
|
||||
|
||||
/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/
|
||||
#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
|
||||
|
||||
/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */
|
||||
#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
|
||||
#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */
|
||||
#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: */
|
||||
#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */
|
||||
#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */
|
||||
|
||||
#define ETH_DMARxDesc_FrameLengthShift 16
|
||||
|
||||
/* ETHERNET errors */
|
||||
#define ETH_ERROR ((uint32_t)0)
|
||||
#define ETH_SUCCESS ((uint32_t)1)
|
||||
|
||||
/* ETH structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t volatile Status; /* Status */
|
||||
uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
|
||||
uint32_t Buffer1Addr; /* Buffer1 address pointer */
|
||||
uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
|
||||
} ETH_DMADESCTypeDef;
|
||||
|
||||
#define ETH_TXBUFNB 1
|
||||
#define ETH_RXBUFNB 4
|
||||
#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||
#define HARDWARE_CHECKSUM_CONFIG 1 /* Hardware checksum checking and insertion configuration, 1: enable, 0: disable */
|
||||
|
||||
extern ETH_DMADESCTypeDef *DMATxDescToSet;
|
||||
extern ETH_DMADESCTypeDef *DMARxDescToGet;
|
||||
extern __attribute__ ((aligned(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE];
|
||||
|
||||
void WCHNET_ETHIsr(void);
|
||||
void ETH_PHYLink( void );
|
||||
void WCHNET_MainTask(void);
|
||||
void ETH_Init( uint8_t *macAddr );
|
||||
void WCHNET_GetMacAddr( uint8_t *p );
|
||||
void WCHNET_TimeIsr( uint16_t timperiod );
|
||||
void ETH_Configuration( uint8_t *macAddr );
|
||||
uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1 @@
|
||||
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{␍/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */␍/*␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K␍*/ ␍␍/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */␍␍/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍*/ ␍ ␍/* CH32V20x_D8 - CH32V203RB␍ CH32V20x_D8W - CH32V208x␍ FLASH + RAM supports the following configuration␍ FLASH-128K + RAM-64K␍ FLASH-144K + RAM-48K␍ FLASH-160K + RAM-32K␍*/␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K␍␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.gnu.linkonce.t.*)␍ . = ALIGN(4);␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . );␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
|
||||
@@ -0,0 +1,2 @@
|
||||
�i“CZ ?"Ç�¸rŸ�F<Fy8E9Y‡½„%P a³D¶La† %Ã'y€¡]Ç;’¶ ŸS)1†1+R4><‚.„ÇÅ¿º° ?/£XO©Ä¿ChQN$*¢”»EÅBk‹!2tŒ+buh†nUb]xl‹l|
|
||||
+"Ÿ<“¯AH42}z8p;m€u 1Ž-¦eh»Od¼Âwµª7x{5�CqEx©=;¦¢e¢º»2£Š ‚«* BP Mš"
|
||||
@@ -0,0 +1,41 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_it.h"
|
||||
#include "eth_driver.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
/**/
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
printf("HardFault_Handler\r\n");
|
||||
printf("mcause:%08x\r\n",__get_MCAUSE());
|
||||
printf("mtval:%08x\r\n",__get_MTVAL());
|
||||
printf("mepc:%08x\r\n",__get_MEPC());
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_IRQHandler
|
||||
*
|
||||
* @brief This function handles ETH exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_IRQHandler(void)
|
||||
{
|
||||
WCHNET_ETHIsr();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn TIM2_IRQHandler
|
||||
*
|
||||
* @brief This function handles TIM2 exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TIM2_IRQHandler(void)
|
||||
{
|
||||
WCHNET_TimeIsr(WCHNETTIMERPERIOD);
|
||||
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,134 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/05/31
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
/*
|
||||
*@Note
|
||||
MAC RAW example, demonstrating that MAC RAW receives and sends data.
|
||||
For details on the selection of engineering chips,
|
||||
please refer to the "CH32V20x Evaluation Board Manual" under the CH32V20xEVT\EVT\PUB folder.
|
||||
*/
|
||||
#include "string.h"
|
||||
#include "eth_driver.h"
|
||||
|
||||
extern volatile uint8_t LinkSta;
|
||||
uint8_t MACAddr[6]; //MAC address
|
||||
uint8_t ARPPackage[]=
|
||||
{
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* destination MAC address */
|
||||
0x84, 0xc2, 0xe4, 0x01, 0x02, 0x03, /* source MAC address */
|
||||
0x08,0x06, /* Type:ARP */
|
||||
0x00,0x01, /* Hardware type:Ethernet(1) */
|
||||
0x08,0x00, /* Protocol type:IPv4 */
|
||||
0x06,0x04, /* Hardware size and Protocol size*/
|
||||
0x00,0x01, /* Opcode:request(1) */
|
||||
0x84, 0xc2, 0xe4, 0x01, 0x02, 0x03, /* Sender MAC address */
|
||||
0xc0,0xa8,0x1,0x0f, /* Sender IP address */
|
||||
0x00,0x00,0x00,0x00,0x00,0x00, /* Target MAC address */
|
||||
0xc0,0xa8,0x1,0x64, /* Target IP address */
|
||||
#if 1 /* padding 16 bytes * line numbers */
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,
|
||||
0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55
|
||||
#endif
|
||||
};
|
||||
|
||||
/*********************************************************************
|
||||
* @fn TIM2_Init
|
||||
*
|
||||
* @brief Initializes TIM2.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TIM2_Init(void)
|
||||
{
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = { 0 };
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
|
||||
|
||||
TIM_TimeBaseStructure.TIM_Period = SystemCoreClock / 1000000;
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = WCHNETTIMERPERIOD * 1000 - 1;
|
||||
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
|
||||
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
|
||||
|
||||
TIM_Cmd(TIM2, ENABLE);
|
||||
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
|
||||
NVIC_EnableIRQ(TIM2_IRQn);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
u8 i;
|
||||
uint32_t PktCnt = 0;
|
||||
|
||||
Delay_Init();
|
||||
USART_Printf_Init(115200); //USART initialize
|
||||
printf("MAC_RAW Test\r\n");
|
||||
if((SystemCoreClock == 60000000) || (SystemCoreClock == 120000000))
|
||||
printf("SystemClk:%d\r\n", SystemCoreClock);
|
||||
else
|
||||
printf("Error: Please choose 60MHz and 120MHz clock when using Ethernet!\r\n");
|
||||
WCHNET_GetMacAddr(MACAddr); //get the chip MAC address
|
||||
printf("mac addr:");
|
||||
for(i = 0; i < 6; i++)
|
||||
printf("%x ", MACAddr[i]);
|
||||
printf("\n");
|
||||
TIM2_Init();
|
||||
ETH_Init(MACAddr);
|
||||
/* change source MAC address */
|
||||
memcpy(&ARPPackage[6], MACAddr, 6);
|
||||
memcpy(&ARPPackage[22], MACAddr, 6);
|
||||
|
||||
while(1)
|
||||
{
|
||||
WCHNET_MainTask();
|
||||
if(LinkSta)
|
||||
{
|
||||
MACRAW_Tx(ARPPackage, sizeof(ARPPackage));
|
||||
if(++PktCnt % 100 == 0)
|
||||
printf("PktCnt:%d\r\n",PktCnt);
|
||||
Delay_Ms(100);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,990 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user