update 1.8
This commit is contained in:
qiyongshuang
@@ -0,0 +1,633 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : eth_driver.c
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* Author : WCH
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* Version : V1.3.0
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* Date : 2022/05/26
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* Description : eth program body.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "string.h"
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#include "eth_driver.h"
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__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
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__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
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__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
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__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
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ETH_DMADESCTypeDef *pDMARxSet;
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ETH_DMADESCTypeDef *pDMATxSet;
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ETH_DMADESCTypeDef *DMATxDescToSet;
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ETH_DMADESCTypeDef *DMARxDescToGet;
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volatile uint8_t LinkSta = 0; //0: No valid link established 1:Valid link establishe
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volatile uint8_t phyLinkReset;
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volatile uint32_t phyLinkTime;
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volatile uint32_t LocalTime;
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uint8_t phyPN = 0x01;
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uint8_t phyStatus = 0;
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uint8_t phySucCnt = 0;
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uint8_t phyLinkCnt = 0;
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uint8_t phyRetryCnt = 0;
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uint8_t CRCErrPktCnt = 0;
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uint8_t phyLinkStatus = 0;
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uint8_t phyPNChangeCnt = 0;
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uint8_t PhyPolarityDetect = 0;
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/*********************************************************************
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* @fn WCHNET_GetMacAddr
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*
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* @brief Get MAC address
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*
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* @return none.
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*/
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void WCHNET_GetMacAddr( uint8_t *p )
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{
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uint8_t i;
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uint8_t *macaddr=(uint8_t *)(ROM_CFG_USERADR_ID+5);
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for(i=0;i<6;i++)
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{
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*p = *macaddr;
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p++;
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macaddr--;
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}
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}
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/*********************************************************************
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* @fn WCHNET_TimeIsr
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*
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* @brief
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*
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* @return none.
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*/
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void WCHNET_TimeIsr( uint16_t timperiod )
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{
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LocalTime += timperiod;
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}
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/*********************************************************************
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* @fn WritePHYReg
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*
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* @brief MCU write PHY register.
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*
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* @param reg_add - PHY address,
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* reg_val - value you want to write.
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*
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* @return none
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*/
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void WritePHYReg(uint8_t reg_add,uint16_t reg_val)
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{
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R32_ETH_MIWR = (reg_add & RB_ETH_MIREGADR_MIRDL) | (1<<8) | (reg_val<<16);
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}
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/*********************************************************************
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* @fn ReadPHYReg
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*
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* @brief MCU read PHY register.
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*
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* @param reg_add - PHY address.
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*
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* @return value you want to get.
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*/
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uint16_t ReadPHYReg(uint8_t reg_add)
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{
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R8_ETH_MIREGADR = reg_add; // write address
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return R16_ETH_MIRD; // get data
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}
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/*********************************************************************
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* @fn WCHNET_LinkProcess
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*
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* @brief link process.
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*
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* @param none.
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*
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* @return none.
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*/
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void WCHNET_LinkProcess( void )
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{
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uint16_t phy_anlpar, phy_bmcr, phy_bmsr;
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phy_anlpar = ReadPHYReg(PHY_ANLPAR);
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phy_bmsr = ReadPHYReg(PHY_BMSR);
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if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) )
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{
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if( !(phyLinkStatus&PHY_LINK_WAIT_SUC) )
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{
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if( (phyPN&0x0C) == PHY_PN_SWITCH_P )
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{
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phySucCnt = 0;
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phyLinkCnt = 0;
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phyLinkStatus = PHY_LINK_WAIT_SUC;
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}
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else
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{
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if( !(phyLinkStatus&PHY_LINK_SUC_N) )
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{
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phyRetryCnt = 0;
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phyLinkStatus |= PHY_LINK_SUC_N;
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phyPN &= ~PHY_PN_SWITCH_N;
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phy_bmcr = ReadPHYReg(PHY_BMCR);
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phy_bmcr |= 1<<9;
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WritePHYReg(PHY_BMCR, phy_bmcr);
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WritePHYReg(PHY_MDIX, phyPN);
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}
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else
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{
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phySucCnt = 0;
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phyLinkCnt = 0;
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phyLinkStatus = PHY_LINK_WAIT_SUC;
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}
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}
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}
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else{
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if((phySucCnt++ == 5) && ((phy_bmsr&(1<<5)) == 0))
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{
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phySucCnt = 0;
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phyRetryCnt = 0;
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phyPNChangeCnt = 0;
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phyLinkStatus = PHY_LINK_INIT;
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phy_bmcr = ReadPHYReg(PHY_BMCR);
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phy_bmcr |= 1<<9;
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WritePHYReg(PHY_BMCR, phy_bmcr);
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if((phyPN&0x0C) == PHY_PN_SWITCH_P)
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{
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phyPN |= PHY_PN_SWITCH_N;
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}
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else {
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phyPN &= ~PHY_PN_SWITCH_N;
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}
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WritePHYReg(PHY_MDIX, phyPN);
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}
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}
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}
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else
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{
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if( phyLinkStatus == PHY_LINK_WAIT_SUC )
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{
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if(phyLinkCnt++ == 10)
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{
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phyLinkCnt = 0;
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phyRetryCnt = 0;
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phyPNChangeCnt = 0;
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phyLinkStatus = PHY_LINK_INIT;
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}
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}
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else if(phyLinkStatus == PHY_LINK_INIT)
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{
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if(phyPNChangeCnt++ == 10)
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{
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phyPNChangeCnt = 0;
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phyPN = ReadPHYReg(PHY_MDIX);
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phyPN &= ~0x0c;
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phyPN ^= 0x03;
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WritePHYReg(PHY_MDIX, phyPN);
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}
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else{
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if((phyPN&0x0C) == PHY_PN_SWITCH_P)
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{
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phyPN |= PHY_PN_SWITCH_N;
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}
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else {
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phyPN &= ~PHY_PN_SWITCH_N;
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}
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WritePHYReg(PHY_MDIX, phyPN);
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}
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}
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else if(phyLinkStatus == PHY_LINK_SUC_N)
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{
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if((phyPN&0x0C) == PHY_PN_SWITCH_P)
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{
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phyPN |= PHY_PN_SWITCH_N;
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phy_bmcr = ReadPHYReg(PHY_BMCR);
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phy_bmcr |= 1<<9;
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WritePHYReg(PHY_BMCR, phy_bmcr);
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Delay_Us(10);
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WritePHYReg(PHY_MDIX, phyPN);
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}
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else{
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if(phyRetryCnt++ == 15)
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{
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phyRetryCnt = 0;
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phyPNChangeCnt = 0;
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phyLinkStatus = PHY_LINK_INIT;
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}
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}
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}
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}
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}
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/*********************************************************************
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* @fn WCHNET_PhyPNProcess
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*
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* @brief Phy PN Polarity related processing
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*
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* @param none.
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*
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* @return none.
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*/
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void WCHNET_PhyPNProcess(void)
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{
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uint32_t PhyVal;
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phyLinkTime = LocalTime;
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if(CRCErrPktCnt >= 3)
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{
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PhyVal = ReadPHYReg(PHY_MDIX);
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if((PhyVal >> 2) & 0x01)
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PhyVal &= ~(3 << 2); //change PHY PN Polarity to normal
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else
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PhyVal |= 1 << 2; //change PHY PN Polarity to reverse
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WritePHYReg(PHY_MDIX, PhyVal);
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CRCErrPktCnt = 0;
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}
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}
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/*********************************************************************
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* @fn WCHNET_HandlePhyNegotiation
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*
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* @brief Handle PHY Negotiation.
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*
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* @param none.
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*
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* @return none.
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*/
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void WCHNET_HandlePhyNegotiation(void)
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{
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if(phyLinkReset) /* After the PHY link is disconnected, wait 500ms before turning on the PHY clock*/
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{
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if( LocalTime - phyLinkTime >= 500 )
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{
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phyLinkReset = 0;
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EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
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WritePHYReg(PHY_BMCR, PHY_Reset);
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PHY_NEGOTIATION_PARAM_INIT();
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}
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}
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else
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{
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if( !phyStatus ) /* Handling PHY Negotiation Exceptions */
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{
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if( LocalTime - phyLinkTime >= PHY_LINK_TASK_PERIOD ) /* 50ms cycle timing call */
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{
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phyLinkTime = LocalTime;
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WCHNET_LinkProcess( );
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}
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}
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else{
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if(PhyPolarityDetect)
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{
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if( LocalTime - phyLinkTime >= 2 * PHY_LINK_TASK_PERIOD )
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{
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WCHNET_PhyPNProcess();
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}
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}
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}
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}
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}
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/*********************************************************************
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* @fn RecDataPolling
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*
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* @brief process received data.
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*
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* @param none.
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*
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* @return none.
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*/
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void RecDataPolling(void)
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{
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uint32_t length, buffer;
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while(!(pDMARxSet->Status & ETH_DMARxDesc_OWN))
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{
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if( !(pDMARxSet->Status & ETH_DMARxDesc_ES) &&\
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(pDMARxSet->Status & ETH_DMARxDesc_LS) &&\
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(pDMARxSet->Status & ETH_DMARxDesc_FS) )
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{
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/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
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length = ((pDMARxSet->Status & ETH_DMARxDesc_FL) >> 16) - 4;
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/* Get the addrees of the actual buffer */
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buffer = pDMARxSet->Buffer1Addr;
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/* Do something*/
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printf("rec data:%d bytes\r\n",length);
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printf("data:%x\r\n",*((uint8_t *)buffer));
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}
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pDMARxSet->Status = ETH_DMARxDesc_OWN;
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pDMARxSet = (ETH_DMADESCTypeDef *)pDMARxSet->Buffer2NextDescAddr;
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}
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}
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/*********************************************************************
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* @fn WCHNET_MainTask
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*
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* @brief library main task function
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*
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* @return none.
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*/
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void WCHNET_MainTask(void)
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{
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WCHNET_HandlePhyNegotiation( );
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RecDataPolling();
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}
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/*********************************************************************
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* @fn ETH_DMATxDescChainInit
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*
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* @brief Initializes the DMA Tx descriptors in chain mode.
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*
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* @param DMATxDescTab - Pointer on the first Tx desc list
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* TxBuff - Pointer on the first TxBuffer list
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* TxBuffCount - Number of the used Tx desc in the list
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*
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* @return none
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*/
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void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
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{
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ETH_DMADESCTypeDef *DMATxDesc;
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DMATxDescToSet = DMATxDescTab;
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DMATxDesc = DMATxDescTab;
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DMATxDesc->Status = 0;
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DMATxDesc->Buffer1Addr = (uint32_t)TxBuff;
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DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab;
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}
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/*********************************************************************
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* @fn ETH_DMARxDescChainInit
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*
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* @brief Initializes the DMA Rx descriptors in chain mode.
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*
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* @param DMARxDescTab - Pointer on the first Rx desc list.
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* RxBuff - Pointer on the first RxBuffer list.
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* RxBuffCount - Number of the used Rx desc in the list.
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*
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* @return none
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*/
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void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
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{
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uint8_t i = 0;
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ETH_DMADESCTypeDef *DMARxDesc;
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DMARxDescToGet = DMARxDescTab;
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for(i = 0; i < RxBuffCount; i++)
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{
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DMARxDesc = DMARxDescTab + i;
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DMARxDesc->Status = ETH_DMARxDesc_OWN;
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DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]);
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if(i < (RxBuffCount - 1))
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{
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DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1);
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}
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else
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{
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DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
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}
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}
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}
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|
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/*********************************************************************
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* @fn ETH_Start
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*
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* @brief Enables ENET MAC and DMA reception/transmission.
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*
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* @return none
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*/
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void ETH_Start(void)
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{
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R16_ETH_ERXST = DMARxDescToGet->Buffer1Addr;
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R8_ETH_ECON1 |= RB_ETH_ECON1_RXEN; //receive enable
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}
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||||
|
||||
/*********************************************************************
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||||
* @fn ETH_SetClock
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*
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||||
* @brief Set ETH Clock(60MHz).
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*
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* @return none
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||||
*/
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void ETH_SetClock(void)
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{
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/* ETH initialization */
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RCC_ETHDIVConfig(RCC_ETHCLK_Div2); // 120M/2 = 60MHz
|
||||
}
|
||||
|
||||
/*********************************************************************
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||||
* @fn ETH_Configuration
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||||
*
|
||||
* @brief Ethernet configure.
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||||
*
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||||
* @return none
|
||||
*/
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||||
void ETH_Configuration( uint8_t *macAddr )
|
||||
{
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||||
ETH_SetClock( );
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||||
R8_ETH_EIE = 0;
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||||
R8_ETH_EIE |= RB_ETH_EIE_INTIE |
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RB_ETH_EIE_RXIE|
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RB_ETH_EIE_LINKIE|
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RB_ETH_EIE_TXIE |
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||||
RB_ETH_EIE_TXERIE|
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RB_ETH_EIE_RXERIE; //Turn on all interrupts
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||||
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R8_ETH_EIE |= RB_ETH_EIE_R_EN50; //Turn on 50 ohm pull-up
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||||
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R8_ETH_EIR = 0xff; //clear interrupt flag
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||||
R8_ETH_ESTAT |= RB_ETH_ESTAT_INT | RB_ETH_ESTAT_BUFER; //clear state
|
||||
|
||||
R8_ETH_ECON1 |= (RB_ETH_ECON1_TXRST|RB_ETH_ECON1_RXRST); //Transceiver module reset
|
||||
R8_ETH_ECON1 &= ~(RB_ETH_ECON1_TXRST|RB_ETH_ECON1_RXRST);
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||||
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||||
//Filter mode, received packet type
|
||||
R8_ETH_ERXFCON = 0;
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||||
R8_ETH_MAADRL1 = macAddr[5]; // MAC assignment
|
||||
R8_ETH_MAADRL2 = macAddr[4];
|
||||
R8_ETH_MAADRL3 = macAddr[3];
|
||||
R8_ETH_MAADRL4 = macAddr[2];
|
||||
R8_ETH_MAADRL5 = macAddr[1];
|
||||
R8_ETH_MAADRL6 = macAddr[0];
|
||||
|
||||
//Filter mode, limit packet type
|
||||
R8_ETH_MACON1 |= RB_ETH_MACON1_MARXEN; //MAC receive enable
|
||||
R8_ETH_MACON2 &= ~RB_ETH_MACON2_PADCFG;
|
||||
R8_ETH_MACON2 |= PADCFG_AUTO_3; //All short packets are automatically padded to 60 bytes
|
||||
R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN; //Hardware padded CRC
|
||||
R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN; //Jumbo frames are not received
|
||||
R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
|
||||
|
||||
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn MACRAW_Tx
|
||||
*
|
||||
* @brief Ethernet sends data frames in chain mode.
|
||||
*
|
||||
* @param buff send buffer pointer
|
||||
* len Send data length
|
||||
*
|
||||
* @return Send status.
|
||||
*/
|
||||
uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||
if( DMATxDescToSet->Status & ETH_DMATxDesc_OWN )
|
||||
{
|
||||
/* Return ERROR: OWN bit set */
|
||||
return ETH_ERROR;
|
||||
}
|
||||
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||||
R16_ETH_ETXLN = len;
|
||||
R16_ETH_ETXST = (uint32_t)buff;
|
||||
R8_ETH_ECON1 |= RB_ETH_ECON1_TXRTS; //start sending
|
||||
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||||
/* Chained Mode */
|
||||
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||||
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||||
/* Return SUCCESS */
|
||||
return ETH_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_PHYLink
|
||||
*
|
||||
* @brief
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_PHYLink( void )
|
||||
{
|
||||
uint32_t phy_stat, phy_anlpar;
|
||||
|
||||
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
|
||||
phy_stat = ReadPHYReg(PHY_BMSR); //Read PHY Status Register
|
||||
|
||||
if((phy_stat&(PHY_Linked_Status))&&(phy_anlpar == 0)){ //restart negotiation
|
||||
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
|
||||
phyLinkReset = 1;
|
||||
phyLinkTime = LocalTime;
|
||||
return;
|
||||
}
|
||||
|
||||
if( (phy_stat&(PHY_Linked_Status)) && (phy_stat&PHY_AutoNego_Complete) )
|
||||
{
|
||||
printf("Link Suc\r\n");
|
||||
if( phy_anlpar&(1<<6) )
|
||||
{
|
||||
R8_ETH_MACON2 |= RB_ETH_MACON2_FULDPX;
|
||||
}
|
||||
else
|
||||
{
|
||||
R8_ETH_MACON2 &= ~RB_ETH_MACON2_FULDPX;
|
||||
}
|
||||
/* Receive CRC error packets */
|
||||
R8_ETH_ERXFCON |= RB_ETH_ERXFCON_CRCEN;
|
||||
CRCErrPktCnt = 0;
|
||||
PhyPolarityDetect = 1;
|
||||
phyLinkTime = LocalTime;
|
||||
phyStatus = PHY_Linked_Status;
|
||||
ETH_Start( );
|
||||
LinkSta = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
LinkSta = 0;
|
||||
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
|
||||
phyLinkReset = 1;
|
||||
phyLinkTime = LocalTime;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_ETHIsr
|
||||
*
|
||||
* @brief
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_ETHIsr( void )
|
||||
{
|
||||
uint8_t eth_irq_flag, estat_regval;
|
||||
|
||||
eth_irq_flag = R8_ETH_EIR;
|
||||
if(eth_irq_flag&RB_ETH_EIR_RXIF) //Receive complete
|
||||
{
|
||||
R8_ETH_EIR = RB_ETH_EIR_RXIF;
|
||||
/* Check if the descriptor is owned by the ETHERNET DMA */
|
||||
if( DMARxDescToGet->Status & ETH_DMARxDesc_OWN )
|
||||
{
|
||||
estat_regval = R8_ETH_ESTAT;
|
||||
if(estat_regval & \
|
||||
(RB_ETH_ESTAT_BUFER | RB_ETH_ESTAT_RXCRCER | RB_ETH_ESTAT_RXNIBBLE | RB_ETH_ESTAT_RXMORE))
|
||||
{
|
||||
return;
|
||||
}
|
||||
if( ((ETH_DMADESCTypeDef*)(DMARxDescToGet->Buffer2NextDescAddr))->Status& ETH_DMARxDesc_OWN )
|
||||
{
|
||||
DMARxDescToGet->Status &= ~ETH_DMARxDesc_OWN;
|
||||
DMARxDescToGet->Status &= ~ETH_DMARxDesc_ES;
|
||||
DMARxDescToGet->Status |= (ETH_DMARxDesc_FS|ETH_DMARxDesc_LS);
|
||||
DMARxDescToGet->Status &= ~ETH_DMARxDesc_FL;
|
||||
DMARxDescToGet->Status |= ((R16_ETH_ERXLN+4)<<ETH_DMARxDesc_FrameLengthShift);
|
||||
|
||||
/* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
|
||||
/* Selects the next DMA Rx descriptor list for next buffer to read */
|
||||
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
||||
R16_ETH_ERXST = DMARxDescToGet->Buffer1Addr;
|
||||
}
|
||||
}
|
||||
if(PhyPolarityDetect)
|
||||
{
|
||||
PhyPolarityDetect = 0;
|
||||
/* Discard CRC error packet */
|
||||
R8_ETH_ERXFCON &= ~RB_ETH_ERXFCON_CRCEN;
|
||||
}
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_TXIF) //send completed
|
||||
{
|
||||
DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
|
||||
R8_ETH_EIR = RB_ETH_EIR_TXIF;
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_LINKIF) //Link change
|
||||
{
|
||||
ETH_PHYLink();
|
||||
R8_ETH_EIR = RB_ETH_EIR_LINKIF;
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_TXERIF) //send error
|
||||
{
|
||||
DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
|
||||
R8_ETH_EIR = RB_ETH_EIR_TXERIF;
|
||||
}
|
||||
if(eth_irq_flag&RB_ETH_EIR_RXERIF) //receive error
|
||||
{
|
||||
if(PhyPolarityDetect) CRCErrPktCnt++;
|
||||
R8_ETH_EIR = RB_ETH_EIR_RXERIF;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_Init
|
||||
*
|
||||
* @brief Ethernet initialization.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_Init( uint8_t *macAddr )
|
||||
{
|
||||
Delay_Ms(100);
|
||||
ETH_Configuration( macAddr );
|
||||
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||
pDMARxSet = DMARxDscrTab;
|
||||
pDMATxSet = DMATxDscrTab;
|
||||
NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
|
||||
/******************************** endfile @ eth_driver ******************************/
|
||||
Reference in New Issue
Block a user