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update 1.8

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qiyongshuang
2023-09-06 10:08:11 +08:00
parent b79c6ac80d
commit 64be955461
760 changed files with 42517 additions and 30957 deletions
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EVT/EXAM/RT-Thread/rt-thread/.cproject
+168 -168
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@@ -1,171 +1,171 @@
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EVT/EXAM/RT-Thread/rt-thread/.project
+52 -44
View File
@@ -1,46 +1,54 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>rt-thread</name>
<comment/>
<projects/>
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<link>
<name>Debug</name>
<type>2</type>
<location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
</link>
<link>
<name>Peripheral</name>
<type>2</type>
<location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
</link>
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<name>rt-thread</name>
<comment></comment>
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EVT/EXAM/RT-Thread/rt-thread/.settings/language.settings.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
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EVT/EXAM/RT-Thread/rt-thread/.settings/org.eclipse.core.resources.prefs
-2
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eclipse.preferences.version=1
encoding//drivers/drv_gpio.c=UTF-8
EVT/EXAM/RT-Thread/rt-thread/Core/core_riscv.c
-399
View File
@@ -1,399 +0,0 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : RISC-V Core Peripheral Access Layer Source File
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/**
* @brief Return the Floating-Point Accrued Exceptions
*/
uint32_t __get_FFLAGS(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
return (result);
}
/**
* @brief Set the Floating-Point Accrued Exceptions
*/
void __set_FFLAGS(uint32_t value)
{
__ASM volatile ("csrw fflags, %0" : : "r" (value) );
}
/**
* @brief Return the Floating-Point Dynamic Rounding Mode
*/
uint32_t __get_FRM(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "frm" : "=r" (result) );
return (result);
}
/**
* @brief Set the Floating-Point Dynamic Rounding Mode
*/
void __set_FRM(uint32_t value)
{
__ASM volatile ("csrw frm, %0" : : "r" (value) );
}
/**
* @brief Return the Floating-Point Control and Status Register
*/
uint32_t __get_FCSR(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
return (result);
}
/**
* @brief Set the Floating-Point Control and Status Register
*/
void __set_FCSR(uint32_t value)
{
__ASM volatile ("csrw fcsr, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Status Register
*/
uint32_t __get_MSTATUS(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Status Register
*/
void __set_MSTATUS(uint32_t value)
{
__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
}
/**
* @brief Return the Machine ISA Register
*/
uint32_t __get_MISA(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine ISA Register
*/
void __set_MISA(uint32_t value)
{
__ASM volatile ("csrw misa, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Interrupt Enable Register
*/
uint32_t __get_MIE(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mie" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine ISA Register
*/
void __set_MIE(uint32_t value)
{
__ASM volatile ("csrw mie, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Trap-Vector Base-Address Register
*/
uint32_t __get_MTVEC(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Trap-Vector Base-Address Register
*/
void __set_MTVEC(uint32_t value)
{
__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Seratch Register
*/
uint32_t __get_MSCRATCH(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Seratch Register
*/
void __set_MSCRATCH(uint32_t value)
{
__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Exception Program Register
*/
uint32_t __get_MEPC(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Exception Program Register
*/
void __set_MEPC(uint32_t value)
{
__ASM volatile ("csrw mepc, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Cause Register
*/
uint32_t __get_MCAUSE(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Cause Register
*/
void __set_MCAUSE(uint32_t value)
{
__ASM volatile ("csrw mcause, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Trap Value Register
*/
uint32_t __get_MTVAL(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Trap Value Register
*/
void __set_MTVAL(uint32_t value)
{
__ASM volatile ("csrw mtval, %0" : : "r" (value) );
}
/**
* @brief Return the Machine Interrupt Pending Register
*/
uint32_t __get_MIP(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mip" : "=r" (result) );
return (result);
}
/**
* @brief Set the Machine Interrupt Pending Register
*/
void __set_MIP(uint32_t value)
{
__ASM volatile ("csrw mip, %0" : : "r" (value) );
}
/**
* @brief Return Lower 32 bits of Cycle counter
*/
uint32_t __get_MCYCLE(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
return (result);
}
/**
* @brief Set Lower 32 bits of Cycle counter
*/
void __set_MCYCLE(uint32_t value)
{
__ASM volatile ("csrw mcycle, %0" : : "r" (value) );
}
/**
* @brief Return Upper 32 bits of Cycle counter
*/
uint32_t __get_MCYCLEH(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
return (result);
}
/**
* @brief Set Upper 32 bits of Cycle counter
*/
void __set_MCYCLEH(uint32_t value)
{
__ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
}
/**
* @brief Return Lower 32 bits of Instructions-retired counter
*/
uint32_t __get_MINSTRET(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
return (result);
}
/**
* @brief Set Lower 32 bits of Instructions-retired counter
*/
void __set_MINSTRET(uint32_t value)
{
__ASM volatile ("csrw minstret, %0" : : "r" (value) );
}
/**
* @brief Return Upper 32 bits of Instructions-retired counter
*/
uint32_t __get_MINSTRETH(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
return (result);
}
/**
* @brief Set Upper 32 bits of Instructions-retired counter
*/
void __set_MINSTRETH(uint32_t value)
{
__ASM volatile ("csrw minstreth, %0" : : "r" (value) );
}
/**
* @brief Return Vendor ID Register
*/
uint32_t __get_MVENDORID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
return (result);
}
/**
* @brief Return Machine Architecture ID Register
*/
uint32_t __get_MARCHID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
return (result);
}
/**
* @brief Return Machine Implementation ID Register
*/
uint32_t __get_MIMPID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
return (result);
}
/**
* @brief Return Hart ID Register
*/
uint32_t __get_MHARTID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
return (result);
}
/**
* @brief Return SP Register
*/
uint32_t __get_SP(void)
{
uint32_t result;
asm volatile (
"mv %0," "sp"
: "=r"(result)
:
);
return (result);
}
EVT/EXAM/RT-Thread/rt-thread/Core/core_riscv.h
-329
View File
@@ -1,329 +0,0 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : RISC-V Core Peripheral Access Layer Header File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CORE_RISCV_H__
#define __CORE_RISCV_H__
/* IO definitions */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef __I uint64_t vuc64; /* Read Only */
typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I uint8_t vuc8; /* Read Only */
typedef const uint64_t uc64; /* Read Only */
typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */
typedef const uint8_t uc8; /* Read Only */
typedef __I int64_t vsc64; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */
typedef const int64_t sc64; /* Read Only */
typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */
typedef __IO uint64_t vu64;
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef __IO int64_t vs64;
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef int64_t s64;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#define RV_STATIC_INLINE static inline
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
typedef struct{
__I uint32_t ISR[8];
__I uint32_t IPR[8];
__IO uint32_t ITHRESDR;
__IO uint32_t RESERVED;
__IO uint32_t CFGR;
__I uint32_t GISR;
uint8_t VTFIDR[4];
uint8_t RESERVED0[12];
__IO uint32_t VTFADDR[4];
uint8_t RESERVED1[0x90];
__O uint32_t IENR[8];
uint8_t RESERVED2[0x60];
__O uint32_t IRER[8];
uint8_t RESERVED3[0x60];
__O uint32_t IPSR[8];
uint8_t RESERVED4[0x60];
__O uint32_t IPRR[8];
uint8_t RESERVED5[0x60];
__IO uint32_t IACTR[8];
uint8_t RESERVED6[0xE0];
__IO uint8_t IPRIOR[256];
uint8_t RESERVED7[0x810];
__IO uint32_t SCTLR;
}PFIC_Type;
/* memory mapped structure for SysTick */
typedef struct
{
__IO u32 CTLR;
__IO u32 SR;
__IO u64 CNT;
__IO u64 CMP;
}SysTick_Type;
#define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000)
/* risc-v specific functions */
RV_STATIC_INLINE void __enable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); }
RV_STATIC_INLINE void __disable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); }
RV_STATIC_INLINE void __NOP() { __asm volatile ("nop"); }
/* ########################## NVIC functions #################################### */
/*******************************************************************************
* Function Name : NVIC_EnableIRQ
* Description : Enable Interrupt
* Input : IRQn: Interrupt Numbers
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*******************************************************************************
* Function Name : NVIC_DisableIRQ
* Description : Disable Interrupt
* Input : IRQn: Interrupt Numbers
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*******************************************************************************
* Function Name : NVIC_GetStatusIRQ
* Description : Get Interrupt Enable State
* Input : IRQn: Interrupt Numbers
* Return : 1: Interrupt Enable
* 0: Interrupt Disable
*******************************************************************************/
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*******************************************************************************
* Function Name : NVIC_GetPendingIRQ
* Description : Get Interrupt Pending State
* Input : IRQn: Interrupt Numbers
* Return : 1: Interrupt Pending Enable
* 0: Interrupt Pending Disable
*******************************************************************************/
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*******************************************************************************
* Function Name : NVIC_SetPendingIRQ
* Description : Set Interrupt Pending
* Input : IRQn: Interrupt Numbers
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*******************************************************************************
* Function Name : NVIC_ClearPendingIRQ
* Description : Clear Interrupt Pending
* Input : IRQn: Interrupt Numbers
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*******************************************************************************
* Function Name : NVIC_GetActive
* Description : Get Interrupt Active State
* Input : IRQn: Interrupt Numbers
* Return : 1: Interrupt Active
* 0: Interrupt No Active
*******************************************************************************/
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*******************************************************************************
* Function Name : NVIC_SetPriority
* Description : Set Interrupt Priority
* Input : IRQn: Interrupt Numbers
* priority: bit7:pre-emption priority
* bit6-bit4: subpriority
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
{
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
}
/*******************************************************************************
* Function Name : __WFI
* Description : Wait for Interrupt
* Input : None
* Return : None
*******************************************************************************/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
{
NVIC->SCTLR &= ~(1<<3); // wfi
asm volatile ("wfi");
}
/*******************************************************************************
* Function Name : __WFE
* Description : Wait for Events
* Input : None
* Return : None
*******************************************************************************/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
{
uint32_t t;
t = NVIC->SCTLR;
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
asm volatile ("wfi");
asm volatile ("wfi");
}
/*******************************************************************************
* Function Name : SetVTFIRQ
* Description : Set VTF Interrupt
* Input : addr��VTF interrupt service function base address.
* IRQn��Interrupt Numbers
* num��VTF Interrupt Numbers
* NewState: DISABLE or ENABLE
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
if(num > 3) return ;
if (NewState != DISABLE)
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)|0x1);
}
else{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)&(~0x1));
}
}
/*******************************************************************************
* Function Name : NVIC_SystemReset
* Description : Initiate a system reset request
* Input : None
* Return : None
*******************************************************************************/
RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
/* Core_Exported_Functions */
extern uint32_t __get_FFLAGS(void);
extern void __set_FFLAGS(uint32_t value);
extern uint32_t __get_FRM(void);
extern void __set_FRM(uint32_t value);
extern uint32_t __get_FCSR(void);
extern void __set_FCSR(uint32_t value);
extern uint32_t __get_MSTATUS(void);
extern void __set_MSTATUS(uint32_t value);
extern uint32_t __get_MISA(void);
extern void __set_MISA(uint32_t value);
extern uint32_t __get_MIE(void);
extern void __set_MIE(uint32_t value);
extern uint32_t __get_MTVEC(void);
extern void __set_MTVEC(uint32_t value);
extern uint32_t __get_MSCRATCH(void);
extern void __set_MSCRATCH(uint32_t value);
extern uint32_t __get_MEPC(void);
extern void __set_MEPC(uint32_t value);
extern uint32_t __get_MCAUSE(void);
extern void __set_MCAUSE(uint32_t value);
extern uint32_t __get_MTVAL(void);
extern void __set_MTVAL(uint32_t value);
extern uint32_t __get_MIP(void);
extern void __set_MIP(uint32_t value);
extern uint32_t __get_MCYCLE(void);
extern void __set_MCYCLE(uint32_t value);
extern uint32_t __get_MCYCLEH(void);
extern void __set_MCYCLEH(uint32_t value);
extern uint32_t __get_MINSTRET(void);
extern void __set_MINSTRET(uint32_t value);
extern uint32_t __get_MINSTRETH(void);
extern void __set_MINSTRETH(uint32_t value);
extern uint32_t __get_MVENDORID(void);
extern uint32_t __get_MARCHID(void);
extern uint32_t __get_MIMPID(void);
extern uint32_t __get_MHARTID(void);
extern uint32_t __get_SP(void);
#endif
EVT/EXAM/RT-Thread/rt-thread/Ld/Link.ld
+1 -1
View File
@@ -1 +1 @@
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.glue_7)␍ *(.glue_7t)␍ *(.gnu.linkonce.t.*)␍ ␍ /* section information for finsh shell */␍ . = ALIGN(4);␍ __fsymtab_start = .;␍ KEEP(*(FSymTab))␍ __fsymtab_end = .;␍ . = ALIGN(4);␍ __vsymtab_start = .;␍ KEEP(*(VSymTab))␍ __vsymtab_end = .;␍ . = ALIGN(4);␍ ␍ /* section information for initial. */␍ . = ALIGN(4);␍ __rt_init_start = .;␍ KEEP(*(SORT(.rti_fn*)))␍ __rt_init_end = .;␍ . = ALIGN(4);␍␍ /* section information for modules */␍ . = ALIGN(4);␍ __rtmsymtab_start = .;␍ KEEP(*(RTMSymTab))␍ __rtmsymtab_end = .;␍ . = ALIGN(4);␍ ␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . ); ␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.gnu.linkonce.t.*)␍ ␍ /* section information for finsh shell */␍ . = ALIGN(4);␍ __fsymtab_start = .;␍ KEEP(*(FSymTab))␍ __fsymtab_end = .;␍ . = ALIGN(4);␍ __vsymtab_start = .;␍ KEEP(*(VSymTab))␍ __vsymtab_end = .;␍ . = ALIGN(4);␍ ␍ /* section information for initial. */␍ . = ALIGN(4);␍ __rt_init_start = .;␍ KEEP(*(SORT(.rti_fn*)))␍ __rt_init_end = .;␍ . = ALIGN(4);␍␍ /* section information for modules */␍ . = ALIGN(4);␍ __rtmsymtab_start = .;␍ KEEP(*(RTMSymTab))␍ __rtmsymtab_end = .;␍ . = ALIGN(4);␍ ␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . ); ␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S
+1 -1
View File
@@ -3,7 +3,7 @@
;* Author : WCH
;* Version : V1.0.0
;* Date : 2021/06/06
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
;* vector table for eclipse toolchain.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/RT-Thread/rt-thread/User/main.c
+13 -11
View File
@@ -4,11 +4,11 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x.h"
#include <rtthread.h>
#include <rthw.h>
@@ -19,7 +19,7 @@
/* Global define */
/* LED0 is driven by the pin driver interface of rt */
#define LED0_PIN 11 //PA0
#define LED0_PIN 11 //PA1
/* Global Variable */
@@ -42,15 +42,17 @@ void LED1_BLINK_INIT(void)
/* main is just one of the threads, in addition to tshell,idle
* main is just an LED blinking, the main thread is registered in rtthread_startup,
* tshell uses the serial port to receive interrupts, and the interrupt stack and thread stack are
* used separately.Note that when entering an interrupt, the 16caller register needs to be pushed
* into the thread stack
* */
* main is just an LED blinking, the main thread is registered in rtthread_startup,
* tshell uses the serial port to receive interrupts, and the interrupt stack and thread stack are
* used separately.Note that when entering an interrupt, the 16caller register needs to be pushed
* into the thread stack
*/
int main(void)
{
SystemCoreClockUpdate();
rt_kprintf("\r\n MCU: CH32V20x\r\n");
rt_kprintf(" SysClk: %dHz\r\n",SystemCoreClock);
rt_kprintf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() );
rt_kprintf(" www.wch.cn\r\n");
LED1_BLINK_INIT();
GPIO_ResetBits(GPIOA,GPIO_Pin_0);