bstanwell/ch32v20x-examples
2
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

update 1.8

Browse Source
This commit is contained in:
qiyongshuang
2023-09-06 10:08:11 +08:00
parent b79c6ac80d
commit 64be955461
760 changed files with 42517 additions and 30957 deletions
Download Patch File Download Diff File Expand all files Collapse all files
EVT/EXAM/SRC/Core/core_riscv.c
+8 -9
View File
@@ -13,20 +13,20 @@
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __ASM __asm /* asm keyword for ARM Compiler */
#define __INLINE __inline /* inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#define __ASM __asm /* asm keyword for IAR Compiler */
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __ASM __asm /* asm keyword for GNU Compiler */
#define __INLINE inline /* inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __ASM __asm /* asm keyword for TASKING Compiler */
#define __INLINE inline /* inline keyword for TASKING Compiler */
#endif
@@ -90,7 +90,6 @@ void __set_MISA(uint32_t value)
__ASM volatile ("csrw misa, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MTVEC
*
EVT/EXAM/SRC/Core/core_riscv.h
+267 -65
View File
@@ -18,43 +18,43 @@ extern "C" {
/* IO definitions */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#define __I volatile /* defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#define __I volatile const /* defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
#define __O volatile /* defines 'write only' permissions */
#define __IO volatile /* defines 'read / write' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef __I uint64_t vuc64; /* Read Only */
typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I uint8_t vuc8; /* Read Only */
typedef __I uint64_t vuc64; /* Read Only */
typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I uint8_t vuc8; /* Read Only */
typedef const uint64_t uc64; /* Read Only */
typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */
typedef const uint8_t uc8; /* Read Only */
typedef const uint8_t uc8; /* Read Only */
typedef __I int64_t vsc64; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */
typedef __I int64_t vsc64; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */
typedef const int64_t sc64; /* Read Only */
typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */
typedef const int64_t sc64; /* Read Only */
typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */
typedef __IO uint64_t vu64;
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint8_t u8;
typedef __IO int64_t vs64;
typedef __IO int32_t vs32;
@@ -63,8 +63,8 @@ typedef __IO int8_t vs8;
typedef int64_t s64;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef int16_t s16;
typedef int8_t s8;
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
@@ -104,18 +104,18 @@ typedef struct{
/* memory mapped structure for SysTick */
typedef struct
{
__IO u32 CTLR;
__IO u32 SR;
__IO u64 CNT;
__IO u64 CMP;
__IO uint32_t CTLR;
__IO uint32_t SR;
__IO uint64_t CNT;
__IO uint64_t CMP;
}SysTick_Type;
#define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000)
@@ -127,7 +127,7 @@ typedef struct
*
* @return none
*/
RV_STATIC_INLINE void __enable_irq()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
{
__asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
}
@@ -139,7 +139,7 @@ RV_STATIC_INLINE void __enable_irq()
*
* @return none
*/
RV_STATIC_INLINE void __disable_irq()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
}
@@ -151,13 +151,13 @@ RV_STATIC_INLINE void __disable_irq()
*
* @return none
*/
RV_STATIC_INLINE void __NOP()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
{
__asm volatile ("nop");
}
/*********************************************************************
* @fn NVIC_EnableIRQ
* @fn NVIC_EnableIRQ
*
* @brief Disable Interrupt
*
@@ -165,13 +165,13 @@ RV_STATIC_INLINE void __NOP()
*
* @return none
*/
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_DisableIRQ
* @fn NVIC_DisableIRQ
*
* @brief Disable Interrupt
*
@@ -179,22 +179,22 @@ RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*
* @return none
*/
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_GetStatusIRQ
* @fn NVIC_GetStatusIRQ
*
* @brief Get Interrupt Enable State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - 1: Interrupt Pending Enable
* 0 - Interrupt Pending Disable
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@@ -206,10 +206,10 @@ RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - 1: Interrupt Pending Enable
* 0 - Interrupt Pending Disable
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@@ -223,7 +223,7 @@ RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*
* @return none
*/
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@@ -237,7 +237,7 @@ RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*
* @return none
*/
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@@ -250,9 +250,9 @@ RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Active
* 0 - Interrupt No Active
* 0 - Interrupt No Active
*/
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@@ -263,18 +263,18 @@ RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* priority: bit7 - pre-emption priority
* bit6-bit4 - subpriority
* priority - bit7 - Pre-emption Priority
* bit[6:5] - Subpriority
*
* @return none
*/
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
{
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
}
/*********************************************************************
* @fn __WFI
* @fn __WFI
*
* @brief Wait for Interrupt
*
@@ -287,7 +287,36 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
}
/*********************************************************************
* @fn __WFE
* @fn _SEV
*
* @brief Set Event
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
{
uint32_t t;
t = NVIC->SCTLR;
NVIC->SCTLR |= (1<<3)|(1<<5);
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
}
/*********************************************************************
* @fn _WFE
*
* @brief Wait for Events
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
{
NVIC->SCTLR |= (1<<3);
asm volatile ("wfi");
}
/*********************************************************************
* @fn __WFE
*
* @brief Wait for Events
*
@@ -295,13 +324,9 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
{
uint32_t t;
t = NVIC->SCTLR;
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
asm volatile ("wfi");
asm volatile ("wfi");
_SEV();
_WFE();
_WFE();
}
/*********************************************************************
@@ -310,13 +335,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
* @brief Set VTF Interrupt
*
* @param addr - VTF interrupt service function base address.
* IRQn - Interrupt Numbers
* num - VTF Interrupt Numbers
* NewState - DISABLE or ENABLE
* IRQn - Interrupt Numbers
* num - VTF Interrupt Numbers
* NewState - DISABLE or ENABLE
*
* @return none
*/
RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
if(num > 3) return ;
if (NewState != DISABLE)
@@ -331,18 +356,195 @@ RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, Func
}
/*********************************************************************
* @fn NVIC_SystemReset
* @fn NVIC_SystemReset
*
* @brief Initiate a system reset request
*
* @return none
*/
RV_STATIC_INLINE void NVIC_SystemReset(void)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
/*********************************************************************
* @fn __AMOADD_W
*
* @brief Atomic Add with 32bit value
* Atomically ADD 32bit value with value in memory using amoadd.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ADDed
*
* @return return memory value + add value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoadd.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOAND_W
*
* @brief Atomic And with 32bit value
* Atomically AND 32bit value with value in memory using amoand.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ANDed
*
* @return return memory value & and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoand.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMAX_W
*
* @brief Atomic signed MAX with 32bit value
* Atomically signed max compare 32bit value with value in memory using amomax.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amomax.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMAXU_W
*
* @brief Atomic unsigned MAX with 32bit value
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
{
uint32_t result;
__asm volatile ("amomaxu.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMIN_W
*
* @brief Atomic signed MIN with 32bit value
* Atomically signed min compare 32bit value with value in memory using amomin.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the smaller value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amomin.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMINU_W
*
* @brief Atomic unsigned MIN with 32bit value
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the smaller value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
{
uint32_t result;
__asm volatile ("amominu.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOOR_W
*
* @brief Atomic OR with 32bit value
* Atomically OR 32bit value with value in memory using amoor.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ORed
*
* @return return memory value | and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoor.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOSWAP_W
*
* @brief Atomically swap new 32bit value into memory using amoswap.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* newval - New value to be stored into the address
*
* @return return the original value in memory
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
{
uint32_t result;
__asm volatile ("amoswap.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
return result;
}
/*********************************************************************
* @fn __AMOXOR_W
*
* @brief Atomic XOR with 32bit value
* Atomically XOR 32bit value with value in memory using amoxor.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be XORed
*
* @return return memory value ^ and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoxor.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/* Core_Exported_Functions */
extern uint32_t __get_MSTATUS(void);
EVT/EXAM/SRC/Debug/debug.c
+6 -5
View File
@@ -5,11 +5,11 @@
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for UART
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "debug.h"
static uint8_t p_us = 0;
@@ -177,6 +177,7 @@ int _write(int fd, char *buf, int size)
*
* @return size: Data length
*/
__attribute__((used))
void *_sbrk(ptrdiff_t incr)
{
extern char _end[];
EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+67 -18
View File
@@ -4,11 +4,11 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_H
#define __CH32V20x_H
@@ -17,7 +17,7 @@ extern "C" {
#endif
#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6)
#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8 */
#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
//#define CH32V20x_D8 /* CH32V203RBT6 */
//#define CH32V20x_D8W /* CH32V208 */
@@ -37,6 +37,13 @@ extern "C" {
#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
/* CH32V20x Standard Peripheral Library version number */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x08) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
/* Interrupt Number Definition, according to the selected device */
typedef enum IRQn
{
@@ -523,22 +530,64 @@ typedef struct
uint16_t RESERVED7;
__IO uint16_t CCER;
uint16_t RESERVED8;
__IO uint16_t CNT;
uint16_t RESERVED9;
union
{
__IO uint32_t CNT_R32;
struct
{
__IO uint16_t CNT;
uint16_t RESERVED9;
};
};
__IO uint16_t PSC;
uint16_t RESERVED10;
__IO uint16_t ATRLR;
uint16_t RESERVED11;
union
{
__IO uint32_t ATRLR_R32;
struct
{
__IO uint16_t ATRLR;
uint16_t RESERVED11;
};
};
__IO uint16_t RPTCR;
uint16_t RESERVED12;
__IO uint16_t CH1CVR;
uint16_t RESERVED13;
__IO uint16_t CH2CVR;
uint16_t RESERVED14;
__IO uint16_t CH3CVR;
uint16_t RESERVED15;
__IO uint16_t CH4CVR;
uint16_t RESERVED16;
union
{
__IO uint32_t CH1CVR_R32;
struct
{
__IO uint16_t CH1CVR;
uint16_t RESERVED13;
};
};
union
{
__IO uint32_t CH2CVR_R32;
struct
{
__IO uint16_t CH2CVR;
uint16_t RESERVED14;
};
};
union
{
__IO uint32_t CH3CVR_R32;
struct
{
__IO uint16_t CH3CVR;
uint16_t RESERVED15;
};
};
union
{
__IO uint32_t CH4CVR_R32;
struct
{
__IO uint16_t CH4CVR;
uint16_t RESERVED16;
};
};
__IO uint16_t BDTR;
uint16_t RESERVED17;
__IO uint16_t DMACFGR;
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_dbgmcu.h
+1 -1
View File
@@ -44,7 +44,7 @@ uint32_t DBGMCU_GetDEVID(void);
uint32_t __get_DEBUG_CR(void);
void __set_DEBUG_CR(uint32_t value);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
uint32_t DBGMCU_GetCHIPID( void );
#ifdef __cplusplus
}
#endif
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h
+1
View File
@@ -181,6 +181,7 @@ void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
void GPIO_IPD_Unused(void);
#ifdef __cplusplus
}
EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c
+582 -581
View File
File diff suppressed because it is too large Load Diff
EVT/EXAM/SRC/Peripheral/src/ch32v20x_dbgmcu.c
+44 -17
View File
@@ -22,7 +22,7 @@
*/
uint32_t DBGMCU_GetREVID(void)
{
return ((*(uint32_t *)0x1FFFF704) >> 16);
return ((*(uint32_t *)0x1FFFF704) >> 16);
}
/*********************************************************************
@@ -34,7 +34,7 @@ uint32_t DBGMCU_GetREVID(void)
*/
uint32_t DBGMCU_GetDEVID(void)
{
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
}
/*********************************************************************
@@ -46,10 +46,10 @@ uint32_t DBGMCU_GetDEVID(void)
*/
uint32_t __get_DEBUG_CR(void)
{
uint32_t result;
uint32_t result;
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
return (result);
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
return (result);
}
/*********************************************************************
@@ -63,7 +63,7 @@ uint32_t __get_DEBUG_CR(void)
*/
void __set_DEBUG_CR(uint32_t value)
{
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
}
@@ -84,17 +84,44 @@ void __set_DEBUG_CR(uint32_t value)
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
uint32_t val;
uint32_t val;
if(NewState != DISABLE)
{
__set_DEBUG_CR(DBGMCU_Periph);
}
else
{
val = __get_DEBUG_CR();
val &= ~(uint32_t)DBGMCU_Periph;
__set_DEBUG_CR(val);
}
if(NewState != DISABLE)
{
__set_DEBUG_CR(DBGMCU_Periph);
}
else
{
val = __get_DEBUG_CR();
val &= ~(uint32_t)DBGMCU_Periph;
__set_DEBUG_CR(val);
}
}
/*********************************************************************
* @fn DBGMCU_GetCHIPID
*
* @brief Returns the CHIP identifier.
*
* @return Device identifier.
* ChipID List-
* CH32V203C8U6-0x203005x0
* CH32V203C8T6-0x203105x0
* CH32V203K8T6-0x203205x0
* CH32V203C6T6-0x203305x0
* CH32V203K6T6-0x203505x0
* CH32V203G6U6-0x203605x0
* CH32V203G8R6-0x203B05x0
* CH32V203F8U6-0x203E05x0
* CH32V203F6P6-0x203705x0-0x203905x0
* CH32V203F8P6-0x203A05x0
* CH32V203RBT6-0x203405xC
* CH32V208WBU6-0x208005xC
* CH32V208RBT6-0x208105xC
* CH32V208CBU6-0x208205xC
* CH32V208GBU6-0x208305xC
*/
uint32_t DBGMCU_GetCHIPID( void )
{
return( *( uint32_t * )0x1FFFF704 );
}
EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c
+351 -9
View File
@@ -4,11 +4,11 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the GPIO firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_gpio.h"
#include "ch32v20x_rcc.h"
@@ -366,8 +366,8 @@ void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
* @param GPIO_Pin - specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* BitVal - specifies the value to be written to the selected bit.
* Bit_SetL - to clear the port pin.
* Bit_SetH - to set the port pin.
* Bit_RESET - to clear the port pin.
* Bit_SET - to set the port pin.
*
* @return none
*/
@@ -582,7 +582,7 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
}
else /* [31:0] 1bit */
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF ) >> 0x15) * 0x10));
}
}
else
@@ -608,7 +608,7 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
/* Set bit */
if(NewState != DISABLE)
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10));
}
if((GPIO_Remap & 0x80000000) == 0x80000000)
@@ -664,3 +664,345 @@ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
AFIO->PCFR1 &= ~(1 << 23);
}
}
/*********************************************************************
* @fn GPIO_IPD_Unused
*
* @brief Configure unused GPIO as input pull-up.
*
* @param none
*
* @return none
*/
void GPIO_IPD_Unused(void)
{
GPIO_InitTypeDef GPIO_InitStructure = {0};
uint32_t chip = 0;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB \
| RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD|RCC_APB2Periph_AFIO,ENABLE);
chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0);
switch(chip)
{
case 0x20370500: //CH32V203F6P6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\
|GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6\
|GPIO_Pin_7|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203A0500: //CH32V203F8P6
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11|GPIO_Pin_12\
|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
|GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_8\
|GPIO_Pin_9|GPIO_Pin_10\
|GPIO_Pin_11|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203E0500: //CH32V203F8U6
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_12|GPIO_Pin_13;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20360500: //CH32V203G6U6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203B0500: //CH32V203G8R6
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20350500: //CH32V203K6T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20320500: //CH32V203K8T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20330500: //CH32V203C6T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20310500: //CH32V203C8T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20300500: //CH32V203C8U6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2034050C: //CH32V203RBT6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2083050C: //CH32V208GBU6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_9|GPIO_Pin_10\
|GPIO_Pin_11|GPIO_Pin_12\
|GPIO_Pin_13|GPIO_Pin_14\
|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2082050C: //CH32V208CBU6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2081050C: //CH32V208RBT6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
default:
{
break;
}
}
}
EVT/EXAM/SRC/Peripheral/src/ch32v20x_pwr.c
+8 -12
View File
@@ -4,11 +4,11 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the PWR firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_pwr.h"
#include "ch32v20x_rcc.h"
@@ -185,7 +185,7 @@ void PWR_EnterSTANDBYMode(void)
* PWR_FLAG_SB - StandBy flag
* PWR_FLAG_PVDO - PVD Output
*
* @return none
* @return The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
@@ -373,14 +373,10 @@ void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
tmpreg |= PWR_Regulator;
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
//2K+30K in standby power.
tmpreg |= (0x1 << 16) | (0x1 << 17);
//2K+30K in standby LV .
tmpreg |= (0x1 << 20);
#else
//RAM in standby power.
tmpreg |= ( ( uint32_t )1 << 16 );
//RAM in standby LV .
tmpreg |= ( ( uint32_t )1 << 20 );
#endif
EVT/EXAM/SRC/Peripheral/src/ch32v20x_tim.c
+1 -1
View File
@@ -497,7 +497,7 @@ void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
*
* @brief Enables or disables the TIM peripheral Main Outputs.
*
* @param TIMx - where x can be 1 to 4 to select the TIM peripheral.
* @param TIMx - where x can be 1/8/9/10 to select the TIM peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S
+1 -1
View File
@@ -3,7 +3,7 @@
;* Author : WCH
;* Version : V1.0.0
;* Date : 2021/06/06
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
;* vector table for eclipse toolchain.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.