diff --git a/EVT/CH32V20x_List.txt b/EVT/CH32V20x_List.txt
index e27cd51..e3676bf 100644
--- a/EVT/CH32V20x_List.txt
+++ b/EVT/CH32V20x_List.txt
@@ -1,5 +1,5 @@
-南京沁恒微电子股份有限公司 2024.04
+南京沁恒微电子股份有限公司 2025.10
最新资料请到我们的网站上查询
https://wch.cn
@@ -20,7 +20,7 @@ https://wch.cn
| | | | |-- Ld：ld文件
| | | | |-- Peripheral：基本外设驱动源文件及头文件
| | | | |-- Startup：启动文件。针对用户使用芯片型号包含下列相应的启动文件，同时在ch32v20x.h文件中选择匹配芯片型号定义
- | | | | | |-- startup_ch32v20x_D6.S：适用于CH32V203F6-CH32V203G6-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8系列
+ | | | | | |-- startup_ch32v20x_D6.S：适用于CH32V203F6-CH32V203G6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8系列
| | | | | |-- startup_ch32v20x_D8.S：适用于CH32V203RB系列
| | | | | |-- startup_ch32v20x_D8W.S：适用于CH32V208系列
| | | |-- ADC
@@ -43,6 +43,8 @@ https://wch.cn
| | | | | |-- I2C_OP_CH223：通过I2C操作CH223例程 ——仅适用于CH32V20x_D8
| | | | |-- WS2812_LED
| | | | | |-- WS2812_LED：通过SPI\PWM操作WS2812例程
+ | | | | |-- CoreMark
+ | | | | | |-- CoreMark：168M（12M_HSE）系统时钟下CoreMark跑分例程——仅适用于CH32V20x_D6,168M仅适用于商业级应用：0℃ ≤TA ≤ 70℃且散热良好
| | | |-- BLE ——仅适用于CH32V20x_D8W
| | | | |-- BackupUpgrade_IAP：备份无线升级IAP例程，检测当前代码标志，判断是否搬运备份区代码到用户区并运行用户区代码
| | | | |-- BackupUpgrade_OTA：备份无线升级用户例程，外设从机例程基础上添加OTA功能，可将升级固件保存到备份区后跳转IAP程序进行升级
@@ -157,8 +159,10 @@ https://wch.cn
| | | | |-- Stop_Mode：低功耗，停机模式例程
| | | | |-- Standby_RAM_LV_Mode：待机模式开启LV时，RAM 2K、30K低功耗数据保持例程
| | | | |-- Standby_RAM_Mode：待机模式不开启LV时，RAM 2K、30K低功耗数据保持例程
+ | | | | |-- Standby_RAM_Application：待机模式，RAM 2K、30K低功耗数据保持应用例程
| | | | |-- PVD_Wakeup：STOP模式PVD中断唤醒例程
| | | | |-- PVD_VoltageJudger：PVD电压判定例程
+ | | | | |-- Stop_Mode_RTC_Wakeup：RTC唤醒停机模式例程
| | | |-- PMP
| | | | |-- PMP：物理内存保护例程
| | | |-- RCC
@@ -198,6 +202,10 @@ https://wch.cn
| | | | |-- Synchro_Timer：定时器同步模式
| | | | |-- TIM_DMA：定时器使用DMA例程
| | | | |-- Encoder：定时器编码器例程
+ | | | | |-- TIM_INT：定时器中断例程
+ | | | | |-- TIM_Continuous：Timer continuous routines
+ | | | | |-- PWM_Phase-shifted：Timer PWM Phase shifted routines
+ | | | | |-- PWM_6_Step：Timer 6_Step PWM routines
| | | |-- TOUCHKEY
| | | | |-- TKey：TouchKey检测例程
| | | |-- USART
diff --git a/EVT/CH32V20x_List_EN.txt b/EVT/CH32V20x_List_EN.txt
index 572edf7..4be7448 100644
--- a/EVT/CH32V20x_List_EN.txt
+++ b/EVT/CH32V20x_List_EN.txt
@@ -1,5 +1,5 @@
-Nanjing Qinheng Microelectronics Co., Ltd. 2024.04
+Nanjing Qinheng Microelectronics Co., Ltd. 2025.10
https://wch-ic.com
@@ -19,7 +19,7 @@ Directory
| | | | |-- Ld: ld file
| | | | |-- Peripheral: basic peripheral driver source file and header file
| | | | |-- Startup: startup file. For different devices selected by users, the following 3 startup files are provided, and the matched device definition is selected in the ch32v20x.h file.
- | | | | | |-- startup_ch32v20x_D6.S: applied to the CH32V203F6-CH32V203G6-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
+ | | | | | |-- startup_ch32v20x_D6.S: applied to the CH32V203F6-CH32V203G6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
| | | | | |-- startup_ch32v20x_D8.S: applied to the CH32V203RB
| | | | | |-- startup_ch32v20x_D8W.S: applied to the CH32V208
| | | |-- ADC
@@ -42,6 +42,8 @@ Directory
| | | | | |-- I2C_OP_CH223锛欼2C Operates CH223 routine, only applied to CH32V20x_D8
| | | | |-- WS2812_LED
| | | | | |-- WS2812_LED锛歋PI\PWM Operates WS2812_LED routine
+ | | | | |-- CoreMark
+ | | | | | |-- CoreMark锛欳oreMark routine under 168M锛12M_HSE锛 system conditions鈥斺攐nly applied to CH32V20x_D6,168M is only suitable for Commercial Grade applications: 0鈩 鈮 TA 鈮 70鈩 with good heat dissipation
| | | |-- BLE ----only for CH32V20x_D8W
| | | | |-- BackupUpgrade_IAP: backup wireless upgrade IAP routine. Detect the current code flag, determine whether to move the code from the backup area to the user area, and run the code in the user area
| | | | |-- BackupUpgrade_OTA: backup wireless upgrade user routine. Add OTA function to peripheral slave routines, save the upgrade firmware to the backup area and jump to the IAP program to upgrade
@@ -156,8 +158,11 @@ Directory
| | | | |-- Stop_Mode: low power, stop mode routine
| | | | |-- Standby_RAM_LV_Mode: when LV is enabled in standby mode, RAM 2k and 30K low-power data holding routines
| | | | |-- Standby_RAM_Mode:when LV is not enabled in standby mode, RAM 2k and 30K low-power data holding routines
+ | | | | |-- Standby_RAM_Application锛歐hen MCU in standby mode, RAM 2k and 30K low-power data holding application routine
| | | | |-- PVD_Wakeup锛歋TOP mode PVD wakeup MCU Routine
| | | | |-- PVD_VoltageJudger锛歅VD voltage Judger Routine
+ | | | | |-- Standby_RAM_Application锛歊AM data holding in standby mode Routine
+ | | | | |-- Stop_Mode_RTC_Wakeup锛歊TC wakeup Stop mode routines
| | | |-- PMP
| | | | |-- PMP锛歅hysical memory protection Routine
| | | |-- RCC
@@ -197,6 +202,10 @@ Directory
| | | | |-- Synchro_Timer:timer synchronization mode
| | | | |-- TIM_DMA: timer DMA routines
| | | | |-- Encode:Timer encoder mode routines
+ | | | | |-- TIM_INT:Timer interput mode routines
+ | | | | |-- TIM_Continuous锛歍imer continuous routines
+ | | | | |-- PWM_Phase-shifted锛歍imer PWM Phase shifted routines
+ | | | | |-- PWM_6_Step锛歍imer 6_Step PWM routines
| | | |-- TOUCHKEY
| | | | |-- TKey:TouchKey Detection Routine
| | | |-- USART
diff --git a/EVT/EXAM/ADC/ADC_DMA/.template b/EVT/EXAM/ADC/ADC_DMA/.template
index 2c9b66f..373245d 100644
--- a/EVT/EXAM/ADC/ADC_DMA/.template
+++ b/EVT/EXAM/ADC/ADC_DMA/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/ADC_DMA/User/main.c b/EVT/EXAM/ADC/ADC_DMA/User/main.c
index 429f9ed..ff18c60 100644
--- a/EVT/EXAM/ADC/ADC_DMA/User/main.c
+++ b/EVT/EXAM/ADC/ADC_DMA/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2021/06/06
+ * Version : V1.0.1
+ * Date : 2025/01/17
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -22,7 +22,7 @@
/* Global Variable */
u16 TxBuf[1024];
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -65,46 +65,6 @@ void ADC_Function_Init(void)
}
-/*********************************************************************
- * @fn Get_ADC_Val
- *
- * @brief Returns ADCx conversion result data.
- *
- * @param ch - ADC channel.
- * ADC_Channel_0 - ADC Channel0 selected.
- * ADC_Channel_1 - ADC Channel1 selected.
- * ADC_Channel_2 - ADC Channel2 selected.
- * ADC_Channel_3 - ADC Channel3 selected.
- * ADC_Channel_4 - ADC Channel4 selected.
- * ADC_Channel_5 - ADC Channel5 selected.
- * ADC_Channel_6 - ADC Channel6 selected.
- * ADC_Channel_7 - ADC Channel7 selected.
- * ADC_Channel_8 - ADC Channel8 selected.
- * ADC_Channel_9 - ADC Channel9 selected.
- * ADC_Channel_10 - ADC Channel10 selected.
- * ADC_Channel_11 - ADC Channel11 selected.
- * ADC_Channel_12 - ADC Channel12 selected.
- * ADC_Channel_13 - ADC Channel13 selected.
- * ADC_Channel_14 - ADC Channel14 selected.
- * ADC_Channel_15 - ADC Channel15 selected.
- * ADC_Channel_16 - ADC Channel16 selected.
- * ADC_Channel_17 - ADC Channel17 selected.
- *
- * @return none
- */
-u16 Get_ADC_Val(u8 ch)
-{
- u16 val;
-
- ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5);
- ADC_SoftwareStartConvCmd(ADC1, ENABLE);
-
- while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));
- val = ADC_GetConversionValue(ADC1);
-
- return val;
-}
-
/*********************************************************************
* @fn DMA_Tx_Init
*
@@ -180,7 +140,9 @@ int main(void)
ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 1, ADC_SampleTime_239Cycles5);
ADC_SoftwareStartConvCmd(ADC1, ENABLE);
- Delay_Ms(50);
+ while(DMA_GetFlagStatus(DMA1_FLAG_TC1) == RESET) /* Wait until ADC1 DMA1 Transfer Complete */
+ {
+ }
ADC_SoftwareStartConvCmd(ADC1, DISABLE);
for(i = 0; i < 1024; i++){
diff --git a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/AnalogWatchdog/.template b/EVT/EXAM/ADC/AnalogWatchdog/.template
index ca19a1c..ede7691 100644
--- a/EVT/EXAM/ADC/AnalogWatchdog/.template
+++ b/EVT/EXAM/ADC/AnalogWatchdog/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/Auto_Injection/.template b/EVT/EXAM/ADC/Auto_Injection/.template
index ee9adf6..1803d48 100644
--- a/EVT/EXAM/ADC/Auto_Injection/.template
+++ b/EVT/EXAM/ADC/Auto_Injection/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/Auto_Injection/User/main.c b/EVT/EXAM/ADC/Auto_Injection/User/main.c
index 2722fce..3f51e82 100644
--- a/EVT/EXAM/ADC/Auto_Injection/User/main.c
+++ b/EVT/EXAM/ADC/Auto_Injection/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2023/12/29
+ * Version : V1.0.1
+ * Date : 2025/01/17
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -19,7 +19,7 @@
#include "debug.h"
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -69,46 +69,6 @@ void ADC_Function_Init(void)
}
-/*********************************************************************
- * @fn Get_ADC_Val
- *
- * @brief Returns ADCx conversion result data.
- *
- * @param ch - ADC channel.
- * ADC_Channel_0 - ADC Channel0 selected.
- * ADC_Channel_1 - ADC Channel1 selected.
- * ADC_Channel_2 - ADC Channel2 selected.
- * ADC_Channel_3 - ADC Channel3 selected.
- * ADC_Channel_4 - ADC Channel4 selected.
- * ADC_Channel_5 - ADC Channel5 selected.
- * ADC_Channel_6 - ADC Channel6 selected.
- * ADC_Channel_7 - ADC Channel7 selected.
- * ADC_Channel_8 - ADC Channel8 selected.
- * ADC_Channel_9 - ADC Channel9 selected.
- * ADC_Channel_10 - ADC Channel10 selected.
- * ADC_Channel_11 - ADC Channel11 selected.
- * ADC_Channel_12 - ADC Channel12 selected.
- * ADC_Channel_13 - ADC Channel13 selected.
- * ADC_Channel_14 - ADC Channel14 selected.
- * ADC_Channel_15 - ADC Channel15 selected.
- * ADC_Channel_16 - ADC Channel16 selected.
- * ADC_Channel_17 - ADC Channel17 selected.
- *
- * @return none
- */
-u16 Get_ADC_Val(u8 ch)
-{
- u16 val;
-
- ADC_SoftwareStartConvCmd(ADC1, ENABLE);
-
- while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));
-
- val = ADC_GetConversionValue(ADC1);
-
- return val;
-}
-
/*********************************************************************
* @fn Get_ConversionVal
*
diff --git a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/Discontinuous_mode/.template b/EVT/EXAM/ADC/Discontinuous_mode/.template
index 640fadf..e234311 100644
--- a/EVT/EXAM/ADC/Discontinuous_mode/.template
+++ b/EVT/EXAM/ADC/Discontinuous_mode/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/main.c b/EVT/EXAM/ADC/Discontinuous_mode/User/main.c
index a98808d..e9ef89c 100644
--- a/EVT/EXAM/ADC/Discontinuous_mode/User/main.c
+++ b/EVT/EXAM/ADC/Discontinuous_mode/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2021/06/06
+ * Version : V1.0.1
+ * Date : 2025/01/16
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -21,7 +21,7 @@
*/
#include "debug.h"
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -55,12 +55,13 @@ void ADC_Function_Init(void)
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
- ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigInjecConv_T1_CC4;
+ ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_Init(ADC1, &ADC_InitStructure);
ADC_InjectedSequencerLengthConfig(ADC1, 3);
+ ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_T1_CC4);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_1, 1, ADC_SampleTime_239Cycles5);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_3, 2, ADC_SampleTime_239Cycles5);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_4, 3, ADC_SampleTime_239Cycles5);
@@ -92,16 +93,10 @@ void ADC_Function_Init(void)
*/
void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp)
{
- GPIO_InitTypeDef GPIO_InitStructure = {0};
TIM_OCInitTypeDef TIM_OCInitStructure = {0};
TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure = {0};
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_TIM1, ENABLE);
-
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
TIM_TimeBaseInitStructure.TIM_Period = arr;
TIM_TimeBaseInitStructure.TIM_Prescaler = psc;
@@ -116,9 +111,6 @@ void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp)
TIM_OC4Init(TIM1, &TIM_OCInitStructure);
TIM_CtrlPWMOutputs(TIM1, ENABLE);
- TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Disable);
- TIM_ARRPreloadConfig(TIM1, ENABLE);
- TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update);
TIM_Cmd(TIM1, ENABLE);
}
diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/.template b/EVT/EXAM/ADC/DualADC_AlternateTrigger/.template
index 4754727..ed6717e 100644
--- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/.template
+++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c
index e40f32f..eebad24 100644
--- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2021/06/06
+ * Version : V1.0.1
+ * Date : 2025/01/16
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -22,8 +22,8 @@
/* Global Variable */
u16 ADC_val[2];
-s16 Calibrattion_Val1 = 0;
-s16 Calibrattion_Val2 = 0;
+vs16 Calibrattion_Val1 = 0;
+vs16 Calibrattion_Val2 = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -52,7 +52,7 @@ void ADC_Function_Init(void)
ADC_InitStructure.ADC_Mode = ADC_Mode_AlterTrig;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
- ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigInjecConv_T2_CC1;
+ ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_InitStructure.ADC_OutputBuffer = ADC_OutputBuffer_Disable;
diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/.template b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/.template
index 8630e85..b21cb29 100644
--- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/.template
+++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c
index 795b370..1b76144 100644
--- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c
@@ -27,10 +27,10 @@
/* Global Variable */
u32 TxBuf[1];
u16 Adc_Val[2];
-u16 ADC_Val1, ADC_Val2;
-u8 Injected_IT_Flag, DMA_IT_Flag;
-s16 Calibrattion_Val1 = 0;
-s16 Calibrattion_Val2 = 0;
+vu16 ADC_Val1, ADC_Val2;
+vu8 Injected_IT_Flag, DMA_IT_Flag;
+vs16 Calibrattion_Val1 = 0;
+vs16 Calibrattion_Val2 = 0;
void ADC1_2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/.template b/EVT/EXAM/ADC/DualADC_FastInterleaved/.template
index a5a8e54..1dd7711 100644
--- a/EVT/EXAM/ADC/DualADC_FastInterleaved/.template
+++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c
index 823a02b..3be5fef 100644
--- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c
@@ -16,16 +16,16 @@
*ADC1 channel 1 (PA1), ADC2 channel 1 (PA1)), the rule group channel obtains
*dual ADC conversion data through ADC interrupt.
*
- *Note:only applied toCH32V203
+ *Note:only applied to CH32V20x_D6
*/
#include "debug.h"
/* Global Variable */
u16 Adc_Val[2];
-u32 temp;
-s16 Calibrattion_Val1 = 0;
-s16 Calibrattion_Val2 = 0;
+vu32 temp;
+vs16 Calibrattion_Val1 = 0;
+vs16 Calibrattion_Val2 = 0;
void ADC1_2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/.template b/EVT/EXAM/ADC/DualADC_InjectionSimul/.template
index a08564e..e57292e 100644
--- a/EVT/EXAM/ADC/DualADC_InjectionSimul/.template
+++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c
index 697147d..5863ed1 100644
--- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c
@@ -15,15 +15,15 @@
*Dual ADC injection simultaneous sampling routine:
*ADC1 channel 1 (PA1), ADC2 channel 2 (PA3).
*
- *Note:only applied toCH32V203
+ *Note:only applied to CH32V20x_D6
*/
#include "debug.h"
/* Global Variable */
-u16 ADC_val1, ADC_val2;
-s16 Calibrattion_Val1 = 0;
-s16 Calibrattion_Val2 = 0;
+vu16 ADC_val1, ADC_val2;
+vs16 Calibrattion_Val1 = 0;
+vs16 Calibrattion_Val2 = 0;
/*********************************************************************
* @fn ADC_Function_Init
diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/.template b/EVT/EXAM/ADC/DualADC_RegSimul/.template
index b7e0882..ad0747a 100644
--- a/EVT/EXAM/ADC/DualADC_RegSimul/.template
+++ b/EVT/EXAM/ADC/DualADC_RegSimul/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c
index 2adfd96..73ede96 100644
--- a/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c
@@ -16,7 +16,7 @@
*ADC1 channel 1 (PA1), ADC2 channel 3 (PA3)), and the rule group channel obtains
*dual ADC conversion data through DMA interrupt.
*
- *Note:only applied toCH32V203
+ *Note:only applied to CH32V20x_D6
*/
#include "debug.h"
@@ -24,8 +24,8 @@
/* Global Variable */
u32 TxBuf[1];
u16 Adc_Val[4];
-s16 Calibrattion_Val1 = 0;
-s16 Calibrattion_Val2 = 0;
+vs16 Calibrattion_Val1 = 0;
+vs16 Calibrattion_Val2 = 0;
void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
@@ -75,7 +75,6 @@ void ADC_Function_Init(void)
while(ADC_GetCalibrationStatus(ADC1));
Calibrattion_Val1 = Get_CalibrationValue(ADC1);
-
ADC_Init(ADC2, &ADC_InitStructure);
ADC_RegularChannelConfig(ADC2, ADC_Channel_3, 1, ADC_SampleTime_239Cycles5);
diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/.template b/EVT/EXAM/ADC/DualADC_SlowInterleaved/.template
index 239bc01..b557c19 100644
--- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/.template
+++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c
index 4acf1c3..dfa2b44 100644
--- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2023/12/29
+ * Version : V1.0.1
+ * Date : 2025/10/27
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -16,16 +16,16 @@
*ADC1 channel 1 (PA1), ADC2 channel 1 (PA1)), the rule group channel obtains
*dual ADC conversion data through ADC interrupt.
*
- *Note:Only applied to CH32V203
+ *Note:only applied to CH32V20x_D6
*/
#include "debug.h"
/* Global Variable */
u16 Adc_Val[2];
-u32 temp;
-s16 Calibrattion_Val1 = 0;
-s16 Calibrattion_Val2 = 0;
+vu32 temp;
+vs16 Calibrattion_Val1 = 0;
+vs16 Calibrattion_Val2 = 0;
void ADC1_2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
@@ -153,13 +153,10 @@ int main(void)
ADC_Function_Init();
printf("CalibrattionValue1:%d\n", Calibrattion_Val1);
printf("CalibrattionValue2:%d\n", Calibrattion_Val2);
+ ADC_SoftwareStartConvCmd(ADC1, ENABLE);
while(1)
{
- ADC_SoftwareStartConvCmd(ADC1, ENABLE);
- Delay_Ms(1000);
- ADC_SoftwareStartConvCmd(ADC1, DISABLE);
- Delay_Ms(1000);
}
}
diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/.template b/EVT/EXAM/ADC/ExtLines_Trigger/.template
index 2256c1a..94bc79b 100644
--- a/EVT/EXAM/ADC/ExtLines_Trigger/.template
+++ b/EVT/EXAM/ADC/ExtLines_Trigger/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c
index 76a299e..81ff53a 100644
--- a/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c
+++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2023/12/29
+ * Version : V1.0.1
+ * Date : 2025/01/17
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -23,7 +23,7 @@
#include "debug.h"
/* Global Variable */
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -50,12 +50,13 @@ void ADC_Function_Init(void)
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
- ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4;
+ ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_Init(ADC1, &ADC_InitStructure);
ADC_InjectedSequencerLengthConfig(ADC1, 1);
+ ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_1, 1, ADC_SampleTime_239Cycles5);
ADC_ExternalTrigInjectedConvCmd(ADC1, ENABLE);
diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/Internal_Temperature/.template b/EVT/EXAM/ADC/Internal_Temperature/.template
index b5e9da0..60b03bb 100644
--- a/EVT/EXAM/ADC/Internal_Temperature/.template
+++ b/EVT/EXAM/ADC/Internal_Temperature/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/main.c b/EVT/EXAM/ADC/Internal_Temperature/User/main.c
index dd27c5d..fe2370f 100644
--- a/EVT/EXAM/ADC/Internal_Temperature/User/main.c
+++ b/EVT/EXAM/ADC/Internal_Temperature/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2021/06/06
+ * Version : V1.0.1
+ * Date : 2024/11/29
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -21,7 +21,7 @@
#include "debug.h"
/* Global Variable */
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -33,16 +33,10 @@ s16 Calibrattion_Val = 0;
void ADC_Function_Init(void)
{
ADC_InitTypeDef ADC_InitStructure = {0};
- GPIO_InitTypeDef GPIO_InitStructure = {0};
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
RCC_ADCCLKConfig(RCC_PCLK2_Div8);
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
ADC_DeInit(ADC1);
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/TIM_Trigger/.template b/EVT/EXAM/ADC/TIM_Trigger/.template
index 7a6625c..7a42442 100644
--- a/EVT/EXAM/ADC/TIM_Trigger/.template
+++ b/EVT/EXAM/ADC/TIM_Trigger/.template
@@ -13,5 +13,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
CLKSpeed=1
diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h
index 6142fd8..640e10e 100644
--- a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h
+++ b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_conf.h
@@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : Library configuration file.
+ *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_CONF_H
#define __CH32V20x_CONF_H
diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h
index eaac7e0..333cac7 100644
--- a/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h
+++ b/EVT/EXAM/ADC/TIM_Trigger/User/ch32v20x_it.h
@@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains the headers of the interrupt handlers.
+ *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_IT_H
#define __CH32V20x_IT_H
diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/main.c b/EVT/EXAM/ADC/TIM_Trigger/User/main.c
index ddbe399..625622d 100644
--- a/EVT/EXAM/ADC/TIM_Trigger/User/main.c
+++ b/EVT/EXAM/ADC/TIM_Trigger/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
-* Version : V1.0.0
-* Date : 2021/06/06
+* Version : V1.0.1
+* Date : 2025/09/22
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -13,8 +13,8 @@
/*
*@Note
*TIM trigger ADC conversion routine:
- *ADC channel 1 (PA1) - injection group channel, TIM2 CH1 pin (PA0) TIM trigger,
- *In this mode, an ADC conversion is triggered by an event on TIM2 CH1 TIM trigger, and a JEOC interrupt is generated after
+ *ADC channel 4 (PA1) - injection group channel, TIM1 CH4 pin TIM trigger,
+ *In this mode, an ADC conversion is triggered by an event on TIM1 CH4 TIM trigger, and a JEOC interrupt is generated after
*the conversion is completed.
*
*/
@@ -23,7 +23,7 @@
#include "debug.h"
/* Global Variable */
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
@@ -50,12 +50,13 @@ void ADC_Function_Init(void)
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
- ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigInjecConv_T1_CC4|ADC_ExternalTrigConv_None;
+ ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_Init(ADC1, &ADC_InitStructure);
ADC_InjectedSequencerLengthConfig(ADC1, 1);
+ ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_T1_CC4);
ADC_InjectedChannelConfig(ADC1, ADC_Channel_4, 1, ADC_SampleTime_7Cycles5);
ADC_ExternalTrigInjectedConvCmd(ADC1, ENABLE);
@@ -75,37 +76,8 @@ void ADC_Function_Init(void)
while(ADC_GetCalibrationStatus(ADC1));
Calibrattion_Val = Get_CalibrationValue(ADC1);
-// ADC_BufferCmd(ADC1, ENABLE); //enable buffer
}
-u16 Get_ADC_Val(u8 ch)
-{
- u16 val;
-
- ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_7Cycles5);
- ADC_SoftwareStartConvCmd(ADC1, ENABLE);
-
- while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));
- val = ADC_GetConversionValue(ADC1);
-
- return val;
-}
-
-void GPIO_Toggle_INIT(void)
-{
- GPIO_InitTypeDef GPIO_InitStructure = {0};
-
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-}
/*********************************************************************
* @fn TIM1_PWM_In
*
@@ -116,17 +88,10 @@ void GPIO_Toggle_INIT(void)
void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp)
{
- GPIO_InitTypeDef GPIO_InitStructure = {0};
TIM_OCInitTypeDef TIM_OCInitStructure = {0};
TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure = {0};
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA| RCC_APB2Periph_TIM1, ENABLE);
-// RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE);
-
- GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
- GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
- GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
- GPIO_Init(GPIOA, &GPIO_InitStructure);
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_TIM1, ENABLE);
TIM_TimeBaseInitStructure.TIM_Period = arr;
TIM_TimeBaseInitStructure.TIM_Prescaler = psc;
@@ -141,13 +106,11 @@ void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp)
TIM_OC4Init(TIM1, &TIM_OCInitStructure);
TIM_CtrlPWMOutputs(TIM1, ENABLE);
- TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Disable);
- TIM_ARRPreloadConfig(TIM1, ENABLE);
- TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update);
TIM_Cmd(TIM1, ENABLE);
}
+
/*********************************************************************
- * @fn Get_ConversionVal1
+ * @fn Get_ConversionVal
*
* @brief Get Conversion Value.
*
@@ -157,7 +120,7 @@ void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp)
*/
u16 Get_ConversionVal(s16 val)
{
- if((val + Calibrattion_Val) < 0)
+ if((val + Calibrattion_Val) < 0 || val==0)
return 0;
if((Calibrattion_Val + val) > 4095 || val==4095)
return 4095;
@@ -176,10 +139,10 @@ int main(void)
SystemCoreClockUpdate();
USART_Printf_Init(115200);
printf("SystemClk:%d\r\n", SystemCoreClock);
- GPIO_Toggle_INIT();
+
ADC_Function_Init();
printf("CalibrattionValue:%d\n", Calibrattion_Val);
- TIM1_PWM_In(7200,100-1,3600);
+ TIM1_PWM_In(7200-1,1000-1,3600);
while(1);
}
@@ -195,14 +158,13 @@ void ADC1_2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void ADC1_2_IRQHandler()
{
- u16 ADC_val,ADC;
+ u16 ADC_val;
if(ADC_GetITStatus(ADC1, ADC_IT_JEOC))
{
-// printf("ADC Extline trigger conversion...\r\n");
+ printf("ADC Extline trigger conversion...\r\n");
ADC_val = ADC_GetInjectedConversionValue(ADC1, ADC_InjectedChannel_1);
- ADC= Get_ADC_Val(ADC_Channel_5);
- printf("%04d %04d\r\n",ADC_val ,ADC);
+ printf("JADC:%04d\r\n",Get_ConversionVal(ADC_val));
}
ADC_ClearITPendingBit(ADC1, ADC_IT_JEOC);
diff --git a/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c
index c475192..299d64c 100644
--- a/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/TIM_Trigger/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ADC/Temperature_External_channel/.template b/EVT/EXAM/ADC/Temperature_External_channel/.template
index 873c596..e14739b 100644
--- a/EVT/EXAM/ADC/Temperature_External_channel/.template
+++ b/EVT/EXAM/ADC/Temperature_External_channel/.template
@@ -13,5 +13,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
CLKSpeed=1
diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h
index 6142fd8..640e10e 100644
--- a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h
+++ b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_conf.h
@@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : Library configuration file.
+ *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_CONF_H
#define __CH32V20x_CONF_H
diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h
index eaac7e0..333cac7 100644
--- a/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h
+++ b/EVT/EXAM/ADC/Temperature_External_channel/User/ch32v20x_it.h
@@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains the headers of the interrupt handlers.
+ *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_IT_H
#define __CH32V20x_IT_H
diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/main.c b/EVT/EXAM/ADC/Temperature_External_channel/User/main.c
index f079892..41a8e6c 100644
--- a/EVT/EXAM/ADC/Temperature_External_channel/User/main.c
+++ b/EVT/EXAM/ADC/Temperature_External_channel/User/main.c
@@ -19,7 +19,7 @@
#include "debug.h"
-s16 Calibrattion_Val = 0;
+vs16 Calibrattion_Val = 0;
/*********************************************************************
* @fn ADC_Function_Init
diff --git a/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c
index ac15402..c99327f 100644
--- a/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Temperature_External_channel/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/APPLICATION/CoreMark/.cproject b/EVT/EXAM/APPLICATION/CoreMark/.cproject
new file mode 100644
index 0000000..76a0b92
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/.cproject
@@ -0,0 +1,284 @@
+
+
+
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\ No newline at end of file
diff --git a/EVT/EXAM/APPLICATION/CoreMark/.project b/EVT/EXAM/APPLICATION/CoreMark/.project
new file mode 100644
index 0000000..ae25317
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/.project
@@ -0,0 +1,60 @@
+
+
+ CoreMark
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
+
+ Core
+ 2
+ PARENT-2-PROJECT_LOC/SRC/Core
+
+
+ Debug
+ 2
+ PARENT-2-PROJECT_LOC/SRC/Debug
+
+
+ Ld
+ 2
+ PARENT-2-PROJECT_LOC/SRC/Ld
+
+
+ Peripheral
+ 2
+ PARENT-2-PROJECT_LOC/SRC/Peripheral
+
+
+ Startup
+ 2
+ PARENT-2-PROJECT_LOC/SRC/Startup
+
+
+
+
+
+ 6
+
+ org.eclipse.ui.ide.multiFilter
+ 1.0-name-matches-false-false-*.wvproj
+
+
+
+
\ No newline at end of file
diff --git a/EVT/EXAM/APPLICATION/CoreMark/.template b/EVT/EXAM/APPLICATION/CoreMark/.template
new file mode 100644
index 0000000..fc71d13
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/.template
@@ -0,0 +1,25 @@
+Vendor=WCH
+Toolchain=RISC-V
+Series=CH32V208
+RTOS=NoneOS
+CalibrateSupport=false
+CalibrateCommand=
+MCU=CH32V203C8T6
+Link=WCH-Link
+PeripheralVersion=1.0
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj/CoreMark.hex
+Exe Path=
+Exe Arguments=
+CLKSpeed=1
+DebugInterfaceMode=0
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+SDIPrintf=false
+Disable Power Output=false
+Clear CodeFlash=false
+Disable Code-Protect=false
\ No newline at end of file
diff --git a/EVT/EXAM/APPLICATION/CoreMark/CoreMark.wvproj b/EVT/EXAM/APPLICATION/CoreMark/CoreMark.wvproj
new file mode 100644
index 0000000..78ee02e
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/CoreMark.wvproj
@@ -0,0 +1,436 @@
+{
+ "version": "1.0",
+ "isNormalMRSProject": true,
+ "basic": {
+ "chipInfo": {
+ "vendor": "WCH",
+ "toolchain": "RISC-V",
+ "series": "CH32V208",
+ "rtos": "NoneOS",
+ "mcu": "CH32V203C8T6",
+ "description": "ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.",
+ "link": "WCH-Link",
+ "peripheral_version": "1.0",
+ "calibrateSupport": false,
+ "calibrateCommand": ""
+ },
+ "linkedFolders": [
+ {
+ "name": "Core",
+ "location": "../../SRC/Core"
+ },
+ {
+ "name": "Debug",
+ "location": "../../SRC/Debug"
+ },
+ {
+ "name": "Ld",
+ "location": "../../SRC/Ld"
+ },
+ {
+ "name": "Peripheral",
+ "location": "../../SRC/Peripheral"
+ },
+ {
+ "name": "Startup",
+ "location": "../../SRC/Startup"
+ }
+ ],
+ "removedResources": [
+ {
+ "parentLogicPath": "",
+ "type": "file",
+ "name": "*.wvproj"
+ }
+ ],
+ "projectName": "CoreMark",
+ "architecture": "RISC-V",
+ "projectType": "c"
+ },
+ "buildConfig": {
+ "configurations": [
+ {
+ "buildArtifact": {
+ "artifact_name": "${ProjName}",
+ "artifact_extension": "elf",
+ "output_prefix": "",
+ "artifact_type": "Executable"
+ },
+ "parallelizationNumber": "optimal",
+ "stop_on_first_build_error": true,
+ "pre_script": "",
+ "pre_script_description": "",
+ "post_script": "",
+ "post_script_description": "",
+ "excludeResources": [
+ "${project}/Startup/startup_ch32v20x_D8W.S",
+ "${project}/coremark/syscall.c",
+ "${project}/coremark/core_main.c",
+ "${project}/main.c",
+ "${project}/Startup/startup_ch32v20x_D8.S"
+ ],
+ "optimization": {
+ "level": "fast",
+ "message_length": true,
+ "char_is_signed": true,
+ "function_sections": true,
+ "data_sections": true,
+ "no_common_unitialized": true,
+ "do_not_inline_functions": false,
+ "assume_freestanding_environment": false,
+ "disable_builtin": false,
+ "single_precision_constants": false,
+ "position_independent_code": false,
+ "link_time_optimizer": false,
+ "disable_loop_invariant_move": false,
+ "optimize_unused_sections_declared_as_high_code": false,
+ "code_generation_without_hardware_floating": false,
+ "use_pipelines": false,
+ "show_caret_indicating_the_column": false,
+ "other_optimization_flags": "-funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting"
+ },
+ "warnings": {
+ "check_syntax_only": false,
+ "pedantic": false,
+ "pedantic_warnings_as_errors": false,
+ "inhibit_all_warnings": false,
+ "warn_on_various_unused_elements": true,
+ "warn_on_uninitialized_variables": true,
+ "enable_all_common_warnings": false,
+ "enable_extra_warnings": false,
+ "warn_on_undeclared_global_function": false,
+ "warn_on_implicit_conversions": false,
+ "warn_if_pointer_arthmetic": false,
+ "warn_if_padding_is_included": false,
+ "warn_if_shadowed_variable": false,
+ "warn_if_suspicious_logical_ops": false,
+ "warn_if_struct_is_returned": false,
+ "warn_if_floats_are_compared_as_equal": false,
+ "generate_errors_instead_of_warnings": false,
+ "other_warning_flags": ""
+ },
+ "debugging": {
+ "debug_level": "default",
+ "debug_format": "default",
+ "generate_prof_information": false,
+ "generate_gprof_information": false,
+ "other_debugging_flags": ""
+ },
+ "assembler": {
+ "preprocessor": {
+ "use_preprocessor": true,
+ "do_not_search_system_directories": false,
+ "preprocess_only": false,
+ "defined_symbols": [],
+ "undefined_symbols": []
+ },
+ "includes": {
+ "include_paths": [
+ "${project}/Startup"
+ ],
+ "include_system_paths": [],
+ "include_files": []
+ },
+ "other_warning_flags": "",
+ "miscellaneous": {
+ "assembler_flags": [],
+ "generate_assembler_listing": false,
+ "save_temporary_files": false,
+ "verbose": false,
+ "other_assembler_flags": ""
+ }
+ },
+ "ccompiler": {
+ "preprocessor": {
+ "do_not_search_system_directories": false,
+ "preprocess_only": false,
+ "defined_symbols": [
+ "HSE_VALUE_12M"
+ ],
+ "undefined_symbols": []
+ },
+ "includes": {
+ "include_paths": [
+ "${project}/Debug",
+ "${project}/Core",
+ "${project}/User",
+ "${project}/Peripheral/inc",
+ "${project}/coremark"
+ ],
+ "include_system_paths": [],
+ "include_files": []
+ },
+ "optimization": {
+ "language_standard": "gnu99",
+ "other_optimization_flags": ""
+ },
+ "warnings": {
+ "warn_if_a_global_function_has_no_prototype": false,
+ "warn_if_a_function_has_no_arg_type": false,
+ "warn_if_wrong_cast": false,
+ "other_warning_flags": ""
+ },
+ "miscellaneous": {
+ "generate_assembler_listing": false,
+ "save_temporary_files": false,
+ "verbose": false,
+ "other_compiler_flags": ""
+ }
+ },
+ "cppcompiler": {
+ "preprocessor": {
+ "do_not_search_system_directories": false,
+ "do_not_search_system_cpp_directories": false,
+ "preprocess_only": false,
+ "defined_symbols": [],
+ "undefined_symbols": []
+ },
+ "includes": {
+ "include_paths": [],
+ "include_system_paths": [],
+ "include_files": []
+ },
+ "optimization": {
+ "cpp_language_standard": "gnucpp11",
+ "abi_version": "0",
+ "do_not_use_exceptions": false,
+ "do_not_use_rtti": false,
+ "do_not_use__cxa_atexit": false,
+ "do_not_use_thread_safe_statics": false,
+ "other_optimization_flags": ""
+ },
+ "warnings": {
+ "warn_on_abi_violations": false,
+ "warn_on_class_privacy": false,
+ "warn_on_no_except_expressions": false,
+ "warn_on_virtual_destructors": false,
+ "warn_on_uncast_null": false,
+ "warn_on_sign_promotion": false,
+ "warn_about_effictive_cpp_violcations": false,
+ "other_warning_flags": ""
+ },
+ "miscellaneous": {
+ "generate_assembler_listing": false,
+ "save_temporary_files": false,
+ "verbose": false,
+ "other_compiler_flags": ""
+ }
+ },
+ "clinker": {
+ "general": {
+ "scriptFiles": [
+ "${project}/Ld/Link.ld"
+ ],
+ "do_not_use_standard_start_files": true,
+ "do_not_use_default_libraries": false,
+ "no_startup_or_default_libs": false,
+ "remove_unused_sections": true,
+ "print_removed_sections": false,
+ "omit_all_symbol_information": false
+ },
+ "libraries": {
+ "libraries": [],
+ "library_search_path": []
+ },
+ "miscellaneous": {
+ "picolibc": "disabled",
+ "linker_flags": [],
+ "other_objects": [],
+ "generate_map": "\"${BuildArtifactFileBaseName}.map\"",
+ "cross_reference": false,
+ "print_link_map": false,
+ "use_newlib_nano": true,
+ "use_float_with_nano_printf": false,
+ "use_float_with_nano_scanf": false,
+ "do_not_use_syscalls": true,
+ "verbose": false,
+ "use_wch_printffloat": true,
+ "use_wch_printf": false,
+ "use_iqmath": false,
+ "other_linker_flags": ""
+ }
+ },
+ "cpplinker": {
+ "general": {
+ "scriptFiles": [
+ "${project}/Ld/Link.ld"
+ ],
+ "do_not_use_standard_start_files": true,
+ "do_not_use_default_libraries": false,
+ "no_startup_or_default_libs": false,
+ "remove_unused_sections": true,
+ "print_removed_sections": false,
+ "omit_all_symbol_information": false
+ },
+ "libraries": {
+ "libraries": [],
+ "library_search_path": []
+ },
+ "miscellaneous": {
+ "picolibc": "disabled",
+ "linker_flags": [],
+ "other_objects": [],
+ "generate_map": "\"${BuildArtifactFileBaseName}.map\"",
+ "cross_reference": false,
+ "print_link_map": false,
+ "use_newlib_nano": true,
+ "use_float_with_nano_printf": false,
+ "use_float_with_nano_scanf": false,
+ "do_not_use_syscalls": true,
+ "verbose": false,
+ "use_wch_printffloat": true,
+ "use_wch_printf": false,
+ "use_iqmath": false,
+ "other_linker_flags": ""
+ }
+ },
+ "archiver": {
+ "archiver_flags": "-r"
+ },
+ "createFlash": {
+ "enabled": true,
+ "outputFileFormat": "ihex",
+ "copy_only_section_text": false,
+ "copy_only_section_data": false,
+ "copy_only_sections": [],
+ "other_flags": ""
+ },
+ "createList": {
+ "enabled": true,
+ "display_source": false,
+ "display_all_headers": true,
+ "demangle_names": true,
+ "display_debug_info": false,
+ "disassemble": true,
+ "display_file_headers": false,
+ "display_line_numbers": false,
+ "display_relocation_info": false,
+ "display_symbols": false,
+ "wide_lines": false,
+ "other_flags": ""
+ },
+ "printSize": {
+ "enabled": true,
+ "size_format": "berkeley",
+ "hex": false,
+ "show_totals": false,
+ "other_flags": ""
+ },
+ "riscvTargetProcessor": {
+ "architecture": "rv32i",
+ "multiply_extension": true,
+ "atomic_extension": true,
+ "floating_point": "none",
+ "compressed_extension": true,
+ "extra_compressed_extension": true,
+ "bit_extension": false,
+ "multiplication_subset_of_the_M_extension": false,
+ "integer_ABI": "ilp32",
+ "floating_point_ABI": "none",
+ "tuning": "default",
+ "code_model": "default",
+ "small_data_limit": 16,
+ "align": "default",
+ "save_restore": true,
+ "other_target_flags": ""
+ },
+ "component_toolchain": "${WCH:Toolchain:GCC12}",
+ "name": "obj",
+ "configVariables": []
+ }
+ ]
+ },
+ "flashConfig": {
+ "mcutype": "CH32V20x",
+ "address": "0x08000000",
+ "target_path": "obj/CoreMark.hex",
+ "clkSpeed": "High",
+ "debug_interface_mode": "1-wire serial",
+ "erase": true,
+ "program": true,
+ "verify": true,
+ "reset": true,
+ "sdiPrintf": false,
+ "disablepowerout": false,
+ "clearcodeflash": false,
+ "disablecodeprotect": false,
+ "exepath": "",
+ "exearguments": ""
+ },
+ "debugConfigurations": {
+ "openOCDCfg": {
+ "useLocalOpenOCD": true,
+ "executable": "${WCH:OpenOCD:default}",
+ "gdbport": 3333,
+ "telnetport": 4444,
+ "tclport": 6666,
+ "configOptions": [
+ "-f \"${WCH:OpenOCD:default}/bin/wch-riscv.cfg\""
+ ],
+ "host": "localhost",
+ "port": 3333,
+ "skipDownloadBeforeDebug": false,
+ "enablePageEraser": false,
+ "enableNoZeroWaitingAreaFlash": false
+ },
+ "gdbCfg": {
+ "executable": "${WCH:Toolchain:GCC12}",
+ "options": [],
+ "commands": [
+ "set mem inaccessible-by-default off",
+ "set architecture riscv:rv32",
+ "set remotetimeout unlimited",
+ "set disassembler-options xw"
+ ]
+ },
+ "startup": {
+ "initCommands": {
+ "initReset": true,
+ "initResetType": "init",
+ "additionalCommands": [],
+ "armSemihosting": false,
+ "armSemihosting_old": false
+ },
+ "loadedFiles": {
+ "loadSymbols": true,
+ "useProjBinaryForSymbols": true,
+ "useFileForSymbols": false,
+ "symbolFile": "",
+ "symbolFileOffset": "",
+ "loadImage": true,
+ "useProjBinaryForImage": true,
+ "useFileForImage": false,
+ "executableFile": "",
+ "executableFileOffset": ""
+ },
+ "runCommands": {
+ "runReset": true,
+ "runResetType": "halt",
+ "additionalCommands": [],
+ "setBreakAt": "handle_reset",
+ "continue": true,
+ "setBreak": true,
+ "setProgramCounter": false,
+ "setProgramCounterAddress": ""
+ },
+ "debugInRAM": false
+ },
+ "svdpath": "${WCH:SDK:default}/RISC-V/CH32V208/NoneOS/CH32V208xx.svd",
+ "output": {
+ "showDebugGDBTrace": true,
+ "saveDebugOutputToFile": false,
+ "showDebugOutputTimestamps": true
+ },
+ "reserve": {
+ "PROGRAM_NAME": "obj/CoreMark.elf",
+ "PROJECT_ATTR": "CoreMark",
+ "PROJECT_BUILD_CONFIG_AUTO_ATTR": true,
+ "PROJECT_BUILD_CONFIG_ID_ATTR": "",
+ "ATTR_BUILD_BEFORE_LAUNCH_ATTR": 2,
+ "GdbServerAllocateConsole": true,
+ "GdbServerAllocateTelnetConsole": false,
+ "StartGdbCLient": true,
+ "UPDATE_THREADLIST_ON_SUSPEND": false
+ }
+ }
+}
\ No newline at end of file
diff --git a/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_conf.h b/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_conf.h
new file mode 100644
index 0000000..d1eeb38
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_conf.h
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v20x_conf.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+
+
+
diff --git a/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_it.c
new file mode 100644
index 0000000..e3dff91
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_it.c
@@ -0,0 +1,46 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v20x_it.c
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2023/12/29
+ * Description : Main Interrupt Service Routines.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn NMI_Handler
+ *
+ * @brief This function handles NMI exception.
+ *
+ * @return none
+ */
+void NMI_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+/*********************************************************************
+ * @fn HardFault_Handler
+ *
+ * @brief This function handles Hard Fault exception.
+ *
+ * @return none
+ */
+void HardFault_Handler(void)
+{
+ NVIC_SystemReset();
+ while (1)
+ {
+ }
+}
+
+
diff --git a/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_it.h b/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_it.h
new file mode 100644
index 0000000..f68b203
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/User/ch32v20x_it.h
@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : ch32v20x_it.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/EVT/EXAM/APPLICATION/CoreMark/User/main.c b/EVT/EXAM/APPLICATION/CoreMark/User/main.c
new file mode 100644
index 0000000..1d174e3
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/User/main.c
@@ -0,0 +1,466 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* File: core_main.c
+ This file contains the framework to acquire a block of memory, seed
+ initial parameters, tun t he benchmark and report the results.
+*/
+
+/* Note:
+ * a.If the actual application must require the use of the system with a frequency greater than 120M
+ * b.This routine under 168M锛12M_HSE锛 system conditions_only applied to CH32V20x_D6
+ * c.168M is only suitable for Commercial Grade Electronic applications: 0鈩 鈮 TA 鈮 70鈩 with good heat dissipation
+ */
+
+#include "coremark.h"
+
+/* Function: iterate
+ Run the benchmark for a specified number of iterations.
+
+ Operation:
+ For each type of benchmarked algorithm:
+ a - Initialize the data block for the algorithm.
+ b - Execute the algorithm N times.
+
+ Returns:
+ NULL.
+*/
+
+static ee_u16 list_known_crc[] = { (ee_u16)0xd4b0,
+ (ee_u16)0x3340,
+ (ee_u16)0x6a79,
+ (ee_u16)0xe714,
+ (ee_u16)0xe3c1 };
+static ee_u16 matrix_known_crc[] = { (ee_u16)0xbe52,
+ (ee_u16)0x1199,
+ (ee_u16)0x5608,
+ (ee_u16)0x1fd7,
+ (ee_u16)0x0747 };
+static ee_u16 state_known_crc[] = { (ee_u16)0x5e47,
+ (ee_u16)0x39bf,
+ (ee_u16)0xe5a4,
+ (ee_u16)0x8e3a,
+ (ee_u16)0x8d84 };
+void *
+iterate(void *pres)
+{
+ ee_u32 i;
+ ee_u16 crc;
+ core_results *res = (core_results *)pres;
+ ee_u32 iterations = res->iterations;
+ res->crc = 0;
+ res->crclist = 0;
+ res->crcmatrix = 0;
+ res->crcstate = 0;
+
+ for (i = 0; i < iterations; i++)
+ {
+ crc = core_bench_list(res, 1);
+ res->crc = crcu16(crc, res->crc);
+ crc = core_bench_list(res, -1);
+ res->crc = crcu16(crc, res->crc);
+ if (i == 0)
+ res->crclist = res->crc;
+ }
+ return NULL;
+}
+
+#if (SEED_METHOD == SEED_ARG)
+ee_s32 get_seed_args(int i, int argc, char *argv[]);
+#define get_seed(x) (ee_s16) get_seed_args(x, argc, argv)
+#define get_seed_32(x) get_seed_args(x, argc, argv)
+#else /* via function or volatile */
+ee_s32 get_seed_32(int i);
+#define get_seed(x) (ee_s16) get_seed_32(x)
+#endif
+
+#if (MEM_METHOD == MEM_STATIC)
+ee_u8 static_memblk[TOTAL_DATA_SIZE];
+#endif
+char *mem_name[3] = { "Static", "Heap", "Stack" };
+/* Function: main
+ Main entry routine for the benchmark.
+ This function is responsible for the following steps:
+
+ 1 - Initialize input seeds from a source that cannot be determined at
+ compile time. 2 - Initialize memory block for use. 3 - Run and time the
+ benchmark. 4 - Report results, testing the validity of the output if the
+ seeds are known.
+
+ Arguments:
+ 1 - first seed : Any value
+ 2 - second seed : Must be identical to first for iterations to be
+ identical 3 - third seed : Any value, should be at least an order of
+ magnitude less then the input size, but bigger then 32. 4 - Iterations :
+ Special, if set to 0, iterations will be automatically determined such that
+ the benchmark will run between 10 to 100 secs
+
+*/
+core_results results[MULTITHREAD];
+#if MAIN_HAS_NOARGC
+MAIN_RETURN_TYPE
+main(void)
+{
+ int argc = 0;
+ char *argv[1];
+#else
+
+MAIN_RETURN_TYPE
+main(int argc, char *argv[])
+{
+#endif
+
+ ee_u16 i, j = 0, num_algorithms = 0;
+
+ ee_s16 known_id = -1, total_errors = 0;
+ ee_u16 seedcrc = 0;
+ CORE_TICKS total_time;
+// core_results results[MULTITHREAD];
+
+ #if (MEM_METHOD == MEM_STACK)
+ ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD];
+ #endif
+
+ /* first call any initializations needed */
+ portable_init(&(results[0].port), &argc, argv);
+
+ /* First some checks to make sure benchmark will run ok */
+ if (sizeof(struct list_head_s) > 128)
+ {
+ ee_printf("list_head structure too big for comparable data!\n");
+ return MAIN_RETURN_VAL;
+ }
+ results[0].seed1 = get_seed(1);
+ results[0].seed2 = get_seed(2);
+ results[0].seed3 = get_seed(3);
+ results[0].iterations = get_seed_32(4);
+#if CORE_DEBUG
+ results[0].iterations = 1;
+#endif
+ results[0].execs = get_seed_32(5);
+ if (results[0].execs == 0)
+ { /* if not supplied, execute all algorithms */
+ results[0].execs = ALL_ALGORITHMS_MASK;
+ }
+ /* put in some default values based on one seed only for easy testing */
+ if ((results[0].seed1 == 0) && (results[0].seed2 == 0)
+ && (results[0].seed3 == 0))
+ { /* perfromance run */
+ results[0].seed1 = 0;
+ results[0].seed2 = 0;
+ results[0].seed3 = 0x66;
+ }
+ if ((results[0].seed1 == 1) && (results[0].seed2 == 0)
+ && (results[0].seed3 == 0))
+ { /* validation run */
+ results[0].seed1 = 0x3415;
+ results[0].seed2 = 0x3415;
+ results[0].seed3 = 0x66;
+ }
+#if (MEM_METHOD == MEM_STATIC)
+ results[0].memblock[0] = (void *)static_memblk;
+ results[0].size = TOTAL_DATA_SIZE;
+ results[0].err = 0;
+#if (MULTITHREAD > 1)
+#error "Cannot use a static data area with multiple contexts!"
+#endif
+#elif (MEM_METHOD == MEM_MALLOC)
+ for (i = 0; i < MULTITHREAD; i++)
+ {
+ ee_s32 malloc_override = get_seed(7);
+ if (malloc_override != 0)
+ results[i].size = malloc_override;
+ else
+ results[i].size = TOTAL_DATA_SIZE;
+ results[i].memblock[0] = portable_malloc(results[i].size);
+ results[i].seed1 = results[0].seed1;
+ results[i].seed2 = results[0].seed2;
+ results[i].seed3 = results[0].seed3;
+ results[i].err = 0;
+ results[i].execs = results[0].execs;
+ }
+#elif (MEM_METHOD == MEM_STACK)
+for (i = 0; i < MULTITHREAD; i++)
+{
+ results[i].memblock[0] = stack_memblock + i * TOTAL_DATA_SIZE;
+ results[i].size = TOTAL_DATA_SIZE;
+ results[i].seed1 = results[0].seed1;
+ results[i].seed2 = results[0].seed2;
+ results[i].seed3 = results[0].seed3;
+ results[i].err = 0;
+ results[i].execs = results[0].execs;
+}
+#else
+#error "Please define a way to initialize a memory block."
+#endif
+ /* Data init */
+ /* Find out how space much we have based on number of algorithms */
+ for (i = 0; i < NUM_ALGORITHMS; i++)
+ {
+ if ((1 << (ee_u32)i) & results[0].execs)
+ num_algorithms++;
+ }
+ for (i = 0; i < MULTITHREAD; i++)
+ results[i].size = results[i].size / num_algorithms;
+ /* Assign pointers */
+ for (i = 0; i < NUM_ALGORITHMS; i++)
+ {
+ ee_u32 ctx;
+ if ((1 << (ee_u32)i) & results[0].execs)
+ {
+ for (ctx = 0; ctx < MULTITHREAD; ctx++)
+ results[ctx].memblock[i + 1]
+ = (char *)(results[ctx].memblock[0]) + results[0].size * j;
+ j++;
+ }
+ }
+ /* call inits */
+ for (i = 0; i < MULTITHREAD; i++)
+ {
+ if (results[i].execs & ID_LIST)
+ {
+ results[i].list = core_list_init(
+ results[0].size, results[i].memblock[1], results[i].seed1);
+ }
+ if (results[i].execs & ID_MATRIX)
+ {
+ core_init_matrix(results[0].size,
+ results[i].memblock[2],
+ (ee_s32)results[i].seed1
+ | (((ee_s32)results[i].seed2) << 16),
+ &(results[i].mat));
+ }
+ if (results[i].execs & ID_STATE)
+ {
+ core_init_state(
+ results[0].size, results[i].seed1, results[i].memblock[3]);
+ }
+ }
+
+ /* automatically determine number of iterations if not set */
+ if (results[0].iterations == 0)
+ {
+ secs_ret secs_passed = 0;
+ ee_u32 divisor;
+ results[0].iterations = 1;
+ while (secs_passed < (secs_ret)1)
+ {
+ results[0].iterations *= 10;
+ start_time();
+ iterate(&results[0]);
+ stop_time();
+ secs_passed = time_in_secs(get_time());
+ }
+ /* now we know it executes for at least 1 sec, set actual run time at
+ * about 10 secs */
+ divisor = (ee_u32)secs_passed;
+ if (divisor == 0) /* some machines cast float to int as 0 since this
+ conversion is not defined by ANSI, but we know at
+ least one second passed */
+ divisor = 1;
+ results[0].iterations *= 1 + 10 / divisor;
+ }
+ /* perform actual benchmark */
+ start_time();
+#if (MULTITHREAD > 1)
+ if (default_num_contexts > MULTITHREAD)
+ {
+ default_num_contexts = MULTITHREAD;
+ }
+ for (i = 0; i < default_num_contexts; i++)
+ {
+ results[i].iterations = results[0].iterations;
+ results[i].execs = results[0].execs;
+ core_start_parallel(&results[i]);
+ }
+ for (i = 0; i < default_num_contexts; i++)
+ {
+ core_stop_parallel(&results[i]);
+ }
+#else
+ iterate(&results[0]);
+#endif
+ stop_time();
+ total_time = get_time();
+ /* get a function of the input to report */
+ seedcrc = crc16(results[0].seed1, seedcrc);
+ seedcrc = crc16(results[0].seed2, seedcrc);
+ seedcrc = crc16(results[0].seed3, seedcrc);
+ seedcrc = crc16(results[0].size, seedcrc);
+
+ switch (seedcrc)
+ { /* test known output for common seeds */
+ case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */
+ known_id = 0;
+ ee_printf("6k performance run parameters for coremark.\n");
+ break;
+ case 0x7b05: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per
+ algorithm */
+ known_id = 1;
+ ee_printf("6k validation run parameters for coremark.\n");
+ break;
+ case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm
+ */
+ known_id = 2;
+ ee_printf("Profile generation run parameters for coremark.\n");
+ break;
+ case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */
+ known_id = 3;
+ ee_printf("2K performance run parameters for coremark.\n");
+ break;
+ case 0x18f2: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per
+ algorithm */
+ known_id = 4;
+ ee_printf("2K validation run parameters for coremark.\n");
+ break;
+ default:
+ total_errors = -1;
+ break;
+ }
+ if (known_id >= 0)
+ {
+ for (i = 0; i < default_num_contexts; i++)
+ {
+ results[i].err = 0;
+ if ((results[i].execs & ID_LIST)
+ && (results[i].crclist != list_known_crc[known_id]))
+ {
+ ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n",
+ i,
+ results[i].crclist,
+ list_known_crc[known_id]);
+ results[i].err++;
+ }
+ if ((results[i].execs & ID_MATRIX)
+ && (results[i].crcmatrix != matrix_known_crc[known_id]))
+ {
+ ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n",
+ i,
+ results[i].crcmatrix,
+ matrix_known_crc[known_id]);
+ results[i].err++;
+ }
+ if ((results[i].execs & ID_STATE)
+ && (results[i].crcstate != state_known_crc[known_id]))
+ {
+ ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n",
+ i,
+ results[i].crcstate,
+ state_known_crc[known_id]);
+ results[i].err++;
+ }
+ total_errors += results[i].err;
+ }
+ }
+ total_errors += check_data_types();
+ /* and report results */
+ ee_printf("CoreMark Size : %lu\n", (long unsigned)results[0].size);
+ ee_printf("Total ticks : %lu\n", (long unsigned)total_time);
+#if HAS_FLOAT
+ ee_printf("Total time (secs): %f\n", time_in_secs(total_time));
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %f\n",
+ default_num_contexts * results[0].iterations
+ / time_in_secs(total_time));
+#else
+ ee_printf("Total time (secs): %d\n", time_in_secs(total_time));
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %d\n",
+ default_num_contexts * results[0].iterations
+ / time_in_secs(total_time));
+#endif
+ if (time_in_secs(total_time) < 10)
+ {
+ ee_printf(
+ "ERROR! Must execute for at least 10 secs for a valid result!\n");
+ total_errors++;
+ }
+
+ ee_printf("Iterations : %lu\n",
+ (long unsigned)default_num_contexts * results[0].iterations);
+ ee_printf("Compiler version : %s\n", COMPILER_VERSION);
+ ee_printf("Compiler flags : %s\n", COMPILER_FLAGS);
+#if (MULTITHREAD > 1)
+ ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts);
+#endif
+
+/* changed by TempersLee */
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+ ee_printf("Memory location : %s\n", MEM_LOCATION);
+#else
+ ee_printf("Memory location : %s\n", mem_name[MEM_METHOD]);
+#endif
+ /* output for verification */
+ ee_printf("seedcrc : 0x%04x\n", seedcrc);
+ if (results[0].execs & ID_LIST)
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crclist : 0x%04x\n", i, results[i].crclist);
+ if (results[0].execs & ID_MATRIX)
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crcmatrix : 0x%04x\n", i, results[i].crcmatrix);
+ if (results[0].execs & ID_STATE)
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crcstate : 0x%04x\n", i, results[i].crcstate);
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crcfinal : 0x%04x\n", i, results[i].crc);
+ if (total_errors == 0)
+ {
+ ee_printf(
+ "Correct operation validated. See README.md for run and reporting "
+ "rules.\n");
+#if HAS_FLOAT
+ if (known_id == 3)
+ {
+ ee_printf("CoreMark 1.0 : %f / %s %s",
+ default_num_contexts * results[0].iterations
+ / time_in_secs(total_time),
+ COMPILER_VERSION,
+ COMPILER_FLAGS);
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+ ee_printf(" / %s", MEM_LOCATION);
+#else
+ ee_printf(" / %s", mem_name[MEM_METHOD]);
+#endif
+
+#if (MULTITHREAD > 1)
+ ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD);
+#endif
+ ee_printf("\n");
+ ee_printf("If working at 1MHz,CoreMark 1.0 : %f/MHz\n",default_num_contexts * results[0].iterations
+ / time_in_secs(total_time)/(SystemCoreClock/1000000));
+
+ }
+#endif
+ }
+ if (total_errors > 0)
+ ee_printf("Errors detected\n");
+ if (total_errors < 0)
+ ee_printf(
+ "Cannot validate operation for these seed values, please compare "
+ "with results on a known platform.\n");
+
+#if (MEM_METHOD == MEM_MALLOC)
+ for (i = 0; i < MULTITHREAD; i++)
+ portable_free(results[i].memblock[0]);
+#endif
+ /* And last call any target specific code for finalizing */
+ portable_fini(&(results[0].port));
+
+ while(1);
+// return MAIN_RETURN_VAL;
+}
diff --git a/EVT/EXAM/APPLICATION/CoreMark/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/CoreMark/User/system_ch32v20x.c
new file mode 100644
index 0000000..496b40d
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/User/system_ch32v20x.c
@@ -0,0 +1,367 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : system_ch32v20x.c
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : CH32V20x Device Peripheral Access Layer System Source File.
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
+ * For HSE = 8Mhz (CH32V20x_D6)
+ * For HSE = 12Mhz (CH32V20x_D6 for 168M)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+
+/*168M Only suitable for commercial-grade applications,The crystal oscillator selecte 12M
+ *-10 < temperature < 70 and good heat dissipation
+ *168M(12M_HSE) system conditions_only applied to CH32V20x_D6*/
+
+ #if defined(HSE_VALUE_12M) && defined(CH32V20x_D6)
+#define SYSCLK_FREQ_168MHz_HSE 168000000
+#endif
+
+#ifndef HSE_VALUE_12M
+
+#define SYSCLK_FREQ_144MHz_HSE 144000000
+// #define SYSCLK_FREQ_144MHz_HSI 144000000
+
+#endif
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_168MHz_HSE
+uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz_HSE; /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+#elif defined SYSCLK_FREQ_168MHz_HSE
+static void SetSysClockTo168_HSE( void );
+
+#endif
+
+/*********************************************************************
+ * @fn SystemInit
+ *
+ * @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
+ * the PLL and update the SystemCoreClock variable.
+ *
+ * @return none
+ */
+void SystemInit (void)
+{
+ RCC->CTLR |= (uint32_t)0x00000001;
+ RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+ RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+ RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+ RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
+ RCC->INTR = 0x009F0000;
+ SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn SystemCoreClockUpdate
+ *
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return none
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+ tmp = RCC->CFGR0 & RCC_SWS;
+
+ switch (tmp)
+ {
+ case 0x00:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04:
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08:
+ pllmull = RCC->CFGR0 & RCC_PLLMULL;
+ pllsource = RCC->CFGR0 & RCC_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if(pllmull == 17) pllmull = 18;
+
+ if (pllsource == 0x00)
+ {
+ if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+ SystemCoreClock = HSI_VALUE * pllmull;
+ }
+ else{
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ }
+ else
+ {
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+ if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
+ {
+ SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+ }
+ else
+#endif
+ if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+ {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+ SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+ }
+ else
+ {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+ SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+ SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+ }
+ }
+
+ if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+ SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn SetSysClock
+ *
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClock(void)
+{
+ //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_144MHz_HSE
+ SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+ SetSysClockTo144_HSI();
+#elif defined SYSCLK_FREQ_168MHz_HSE
+ SetSysClockTo168_HSE();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ * source (default after reset)
+ */
+}
+
+
+#ifdef SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo144_HSE
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+ * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+ * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+ */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_168MHz_HSE
+
+/*********************************************************************
+ * @fn SetSysClockTo168_HSE
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ * 168M(12M_HSE) system conditions_only applied to CH32V20x_D6
+ * @return none
+ */
+static void SetSysClockTo168_HSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CTLR & RCC_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CTLR & RCC_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+ RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL14);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ {
+ /*
+ * If HSE fails to start-up, the application will have wrong clock
+ * configuration. User can add here some code to deal with this error
+ */
+ }
+}
+
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn SetSysClockTo144_HSI
+ *
+ * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ /* PCLK2 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ /* PCLK1 = HCLK */
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+ /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0)
+ {
+ }
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+ {
+ }
+}
+
+
+#endif
diff --git a/EVT/EXAM/APPLICATION/CoreMark/User/system_ch32v20x.h b/EVT/EXAM/APPLICATION/CoreMark/User/system_ch32v20x.h
new file mode 100644
index 0000000..9c8a3f7
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/User/system_ch32v20x.h
@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name : system_ch32v20x.h
+ * Author : WCH
+ * Version : V1.0.0
+ * Date : 2021/06/06
+ * Description : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/LICENSE.md b/EVT/EXAM/APPLICATION/CoreMark/coremark/LICENSE.md
new file mode 100644
index 0000000..14e53e9
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/LICENSE.md
@@ -0,0 +1,100 @@
+# COREMARK庐 ACCEPTABLE USE AGREEMENT
+
+This ACCEPTABLE USE AGREEMENT (this 鈥淎greement鈥) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (鈥淟icensor鈥), to users of its CoreMark庐 software (鈥淟icensee鈥) exclusively on the following terms.
+
+Licensor offers benchmarking software (鈥淪oftware鈥) pursuant to an open source license, but carefully controls use of its benchmarks and their associated goodwill. Licensor has registered its trademark in one of the benchmarks available through the Software, COREMARK, Ser. No. 85/487,290; Reg. No. 4,179,307 (the 鈥淭rademark鈥), and promotes the use of a standard metric as a benchmark for assessing the performance of embedded systems. Solely on the terms described herein, Licensee may use and display the Trademark in connection with the generation of data regarding measurement and analysis of computer and embedded system benchmarking via the Software (the 鈥淟icensed Use鈥).
+
+## Article 1 鈥 License Grant.
+1.1. License. Subject to the terms and conditions of this Agreement, Licensor hereby grants to Licensee, and Licensee hereby accepts from Licensor, a personal, non-exclusive, royalty-free, revocable right and license to use and display the Trademark during the term of this Agreement (the 鈥淭erm鈥), solely and exclusively in connection with the Licensed Use. During the Term, Licensee (i) shall not modify or otherwise create derivative works of the Trademark, and (ii) may use the Trademark only to the extent permitted under this License. Neither Licensee nor any affiliate or agent thereof shall otherwise use the Trademark without the prior express written consent of Licensor, which may be withheld in its sole and absolute discretion. All rights not expressly granted to Licensee hereunder shall remain the exclusive property of Licensor.
+
+1.2. Modifications to the Software. Licensee shall not use the Trademark in connection with any use of a modified, derivative, or otherwise altered copy of the Software.
+
+1.3. Licensor鈥檚 Use. Nothing in this Agreement shall preclude Licensor or any of its successors or assigns from using or permitting other entities to use the Trademark, whether or not such entity directly or indirectly competes or conflicts with Licensee鈥檚 Licensed Use in any manner.
+
+1.4. Term and Termination. This Agreement is perpetual unless terminated by either of the parties. Licensee may terminate this Agreement for convenience, without cause or liability, for any reason or for no reason whatsoever, upon ten (10) business days written notice. Licensor may terminate this Agreement effective immediately upon notice of breach. Upon termination, Licensee shall immediately remove all implementations of the Trademark from the Licensed Use, and delete all digitals files and records of all materials related to the Trademark.
+
+## Article 2 鈥 Ownership.
+2.1. Ownership. Licensee acknowledges and agrees that Licensor is the owner of all right, title, and interest in and to the Trademark, and all such right, title, and interest shall remain with Licensor. Licensee shall not contest, dispute, challenge, oppose, or seek to cancel Licensor鈥檚 right, title, and interest in and to the Trademark. Licensee shall not prosecute any application for registration of the Trademark. Licensee shall display appropriate notices regarding ownership of the Trademark in connection with the Licensed Use.
+
+2.2. Goodwill. Licensee acknowledges that Licensee shall not acquire any right, title, or interest in the Trademark by virtue of this Agreement other than the license granted hereunder, and disclaims any such right, title, interest, or ownership. All goodwill and reputation generated by Licensee鈥檚 use of the Trademark shall inure to the exclusive benefit of Licensor. Licensee shall not by any act or omission use the Trademark in any manner that disparages or reflects adversely on Licensor or its Licensed Use or reputation. Licensee shall not take any action that would interfere with or prejudice Licensor鈥檚 ownership or registration of the Trademark, the validity of the Trademark or the validity of the license granted by this Agreement. If Licensor determines and notifies Licensee that any act taken in connection with the Licensed Use (i) is inaccurate, unlawful or offensive to good taste; (ii) fails to provide for proper trademark notices, or (iii) otherwise violates Licensee鈥檚 obligations under this Agreement, the license granted under this Agreement shall terminate.
+
+## Article 3 鈥 Indemnification.
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+
+# Apache License
+
+Version 2.0, January 2004
+
+http://www.apache.org/licenses/
+
+## TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/README.md b/EVT/EXAM/APPLICATION/CoreMark/coremark/README.md
new file mode 100644
index 0000000..16b54b7
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/README.md
@@ -0,0 +1,398 @@
+
+# Introduction
+
+CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features. For more information about EEMBC's comprehensive embedded benchmark suites, please see www.eembc.org.
+
+For a more compute-intensive version of CoreMark that uses larger datasets and execution loops taken from common applications, please check out EEMBC's [CoreMark-PRO](https://www.github.com/eembc/coremark-pro) benchmark, also on GitHub.
+
+# Building and Running
+
+To build and run the benchmark, type
+
+`> make`
+
+Full results are available in the files `run1.log` and `run2.log`. CoreMark result can be found in `run1.log`.
+
+## Cross Compiling
+
+For cross compile platforms please adjust `core_portme.mak`, `core_portme.h` (and possibly `core_portme.c`) according to the specific platform used. When porting to a new platform, it is recommended to copy one of the default port folders (e.g. `mkdir && cp linux/* `), adjust the porting files, and run:
+~~~
+% make PORT_DIR=
+~~~
+
+## Make Targets
+`run` - Default target, creates `run1.log` and `run2.log`.
+`run1.log` - Run the benchmark with performance parameters, and output to `run1.log`
+`run2.log` - Run the benchmark with validation parameters, and output to `run2.log`
+`run3.log` - Run the benchmark with profile generation parameters, and output to `run3.log`
+`compile` - compile the benchmark executable
+`link` - link the benchmark executable
+`check` - test MD5 of sources that may not be modified
+`clean` - clean temporary files
+
+### Make flag: `ITERATIONS`
+By default, the benchmark will run between 10-100 seconds. To override, use `ITERATIONS=N`
+~~~
+% make ITERATIONS=10
+~~~
+Will run the benchmark for 10 iterations. It is recommended to set a specific number of iterations in certain situations e.g.:
+
+* Running with a simulator
+* Measuring power/energy
+* Timing cannot be restarted
+
+Minimum required run time: **Results are only valid for reporting if the benchmark ran for at least 10 secs!**
+
+### Make flag: `XCFLAGS`
+To add compiler flags from the command line, use `XCFLAGS` e.g.:
+
+~~~
+% make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1"
+~~~
+
+### Make flag: `CORE_DEBUG`
+
+Define to compile for a debug run if you get incorrect CRC.
+
+~~~
+% make XCFLAGS="-DCORE_DEBUG=1"
+~~~
+
+### Make flag: `REBUILD`
+
+Force a rebuild of the executable.
+
+## Systems Without `make`
+The following files need to be compiled:
+* `core_list_join.c`
+* `core_main.c`
+* `core_matrix.c`
+* `core_state.c`
+* `core_util.c`
+* `PORT_DIR/core_portme.c`
+
+For example:
+~~~
+% gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000
+% ./coremark.exe > run1.log
+~~~
+The above will compile the benchmark for a performance run and 1000 iterations. Output is redirected to `run1.log`.
+
+# Parallel Execution
+Use `XCFLAGS=-DMULTITHREAD=N` where N is number of threads to run in parallel. Several implementations are available to execute in multiple contexts, or you can implement your own in `core_portme.c`.
+
+~~~
+% make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD"
+~~~
+
+The above will compile the benchmark for execution on 4 cores, using POSIX Threads API.
+
+Note: linking may fail on the previous command if your linker does not automatically add the `pthread` library. If you encounter `undefined reference` errors, please modify the `core_portme.mak` file for your platform, (e.g. `linux/core_portme.mak`) and add `-lpthread` to the `LFLAGS_END` parameter.
+
+# Run Parameters for the Benchmark Executable
+CoreMark's executable takes several parameters as follows (but only if `main()` accepts arguments):
+1st - A seed value used for initialization of data.
+2nd - A seed value used for initialization of data.
+3rd - A seed value used for initialization of data.
+4th - Number of iterations (0 for auto : default value)
+5th - Reserved for internal use.
+6th - Reserved for internal use.
+7th - For malloc users only, ovreride the size of the input data buffer.
+
+The run target from make will run coremark with 2 different data initialization seeds.
+
+## Alternative parameters:
+If not using `malloc` or command line arguments are not supported, the buffer size
+for the algorithms must be defined via the compiler define `TOTAL_DATA_SIZE`.
+`TOTAL_DATA_SIZE` must be set to 2000 bytes (default) for standard runs.
+The default for such a target when testing different configurations could be:
+
+~~~
+% make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1"
+~~~
+
+# Submitting Results
+
+CoreMark results can be submitted on the web. Open a web browser and go to the [submission page](https://www.eembc.org/coremark/submit.php). After registering an account you may enter a score.
+
+# Run Rules
+What is and is not allowed.
+
+## Required
+1. The benchmark needs to run for at least 10 seconds.
+2. All validation must succeed for seeds `0,0,0x66` and `0x3415,0x3415,0x66`, buffer size of 2000 bytes total.
+ * If not using command line arguments to main:
+~~~
+ % make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log
+ % make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log
+~~~
+3. If using profile guided optimization, profile must be generated using seeds of `8,8,8`, and buffer size of 1200 bytes total.
+~~~
+ % make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log
+~~~
+4. All source files must be compiled with the same flags.
+5. All data type sizes must match size in bits such that:
+ * `ee_u8` is an unsigned 8-bit datatype.
+ * `ee_s16` is a signed 16-bit datatype.
+ * `ee_u16` is an unsigned 16-bit datatype.
+ * `ee_s32` is a signed 32-bit datatype.
+ * `ee_u32` is an unsigned 32-bit datatype.
+
+## Allowed
+
+1. Changing number of iterations
+2. Changing toolchain and build/load/run options
+3. Changing method of acquiring a data memory block
+5. Changing the method of acquiring seed values
+6. Changing implementation `in core_portme.c`
+7. Changing configuration values in `core_portme.h`
+8. Changing `core_portme.mak`
+
+## NOT ALLOWED
+1. Changing of source file other then `core_portme*` (use `make check` to validate)
+
+# Reporting rules
+Use the following syntax to report results on a data sheet:
+
+CoreMark 1.0 : N / C [/ P] [/ M]
+
+N - Number of iterations per second with seeds 0,0,0x66,size=2000)
+
+C - Compiler version and flags
+
+P - Parameters such as data and code allocation specifics
+
+* This parameter *may* be omitted if all data was allocated on the heap in RAM.
+* This parameter *may not* be omitted when reporting CoreMark/MHz
+
+M - Type of parallel execution (if used) and number of contexts
+* This parameter may be omitted if parallel execution was not used.
+
+e.g.:
+
+~~~
+CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2
+~~~
+or
+~~~
+CoreMark 1.0 : 1400 / GCC 3.4 -O4
+~~~
+
+If reporting scaling results, the results must be reported as follows:
+
+CoreMark/MHz 1.0 : N / C / P [/ M]
+
+P - When reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio.
+1. If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included.
+
+e.g.:
+
+~~~
+CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache
+~~~
+
+# Log File Format
+The log files have the following format
+
+~~~
+2K performance run parameters for coremark. (Run type)
+CoreMark Size : 666 (Buffer size)
+Total ticks : 25875 (platform dependent value)
+Total time (secs) : 25.875000 (actual time in seconds)
+Iterations/Sec : 3864.734300 (Performance value to report)
+Iterations : 100000 (number of iterations used)
+Compiler version : GCC3.4.4 (Compiler and version)
+Compiler flags : -O2 (Compiler and linker flags)
+Memory location : Code in flash, data in on chip RAM
+seedcrc : 0xe9f5 (identifier for the input seeds)
+[0]crclist : 0xe714 (validation for list part)
+[0]crcmatrix : 0x1fd7 (validation for matrix part)
+[0]crcstate : 0x8e3a (validation for state part)
+[0]crcfinal : 0x33ff (iteration dependent output)
+Correct operation validated. See README.md for run and reporting rules. (*Only when run is successful*)
+CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap (*Only on a successful performance run*)
+~~~
+
+# Theory of Operation
+
+This section describes the initial goals of CoreMark and their implementation.
+
+## Small and easy to understand
+
+* X number of source code lines for timed portion of the benchmark.
+* Meaningful names for variables and functions.
+* Comments for each block of code more than 10 lines long.
+
+## Portability
+
+A thin abstraction layer will be provided for I/O and timing in a separate file. All I/O and timing of the benchmark will be done through this layer.
+
+### Code / data size
+
+* Compile with gcc on x86 and make sure all sizes are according to requirements.
+* If dynamic memory allocation is used, take total memory allocated into account as well.
+* Avoid recursive functions and keep track of stack usage.
+* Use the same memory block as data site for all algorithms, and initialize the data before each algorithm 鈥 while this means that initialization with data happens during the timed portion, it will only happen once during the timed portion and so have negligible effect on the results.
+
+## Controlled output
+
+This may be the most difficult goal. Compilers are constantly improving and getting better at analyzing code. To create work that cannot be computed at compile time and must be computed at run time, we will rely on two assumptions:
+
+* Some system functions (e.g. time, scanf) and parameters cannot be computed at compile time. In most cases, marking a variable volatile means the compiler is force to read this variable every time it is read. This will be used to introduce a factor into the input that cannot be precomputed at compile time. Since the results are input dependent, that will make sure that computation has to happen at run time.
+
+* Either a system function or I/O (e.g. scanf) or command line parameters or volatile variables will be used before the timed portion to generate data which is not available at compile time. Specific method used is not relevant as long as it can be controlled, and that it cannot be computed or eliminated by the compiler at compile time. E.g. if the clock() functions is a compiler stub, it may not be used. The derived values will be reported on the output so that verification can be done on a different machine.
+
+* We cannot rely on command line parameters since some embedded systems do not have the capability to provide command line parameters. All 3 methods above will be implemented (time based, scanf and command line parameters) and all 3 are valid if the compiler cannot determine the value at compile time.
+
+* It is important to note that The actual values that are to be supplied at run time will be standardized. The methodology is not intended to provide random data, but simply to provide controlled data that cannot be precomputed at compile time.
+
+* Printed results must be valid at run time. This will be used to make sure the computation has been executed.
+
+* Some embedded systems do not provide 鈥減rintf鈥 or other I/O functionality. All I/O will be done through a thin abstraction interface to allow execution on such systems (e.g. allow output via JTAG).
+
+## Key Algorithms
+
+### Linked List
+
+The following linked list structure will be used:
+
+~~~
+typedef struct list_data_s {
+ ee_s16 data16;
+ ee_s16 idx;
+} list_data;
+
+typedef struct list_head_s {
+ struct list_head_s *next;
+ struct list_data_s *info;
+} list_head;
+~~~
+
+While adding a level of indirection accessing the data, this structure is realistic and used in many embedded applications for small to medium lists.
+
+The list itself will be initialized on a block of memory that will be passed in to the initialization function. While in general linked lists use malloc for new nodes, embedded applications sometime control the memory for small data structures such as arrays and lists directly to avoid the overhead of system calls, so this approach is realistic.
+
+The linked list will be initialized such that 1/4 of the list pointers point to sequential areas in memory, and 3/4 of the list pointers are distributed in a non sequential manner. This is done to emulate a linked list that had add/remove happen for a while disrupting the neat order, and then a series of adds that are likely to come from sequential memory locations.
+
+For the benchmark itself:
+- Multiple find operations are going to be performed. These find operations may result in the whole list being traversed. The result of each find will become part of the output chain.
+- The list will be sorted using merge sort based on the data16 value, and then derive CRC of the data16 item in order for part of the list. The CRC will become part of the output chain.
+- The list will be sorted again using merge sort based on the idx value. This sort will guarantee that the list is returned to the primary state before leaving the function, so that multiple iterations of the function will have the same result. CRC of the data16 for part of the list will again be calculated and become part of the output chain.
+
+The actual `data16` in each cell will be pseudo random based on a single 16b input that cannot be determined at compile time. In addition, the part of the list which is used for CRC will also be passed to the function, and determined based on an input that cannot be determined at run time.
+
+### Matrix Multiply
+
+This very simple algorithm forms the basis of many more complex algorithms. The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing.
+
+The total available data space will be divided to 3 parts:
+1. NxN matrix A.
+2. NxN matrix B.
+3. NxN matrix C.
+
+E.g. for 2K we will have 3 12x12 matrices (assuming data type of 32b 12(len)*12(wid)*4(size)*3(num) =1728 bytes).
+
+Matrix A will be initialized with small values (upper 3/4 of the bits all zero).
+Matrix B will be initialized with medium values (upper half of the bits all zero).
+Matrix C will be used for the result.
+
+For the benchmark itself:
+- Multiple A by a constant into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain.
+- Multiple A by column X of B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain.
+- Multiple A by B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain.
+
+The actual values for A and B must be derived based on input that is not available at compile time.
+
+### State Machine
+
+This part of the code needs to exercise switch and if statements. As such, we will use a small Moore state machine. In particular, this will be a state machine that identifies string input as numbers and divides them according to format.
+
+The state machine will parse the input string until either a 鈥,鈥 separator or end of input is encountered. An invalid number will cause the state machine to return invalid state and a valid number will cause the state machine to return with type of number format (int/float/scientific).
+
+This code will perform a realistic task, be small enough to easily understand, and exercise the required functionality. The other option used in embedded systems is a mealy based state machine, which is driven by a table. The table then determines the number of states and complexity of transitions. This approach, however, tests mainly the load/store and function call mechanisms and less the handling of branches. If analysis of the final results shows that the load/store functionality of the processor is not exercised thoroughly, it may be a good addition to the benchmark (codesize allowing).
+
+For input, the memory block will be initialized with comma separated values of mixed formats, as well as invalid inputs.
+
+For the benchmark itself:
+- Invoke the state machine on all of the input and count final states and state transitions. CRC of all final states and transitions will become part of the output chain.
+- Modify the input at intervals (inject errors) and repeat the state machine operation.
+- Modify the input back to original form.
+
+The actual input must be initialized based on data that cannot be determined at compile time. In addition the intervals for modification of the input and the actual modification must be based on input that cannot be determined at compile time.
+
+# Validation
+
+This release was tested on the following platforms:
+* x86 cygwin and gcc 3.4 (Quad, dual and single core systems)
+* x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems)
+* MIPS64 BE linux and gcc 3.4 16 cores system
+* MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system
+* PPC simulator with gcc 4.2.2 (No OS)
+* PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system)
+* BF533 with VDSP50
+* Renesas R8C/H8 MCU with HEW 4.05
+* NXP LPC1700 armcc v4.0.0.524
+* NEC 78K with IAR v4.61
+* ARM simulator with armcc v4
+
+# Memory Analysis
+
+Valgrind 3.4.0 used and no errors reported.
+
+# Balance Analysis
+
+Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0.
+
+# Statistics
+
+Lines:
+~~~
+Lines Blank Cmnts Source AESL
+===== ===== ===== ===== ========== =======================================
+ 469 66 170 251 627.5 core_list_join.c (C)
+ 330 18 54 268 670.0 core_main.c (C)
+ 256 32 80 146 365.0 core_matrix.c (C)
+ 240 16 51 186 465.0 core_state.c (C)
+ 165 11 20 134 335.0 core_util.c (C)
+ 150 23 36 98 245.0 coremark.h (C)
+ 1610 166 411 1083 2707.5 ----- Benchmark ----- (6 files)
+ 293 15 74 212 530.0 linux/core_portme.c (C)
+ 235 30 104 104 260.0 linux/core_portme.h (C)
+ 528 45 178 316 790.0 ----- Porting ----- (2 files)
+
+* For comparison, here are the stats for Dhrystone
+Lines Blank Cmnts Source AESL
+===== ===== ===== ===== ========== =======================================
+ 311 15 242 54 135.0 dhry.h (C)
+ 789 132 119 553 1382.5 dhry_1.c (C)
+ 186 26 68 107 267.5 dhry_2.c (C)
+ 1286 173 429 714 1785.0 ----- C ----- (3 files)
+~~~
+
+# Credits
+Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name; note that company names may no longer be accurate as this was written in 2009).
+* Alan Anderson, ADI
+* Adhikary Rajiv, ADI
+* Elena Stohr, ARM
+* Ian Rickards, ARM
+* Andrew Pickard, ARM
+* Trent Parker, CAVIUM
+* Shay Gal-On, EEMBC
+* Markus Levy, EEMBC
+* Peter Torelli, EEMBC
+* Ron Olson, IBM
+* Eyal Barzilay, MIPS
+* Jens Eltze, NEC
+* Hirohiko Ono, NEC
+* Ulrich Drees, NEC
+* Frank Roscheda, NEC
+* Rob Cosaro, NXP
+* Shumpei Kawasaki, RENESAS
+
+# Legal
+Please refer to LICENSE.md in this reposity for a description of your rights to use this code.
+
+# Copyright
+Copyright 漏 2009 EEMBC All rights reserved.
+CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
+
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/core_list_join.c b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_list_join.c
new file mode 100644
index 0000000..d9c256d
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_list_join.c
@@ -0,0 +1,595 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/*
+Topic: Description
+ Benchmark using a linked list.
+
+ Linked list is a common data structure used in many applications.
+
+ For our purposes, this will excercise the memory units of the processor.
+ In particular, usage of the list pointers to find and alter data.
+
+ We are not using Malloc since some platforms do not support this
+library.
+
+ Instead, the memory block being passed in is used to create a list,
+ and the benchmark takes care not to add more items then can be
+ accomodated by the memory block. The porting layer will make sure
+ that we have a valid memory block.
+
+ All operations are done in place, without using any extra memory.
+
+ The list itself contains list pointers and pointers to data items.
+ Data items contain the following:
+
+ idx - An index that captures the initial order of the list.
+ data - Variable data initialized based on the input parameters. The 16b
+are divided as follows: o Upper 8b are backup of original data. o Bit 7
+indicates if the lower 7 bits are to be used as is or calculated. o Bits 0-2
+indicate type of operation to perform to get a 7b value. o Bits 3-6 provide
+input for the operation.
+
+*/
+
+/* local functions */
+
+list_head *core_list_find(list_head *list, list_data *info);
+list_head *core_list_reverse(list_head *list);
+list_head *core_list_remove(list_head *item);
+list_head *core_list_undo_remove(list_head *item_removed,
+ list_head *item_modified);
+list_head *core_list_insert_new(list_head * insert_point,
+ list_data * info,
+ list_head **memblock,
+ list_data **datablock,
+ list_head * memblock_end,
+ list_data * datablock_end);
+typedef ee_s32 (*list_cmp)(list_data *a, list_data *b, core_results *res);
+list_head *core_list_mergesort(list_head * list,
+ list_cmp cmp,
+ core_results *res);
+
+ee_s16
+calc_func(ee_s16 *pdata, core_results *res)
+{
+ ee_s16 data = *pdata;
+ ee_s16 retval;
+ ee_u8 optype
+ = (data >> 7)
+ & 1; /* bit 7 indicates if the function result has been cached */
+ if (optype) /* if cached, use cache */
+ return (data & 0x007f);
+ else
+ { /* otherwise calculate and cache the result */
+ ee_s16 flag = data & 0x7; /* bits 0-2 is type of function to perform */
+ ee_s16 dtype
+ = ((data >> 3)
+ & 0xf); /* bits 3-6 is specific data for the operation */
+ dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */
+ switch (flag)
+ {
+ case 0:
+ if (dtype < 0x22) /* set min period for bit corruption */
+ dtype = 0x22;
+ retval = core_bench_state(res->size,
+ res->memblock[3],
+ res->seed1,
+ res->seed2,
+ dtype,
+ res->crc);
+ if (res->crcstate == 0)
+ res->crcstate = retval;
+ break;
+ case 1:
+ retval = core_bench_matrix(&(res->mat), dtype, res->crc);
+ if (res->crcmatrix == 0)
+ res->crcmatrix = retval;
+ break;
+ default:
+ retval = data;
+ break;
+ }
+ res->crc = crcu16(retval, res->crc);
+ retval &= 0x007f;
+ *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */
+ return retval;
+ }
+}
+/* Function: cmp_complex
+ Compare the data item in a list cell.
+
+ Can be used by mergesort.
+*/
+ee_s32
+cmp_complex(list_data *a, list_data *b, core_results *res)
+{
+ ee_s16 val1 = calc_func(&(a->data16), res);
+ ee_s16 val2 = calc_func(&(b->data16), res);
+ return val1 - val2;
+}
+
+/* Function: cmp_idx
+ Compare the idx item in a list cell, and regen the data.
+
+ Can be used by mergesort.
+*/
+ee_s32
+cmp_idx(list_data *a, list_data *b, core_results *res)
+{
+ if (res == NULL)
+ {
+ a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16 >> 8));
+ b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16 >> 8));
+ }
+ return a->idx - b->idx;
+}
+
+void
+copy_info(list_data *to, list_data *from)
+{
+ to->data16 = from->data16;
+ to->idx = from->idx;
+}
+
+/* Benchmark for linked list:
+ - Try to find multiple data items.
+ - List sort
+ - Operate on data from list (crc)
+ - Single remove/reinsert
+ * At the end of this function, the list is back to original state
+*/
+ee_u16
+core_bench_list(core_results *res, ee_s16 finder_idx)
+{
+ ee_u16 retval = 0;
+ ee_u16 found = 0, missed = 0;
+ list_head *list = res->list;
+ ee_s16 find_num = res->seed3;
+ list_head *this_find;
+ list_head *finder, *remover;
+ list_data info;
+ ee_s16 i;
+
+ info.idx = finder_idx;
+ /* find values in the list, and change the list each time
+ * (reverse and cache if value found) */
+ for (i = 0; i < find_num; i++)
+ {
+ info.data16 = (i & 0xff);
+ this_find = core_list_find(list, &info);
+ list = core_list_reverse(list);
+ if (this_find == NULL)
+ {
+ missed++;
+ retval += (list->next->info->data16 >> 8) & 1;
+ }
+ else
+ {
+ found++;
+ if (this_find->info->data16 & 0x1) /* use found value */
+ retval += (this_find->info->data16 >> 9) & 1;
+ /* and cache next item at the head of the list (if any) */
+ if (this_find->next != NULL)
+ {
+ finder = this_find->next;
+ this_find->next = finder->next;
+ finder->next = list->next;
+ list->next = finder;
+ }
+ }
+ if (info.idx >= 0)
+ info.idx++;
+#if CORE_DEBUG
+ ee_printf("List find %d: [%d,%d,%d]\n", i, retval, missed, found);
+#endif
+ }
+ retval += found * 4 - missed;
+ /* sort the list by data content and remove one item*/
+ if (finder_idx > 0)
+ list = core_list_mergesort(list, cmp_complex, res);
+ remover = core_list_remove(list->next);
+ /* CRC data content of list from location of index N forward, and then undo
+ * remove */
+ finder = core_list_find(list, &info);
+ if (!finder)
+ finder = list->next;
+ while (finder)
+ {
+ retval = crc16(list->info->data16, retval);
+ finder = finder->next;
+ }
+#if CORE_DEBUG
+ ee_printf("List sort 1: %04x\n", retval);
+#endif
+ remover = core_list_undo_remove(remover, list->next);
+ /* sort the list by index, in effect returning the list to original state */
+ list = core_list_mergesort(list, cmp_idx, NULL);
+ /* CRC data content of list */
+ finder = list->next;
+ while (finder)
+ {
+ retval = crc16(list->info->data16, retval);
+ finder = finder->next;
+ }
+#if CORE_DEBUG
+ ee_printf("List sort 2: %04x\n", retval);
+#endif
+ return retval;
+}
+/* Function: core_list_init
+ Initialize list with data.
+
+ Parameters:
+ blksize - Size of memory to be initialized.
+ memblock - Pointer to memory block.
+ seed - Actual values chosen depend on the seed parameter.
+ The seed parameter MUST be supplied from a source that cannot be
+ determined at compile time
+
+ Returns:
+ Pointer to the head of the list.
+
+*/
+list_head *
+core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed)
+{
+ /* calculated pointers for the list */
+ ee_u32 per_item = 16 + sizeof(struct list_data_s);
+ ee_u32 size = (blksize / per_item)
+ - 2; /* to accomodate systems with 64b pointers, and make sure
+ same code is executed, set max list elements */
+ list_head *memblock_end = memblock + size;
+ list_data *datablock = (list_data *)(memblock_end);
+ list_data *datablock_end = datablock + size;
+ /* some useful variables */
+ ee_u32 i;
+ list_head *finder, *list = memblock;
+ list_data info;
+
+ /* create a fake items for the list head and tail */
+ list->next = NULL;
+ list->info = datablock;
+ list->info->idx = 0x0000;
+ list->info->data16 = (ee_s16)0x8080;
+ memblock++;
+ datablock++;
+ info.idx = 0x7fff;
+ info.data16 = (ee_s16)0xffff;
+ core_list_insert_new(
+ list, &info, &memblock, &datablock, memblock_end, datablock_end);
+
+ /* then insert size items */
+ for (i = 0; i < size; i++)
+ {
+ ee_u16 datpat = ((ee_u16)(seed ^ i) & 0xf);
+ ee_u16 dat
+ = (datpat << 3) | (i & 0x7); /* alternate between algorithms */
+ info.data16 = (dat << 8) | dat; /* fill the data with actual data and
+ upper bits with rebuild value */
+ core_list_insert_new(
+ list, &info, &memblock, &datablock, memblock_end, datablock_end);
+ }
+ /* and now index the list so we know initial seed order of the list */
+ finder = list->next;
+ i = 1;
+ while (finder->next != NULL)
+ {
+ if (i < size / 5) /* first 20% of the list in order */
+ finder->info->idx = i++;
+ else
+ {
+ ee_u16 pat = (ee_u16)(i++ ^ seed); /* get a pseudo random number */
+ finder->info->idx = 0x3fff
+ & (((i & 0x07) << 8)
+ | pat); /* make sure the mixed items end up
+ after the ones in sequence */
+ }
+ finder = finder->next;
+ }
+ list = core_list_mergesort(list, cmp_idx, NULL);
+#if CORE_DEBUG
+ ee_printf("Initialized list:\n");
+ finder = list;
+ while (finder)
+ {
+ ee_printf(
+ "[%04x,%04x]", finder->info->idx, (ee_u16)finder->info->data16);
+ finder = finder->next;
+ }
+ ee_printf("\n");
+#endif
+ return list;
+}
+
+/* Function: core_list_insert
+ Insert an item to the list
+
+ Parameters:
+ insert_point - where to insert the item.
+ info - data for the cell.
+ memblock - pointer for the list header
+ datablock - pointer for the list data
+ memblock_end - end of region for list headers
+ datablock_end - end of region for list data
+
+ Returns:
+ Pointer to new item.
+*/
+list_head *
+core_list_insert_new(list_head * insert_point,
+ list_data * info,
+ list_head **memblock,
+ list_data **datablock,
+ list_head * memblock_end,
+ list_data * datablock_end)
+{
+ list_head *newitem;
+
+ if ((*memblock + 1) >= memblock_end)
+ return NULL;
+ if ((*datablock + 1) >= datablock_end)
+ return NULL;
+
+ newitem = *memblock;
+ (*memblock)++;
+ newitem->next = insert_point->next;
+ insert_point->next = newitem;
+
+ newitem->info = *datablock;
+ (*datablock)++;
+ copy_info(newitem->info, info);
+
+ return newitem;
+}
+
+/* Function: core_list_remove
+ Remove an item from the list.
+
+ Operation:
+ For a singly linked list, remove by copying the data from the next item
+ over to the current cell, and unlinking the next item.
+
+ Note:
+ since there is always a fake item at the end of the list, no need to
+ check for NULL.
+
+ Returns:
+ Removed item.
+*/
+list_head *
+core_list_remove(list_head *item)
+{
+ list_data *tmp;
+ list_head *ret = item->next;
+ /* swap data pointers */
+ tmp = item->info;
+ item->info = ret->info;
+ ret->info = tmp;
+ /* and eliminate item */
+ item->next = item->next->next;
+ ret->next = NULL;
+ return ret;
+}
+
+/* Function: core_list_undo_remove
+ Undo a remove operation.
+
+ Operation:
+ Since we want each iteration of the benchmark to be exactly the same,
+ we need to be able to undo a remove.
+ Link the removed item back into the list, and switch the info items.
+
+ Parameters:
+ item_removed - Return value from the
+ item_modified - List item that was modified during
+
+ Returns:
+ The item that was linked back to the list.
+
+*/
+list_head *
+core_list_undo_remove(list_head *item_removed, list_head *item_modified)
+{
+ list_data *tmp;
+ /* swap data pointers */
+ tmp = item_removed->info;
+ item_removed->info = item_modified->info;
+ item_modified->info = tmp;
+ /* and insert item */
+ item_removed->next = item_modified->next;
+ item_modified->next = item_removed;
+ return item_removed;
+}
+
+/* Function: core_list_find
+ Find an item in the list
+
+ Operation:
+ Find an item by idx (if not 0) or specific data value
+
+ Parameters:
+ list - list head
+ info - idx or data to find
+
+ Returns:
+ Found item, or NULL if not found.
+*/
+list_head *
+core_list_find(list_head *list, list_data *info)
+{
+ if (info->idx >= 0)
+ {
+ while (list && (list->info->idx != info->idx))
+ list = list->next;
+ return list;
+ }
+ else
+ {
+ while (list && ((list->info->data16 & 0xff) != info->data16))
+ list = list->next;
+ return list;
+ }
+}
+/* Function: core_list_reverse
+ Reverse a list
+
+ Operation:
+ Rearrange the pointers so the list is reversed.
+
+ Parameters:
+ list - list head
+ info - idx or data to find
+
+ Returns:
+ Found item, or NULL if not found.
+*/
+
+list_head *
+core_list_reverse(list_head *list)
+{
+ list_head *next = NULL, *tmp;
+ while (list)
+ {
+ tmp = list->next;
+ list->next = next;
+ next = list;
+ list = tmp;
+ }
+ return next;
+}
+/* Function: core_list_mergesort
+ Sort the list in place without recursion.
+
+ Description:
+ Use mergesort, as for linked list this is a realistic solution.
+ Also, since this is aimed at embedded, care was taken to use iterative
+ rather then recursive algorithm. The sort can either return the list to
+ original order (by idx) , or use the data item to invoke other other
+ algorithms and change the order of the list.
+
+ Parameters:
+ list - list to be sorted.
+ cmp - cmp function to use
+
+ Returns:
+ New head of the list.
+
+ Note:
+ We have a special header for the list that will always be first,
+ but the algorithm could theoretically modify where the list starts.
+
+ */
+list_head *
+core_list_mergesort(list_head *list, list_cmp cmp, core_results *res)
+{
+ list_head *p, *q, *e, *tail;
+ ee_s32 insize, nmerges, psize, qsize, i;
+
+ insize = 1;
+
+ while (1)
+ {
+ p = list;
+ list = NULL;
+ tail = NULL;
+
+ nmerges = 0; /* count number of merges we do in this pass */
+
+ while (p)
+ {
+ nmerges++; /* there exists a merge to be done */
+ /* step `insize' places along from p */
+ q = p;
+ psize = 0;
+ for (i = 0; i < insize; i++)
+ {
+ psize++;
+ q = q->next;
+ if (!q)
+ break;
+ }
+
+ /* if q hasn't fallen off end, we have two lists to merge */
+ qsize = insize;
+
+ /* now we have two lists; merge them */
+ while (psize > 0 || (qsize > 0 && q))
+ {
+
+ /* decide whether next element of merge comes from p or q */
+ if (psize == 0)
+ {
+ /* p is empty; e must come from q. */
+ e = q;
+ q = q->next;
+ qsize--;
+ }
+ else if (qsize == 0 || !q)
+ {
+ /* q is empty; e must come from p. */
+ e = p;
+ p = p->next;
+ psize--;
+ }
+ else if (cmp(p->info, q->info, res) <= 0)
+ {
+ /* First element of p is lower (or same); e must come from
+ * p. */
+ e = p;
+ p = p->next;
+ psize--;
+ }
+ else
+ {
+ /* First element of q is lower; e must come from q. */
+ e = q;
+ q = q->next;
+ qsize--;
+ }
+
+ /* add the next element to the merged list */
+ if (tail)
+ {
+ tail->next = e;
+ }
+ else
+ {
+ list = e;
+ }
+ tail = e;
+ }
+
+ /* now p has stepped `insize' places along, and q has too */
+ p = q;
+ }
+
+ tail->next = NULL;
+
+ /* If we have done only one merge, we're finished. */
+ if (nmerges <= 1) /* allow for nmerges==0, the empty list case */
+ return list;
+
+ /* Otherwise repeat, merging lists twice the size */
+ insize *= 2;
+ }
+#if COMPILER_REQUIRES_SORT_RETURN
+ return list;
+#endif
+}
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/core_matrix.c b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_matrix.c
new file mode 100644
index 0000000..29fd8ab
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_matrix.c
@@ -0,0 +1,359 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/*
+Topic: Description
+ Matrix manipulation benchmark
+
+ This very simple algorithm forms the basis of many more complex
+algorithms.
+
+ The tight inner loop is the focus of many optimizations (compiler as
+well as hardware based) and is thus relevant for embedded processing.
+
+ The total available data space will be divided to 3 parts:
+ NxN Matrix A - initialized with small values (upper 3/4 of the bits all
+zero). NxN Matrix B - initialized with medium values (upper half of the bits all
+zero). NxN Matrix C - used for the result.
+
+ The actual values for A and B must be derived based on input that is not
+available at compile time.
+*/
+ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val);
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval);
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val);
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val);
+
+#define matrix_test_next(x) (x + 1)
+#define matrix_clip(x, y) ((y) ? (x)&0x0ff : (x)&0x0ffff)
+#define matrix_big(x) (0xf000 | (x))
+#define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff << (to))))
+
+#if CORE_DEBUG
+void
+printmat(MATDAT *A, ee_u32 N, char *name)
+{
+ ee_u32 i, j;
+ ee_printf("Matrix %s [%dx%d]:\n", name, N, N);
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ if (j != 0)
+ ee_printf(",");
+ ee_printf("%d", A[i * N + j]);
+ }
+ ee_printf("\n");
+ }
+}
+void
+printmatC(MATRES *C, ee_u32 N, char *name)
+{
+ ee_u32 i, j;
+ ee_printf("Matrix %s [%dx%d]:\n", name, N, N);
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ if (j != 0)
+ ee_printf(",");
+ ee_printf("%d", C[i * N + j]);
+ }
+ ee_printf("\n");
+ }
+}
+#endif
+/* Function: core_bench_matrix
+ Benchmark function
+
+ Iterate N times,
+ changing the matrix values slightly by a constant amount each time.
+*/
+ee_u16
+core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc)
+{
+ ee_u32 N = p->N;
+ MATRES *C = p->C;
+ MATDAT *A = p->A;
+ MATDAT *B = p->B;
+ MATDAT val = (MATDAT)seed;
+
+ crc = crc16(matrix_test(N, C, A, B, val), crc);
+
+ return crc;
+}
+
+/* Function: matrix_test
+ Perform matrix manipulation.
+
+ Parameters:
+ N - Dimensions of the matrix.
+ C - memory for result matrix.
+ A - input matrix
+ B - operator matrix (not changed during operations)
+
+ Returns:
+ A CRC value that captures all results calculated in the function.
+ In particular, crc of the value calculated on the result matrix
+ after each step by .
+
+ Operation:
+
+ 1 - Add a constant value to all elements of a matrix.
+ 2 - Multiply a matrix by a constant.
+ 3 - Multiply a matrix by a vector.
+ 4 - Multiply a matrix by a matrix.
+ 5 - Add a constant value to all elements of a matrix.
+
+ After the last step, matrix A is back to original contents.
+*/
+ee_s16
+matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val)
+{
+ ee_u16 crc = 0;
+ MATDAT clipval = matrix_big(val);
+
+ matrix_add_const(N, A, val); /* make sure data changes */
+#if CORE_DEBUG
+ printmat(A, N, "matrix_add_const");
+#endif
+ matrix_mul_const(N, C, A, val);
+ crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+ printmatC(C, N, "matrix_mul_const");
+#endif
+ matrix_mul_vect(N, C, A, B);
+ crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+ printmatC(C, N, "matrix_mul_vect");
+#endif
+ matrix_mul_matrix(N, C, A, B);
+ crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+ printmatC(C, N, "matrix_mul_matrix");
+#endif
+ matrix_mul_matrix_bitextract(N, C, A, B);
+ crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+ printmatC(C, N, "matrix_mul_matrix_bitextract");
+#endif
+
+ matrix_add_const(N, A, -val); /* return matrix to initial value */
+ return crc;
+}
+
+/* Function : matrix_init
+ Initialize the memory block for matrix benchmarking.
+
+ Parameters:
+ blksize - Size of memory to be initialized.
+ memblk - Pointer to memory block.
+ seed - Actual values chosen depend on the seed parameter.
+ p - pointers to containing initialized matrixes.
+
+ Returns:
+ Matrix dimensions.
+
+ Note:
+ The seed parameter MUST be supplied from a source that cannot be
+ determined at compile time
+*/
+ee_u32
+core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p)
+{
+ ee_u32 N = 0;
+ MATDAT *A;
+ MATDAT *B;
+ ee_s32 order = 1;
+ MATDAT val;
+ ee_u32 i = 0, j = 0;
+ if (seed == 0)
+ seed = 1;
+ while (j < blksize)
+ {
+ i++;
+ j = i * i * 2 * 4;
+ }
+ N = i - 1;
+ A = (MATDAT *)align_mem(memblk);
+ B = A + N * N;
+
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ seed = ((order * seed) % 65536);
+ val = (seed + order);
+ val = matrix_clip(val, 0);
+ B[i * N + j] = val;
+ val = (val + order);
+ val = matrix_clip(val, 1);
+ A[i * N + j] = val;
+ order++;
+ }
+ }
+
+ p->A = A;
+ p->B = B;
+ p->C = (MATRES *)align_mem(B + N * N);
+ p->N = N;
+#if CORE_DEBUG
+ printmat(A, N, "A");
+ printmat(B, N, "B");
+#endif
+ return N;
+}
+
+/* Function: matrix_sum
+ Calculate a function that depends on the values of elements in the
+ matrix.
+
+ For each element, accumulate into a temporary variable.
+
+ As long as this value is under the parameter clipval,
+ add 1 to the result if the element is bigger then the previous.
+
+ Otherwise, reset the accumulator and add 10 to the result.
+*/
+ee_s16
+matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval)
+{
+ MATRES tmp = 0, prev = 0, cur = 0;
+ ee_s16 ret = 0;
+ ee_u32 i, j;
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ cur = C[i * N + j];
+ tmp += cur;
+ if (tmp > clipval)
+ {
+ ret += 10;
+ tmp = 0;
+ }
+ else
+ {
+ ret += (cur > prev) ? 1 : 0;
+ }
+ prev = cur;
+ }
+ }
+ return ret;
+}
+
+/* Function: matrix_mul_const
+ Multiply a matrix by a constant.
+ This could be used as a scaler for instance.
+*/
+void
+matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val)
+{
+ ee_u32 i, j;
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ C[i * N + j] = (MATRES)A[i * N + j] * (MATRES)val;
+ }
+ }
+}
+
+/* Function: matrix_add_const
+ Add a constant value to all elements of a matrix.
+*/
+void
+matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val)
+{
+ ee_u32 i, j;
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ A[i * N + j] += val;
+ }
+ }
+}
+
+/* Function: matrix_mul_vect
+ Multiply a matrix by a vector.
+ This is common in many simple filters (e.g. fir where a vector of
+ coefficients is applied to the matrix.)
+*/
+void
+matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B)
+{
+ ee_u32 i, j;
+ for (i = 0; i < N; i++)
+ {
+ C[i] = 0;
+ for (j = 0; j < N; j++)
+ {
+ C[i] += (MATRES)A[i * N + j] * (MATRES)B[j];
+ }
+ }
+}
+
+/* Function: matrix_mul_matrix
+ Multiply a matrix by a matrix.
+ Basic code is used in many algorithms, mostly with minor changes such as
+ scaling.
+*/
+void
+matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B)
+{
+ ee_u32 i, j, k;
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ C[i * N + j] = 0;
+ for (k = 0; k < N; k++)
+ {
+ C[i * N + j] += (MATRES)A[i * N + k] * (MATRES)B[k * N + j];
+ }
+ }
+ }
+}
+
+/* Function: matrix_mul_matrix_bitextract
+ Multiply a matrix by a matrix, and extract some bits from the result.
+ Basic code is used in many algorithms, mostly with minor changes such as
+ scaling.
+*/
+void
+matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B)
+{
+ ee_u32 i, j, k;
+ for (i = 0; i < N; i++)
+ {
+ for (j = 0; j < N; j++)
+ {
+ C[i * N + j] = 0;
+ for (k = 0; k < N; k++)
+ {
+ MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j];
+ C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7);
+ }
+ }
+ }
+}
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/core_portme.c b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_portme.c
new file mode 100644
index 0000000..640b562
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_portme.c
@@ -0,0 +1,182 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+
+
+#include "coremark.h"
+#include "core_portme.h"
+
+
+volatile CORETIMETYPE g_msticks=0;
+void systick_init(void);
+#define ITERATIONS (5500)
+
+
+#if VALIDATION_RUN
+volatile ee_s32 seed1_volatile = 0x3415;
+volatile ee_s32 seed2_volatile = 0x3415;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PERFORMANCE_RUN
+volatile ee_s32 seed1_volatile = 0x0;
+volatile ee_s32 seed2_volatile = 0x0;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PROFILE_RUN
+volatile ee_s32 seed1_volatile = 0x8;
+volatile ee_s32 seed2_volatile = 0x8;
+volatile ee_s32 seed3_volatile = 0x8;
+#endif
+volatile ee_s32 seed4_volatile = ITERATIONS;
+volatile ee_s32 seed5_volatile = 0;
+/* Porting : Timing functions
+ How to capture time and convert to seconds must be ported to whatever is
+ supported by the platform. e.g. Read value from on board RTC, read value from
+ cpu clock cycles performance counter etc. Sample implementation for standard
+ time.h and windows.h definitions included.
+*/
+CORETIMETYPE
+barebones_clock(void)
+{
+// return g_msticks;
+ return SysTick->CNT;
+}
+/* Define : TIMER_RES_DIVIDER
+ Divider to trade off timer resolution and total time that can be
+ measured.
+
+ Use lower values to increase resolution, but make sure that overflow
+ does not occur. If there are issues with the return value overflowing,
+ increase this value.
+ */
+#define CLOCKS_PER_SEC (SystemCoreClock)
+#define GETMYTIME(_t) (*_t = barebones_clock())
+#define MYTIMEDIFF(fin, ini) ((fin) - (ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of
+ the benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the
+ example code) or zeroing some system parameters - e.g. setting the cpu clocks
+ cycles to 0.
+*/
+void
+start_time(void)
+{
+ SysTick->CTLR = 0;
+ SysTick->CMP = 0xFFFFFFFF;
+ SysTick->CNT = 0;
+ GETMYTIME(&start_time_val);
+ SysTick->CTLR = 0b1101;
+}
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the
+ benchmark.
+
+ Implementation may be capturing a system timer (as implemented in the
+ example code) or other system parameters - e.g. reading the current value of
+ cpu cycles counter.
+*/
+void
+stop_time(void)
+{
+ SysTick->CTLR = 0;
+ GETMYTIME(&stop_time_val);
+}
+/* Function : get_time
+ Return an abstract "ticks" number that signifies time on the system.
+
+ Actual value returned may be cpu cycles, milliseconds or any other
+ value, as long as it can be converted to seconds by . This
+ methodology is taken to accomodate any hardware or simulated platform. The
+ sample implementation returns millisecs by default, and the resolution is
+ controlled by
+*/
+CORE_TICKS
+get_time(void)
+{
+ CORE_TICKS elapsed
+ = (CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+ return elapsed;
+}
+/* Function : time_in_secs
+ Convert the value returned by get_time to seconds.
+
+ The type is used to accomodate systems with no support for
+ floating point. Default implementation implemented by the EE_TICKS_PER_SEC
+ macro above.
+*/
+secs_ret
+time_in_secs(CORE_TICKS ticks)
+{
+ secs_ret retval = ((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+ return retval;
+}
+
+ee_u32 default_num_contexts = 1;
+
+/* Function : portable_init
+ Target specific initialization code
+ Test for some common mistakes.
+*/
+void
+portable_init(core_portable *p, int *argc, char *argv[])
+{
+//#error \
+// "Call board initialization routines in portable init (if needed), in particular initialize UART!\n"
+ SystemCoreClockUpdate();
+ Delay_Init();
+ USART_Printf_Init(115200);
+ ee_printf("MCU:CH32V203\r\n");
+ ee_printf("SystemClk:%dHz\r\n",SystemCoreClock);
+
+ if (sizeof(ee_ptr_int) != sizeof(ee_u8 *))
+ {
+ ee_printf(
+ "ERROR! Please define ee_ptr_int to a type that holds a "
+ "pointer!\n");
+ }
+ if (sizeof(ee_u32) != 4)
+ {
+ ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+ }
+ p->portable_id = 1;
+}
+/* Function : portable_fini
+ Target specific final code
+*/
+void
+portable_fini(core_portable *p)
+{
+ p->portable_id = 0;
+}
+
+
+
+
+
+
+
+
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/core_portme.h b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_portme.h
new file mode 100644
index 0000000..b9b8ade
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_portme.h
@@ -0,0 +1,213 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+/* Topic : Description
+ This file contains configuration constants required to execute on
+ different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+#include "debug.h"
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+ Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration : HAS_TIME_H
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 1
+#endif
+/* Configuration : USE_CLOCK
+ Define to 1 if platform has the time.h header file,
+ and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration : HAS_STDIO
+ Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration : HAS_PRINTF
+ Define to 1 if the platform has stdio.h and implements the printf
+ function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+ Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+#ifdef __GNUC__
+#define COMPILER_VERSION "GCC"__VERSION__
+#else
+#define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+#endif
+#endif
+#ifndef COMPILER_FLAGS
+#define COMPILER_FLAGS \
+ "-Ofast" /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+//#define MEM_LOCATION
+#endif
+
+/* Data Types :
+ To avoid compiler issues, define the data types that need ot be used for
+ 8b, 16b and 32b in .
+
+ *Imprtant* :
+ ee_ptr_int needs to be the data type used to hold pointers, otherwise
+ coremark may fail!!!
+*/
+typedef signed short ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int ee_s32;
+typedef double ee_f32;
+typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
+typedef ee_u32 ee_ptr_int;
+typedef size_t ee_size_t;
+#define NULL ((void *)0)
+/* align_mem :
+ This macro is used to align an offset to point to a 32b value. It is
+ used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3))
+
+/* Configuration : CORE_TICKS
+ Define type of return from the timing functions.
+ */
+#define CORETIMETYPE ee_u32
+typedef ee_u32 CORE_TICKS;
+
+/* Configuration : SEED_METHOD
+ Defines method to get seed values that cannot be computed at compile
+ time.
+
+ Valid values :
+ SEED_ARG - from command line.
+ SEED_FUNC - from a system function.
+ SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+ Defines method to get a block of memry.
+
+ Valid values :
+ MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+ MEM_STATIC - to use a static memory array.
+ MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_STATIC // MEM_STACK
+#endif
+
+/* Configuration : MULTITHREAD
+ Define for parallel execution
+
+ Valid values :
+ 1 - only one context (default).
+ N>1 - will execute N copies in parallel.
+
+ Note :
+ If this flag is defined to more then 1, an implementation for launching
+ parallel contexts must be defined.
+
+ Two sample implementations are provided. Use or
+ to enable them.
+
+ It is valid to have a different implementation of
+ and in , to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD 1
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+ Needed if platform does not support getting arguments to main.
+
+ Valid values :
+ 0 - argc/argv to main is supported
+ 1 - argc/argv to main is not supported
+
+ Note :
+ This flag only matters if MULTITHREAD has been defined to a value
+ greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 0
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+ Needed if platform does not support returning a value from main.
+
+ Valid values :
+ 0 - main returns an int, and return value will be 0.
+ 1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+ Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S
+{
+ ee_u8 portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) \
+ && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE == 1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE == 2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+int ee_printf(const char *fmt, ...);
+
+#define ee_printf printf
+
+#endif /* CORE_PORTME_H */
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/core_state.c b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_state.c
new file mode 100644
index 0000000..6dbab9d
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_state.c
@@ -0,0 +1,330 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/* local functions */
+enum CORE_STATE core_state_transition(ee_u8 **instr, ee_u32 *transition_count);
+
+/*
+Topic: Description
+ Simple state machines like this one are used in many embedded products.
+
+ For more complex state machines, sometimes a state transition table
+implementation is used instead, trading speed of direct coding for ease of
+maintenance.
+
+ Since the main goal of using a state machine in CoreMark is to excercise
+the switch/if behaviour, we are using a small moore machine.
+
+ In particular, this machine tests type of string input,
+ trying to determine whether the input is a number or something else.
+ (see core_state.png).
+*/
+
+/* Function: core_bench_state
+ Benchmark function
+
+ Go over the input twice, once direct, and once after introducing some
+ corruption.
+*/
+ee_u16
+core_bench_state(ee_u32 blksize,
+ ee_u8 *memblock,
+ ee_s16 seed1,
+ ee_s16 seed2,
+ ee_s16 step,
+ ee_u16 crc)
+{
+ ee_u32 final_counts[NUM_CORE_STATES];
+ ee_u32 track_counts[NUM_CORE_STATES];
+ ee_u8 *p = memblock;
+ ee_u32 i;
+
+#if CORE_DEBUG
+ ee_printf("State Bench: %d,%d,%d,%04x\n", seed1, seed2, step, crc);
+#endif
+ for (i = 0; i < NUM_CORE_STATES; i++)
+ {
+ final_counts[i] = track_counts[i] = 0;
+ }
+ /* run the state machine over the input */
+ while (*p != 0)
+ {
+ enum CORE_STATE fstate = core_state_transition(&p, track_counts);
+ final_counts[fstate]++;
+#if CORE_DEBUG
+ ee_printf("%d,", fstate);
+ }
+ ee_printf("\n");
+#else
+ }
+#endif
+ p = memblock;
+ while (p < (memblock + blksize))
+ { /* insert some corruption */
+ if (*p != ',')
+ *p ^= (ee_u8)seed1;
+ p += step;
+ }
+ p = memblock;
+ /* run the state machine over the input again */
+ while (*p != 0)
+ {
+ enum CORE_STATE fstate = core_state_transition(&p, track_counts);
+ final_counts[fstate]++;
+#if CORE_DEBUG
+ ee_printf("%d,", fstate);
+ }
+ ee_printf("\n");
+#else
+ }
+#endif
+ p = memblock;
+ while (p < (memblock + blksize))
+ { /* undo corruption is seed1 and seed2 are equal */
+ if (*p != ',')
+ *p ^= (ee_u8)seed2;
+ p += step;
+ }
+ /* end timing */
+ for (i = 0; i < NUM_CORE_STATES; i++)
+ {
+ crc = crcu32(final_counts[i], crc);
+ crc = crcu32(track_counts[i], crc);
+ }
+ return crc;
+}
+
+/* Default initialization patterns */
+static ee_u8 *intpat[4]
+ = { (ee_u8 *)"5012", (ee_u8 *)"1234", (ee_u8 *)"-874", (ee_u8 *)"+122" };
+static ee_u8 *floatpat[4] = { (ee_u8 *)"35.54400",
+ (ee_u8 *)".1234500",
+ (ee_u8 *)"-110.700",
+ (ee_u8 *)"+0.64400" };
+static ee_u8 *scipat[4] = { (ee_u8 *)"5.500e+3",
+ (ee_u8 *)"-.123e-2",
+ (ee_u8 *)"-87e+832",
+ (ee_u8 *)"+0.6e-12" };
+static ee_u8 *errpat[4] = { (ee_u8 *)"T0.3e-1F",
+ (ee_u8 *)"-T.T++Tq",
+ (ee_u8 *)"1T3.4e4z",
+ (ee_u8 *)"34.0e-T^" };
+
+/* Function: core_init_state
+ Initialize the input data for the state machine.
+
+ Populate the input with several predetermined strings, interspersed.
+ Actual patterns chosen depend on the seed parameter.
+
+ Note:
+ The seed parameter MUST be supplied from a source that cannot be
+ determined at compile time
+*/
+void
+core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p)
+{
+ ee_u32 total = 0, next = 0, i;
+ ee_u8 *buf = 0;
+#if CORE_DEBUG
+ ee_u8 *start = p;
+ ee_printf("State: %d,%d\n", size, seed);
+#endif
+ size--;
+ next = 0;
+ while ((total + next + 1) < size)
+ {
+ if (next > 0)
+ {
+ for (i = 0; i < next; i++)
+ *(p + total + i) = buf[i];
+ *(p + total + i) = ',';
+ total += next + 1;
+ }
+ seed++;
+ switch (seed & 0x7)
+ {
+ case 0: /* int */
+ case 1: /* int */
+ case 2: /* int */
+ buf = intpat[(seed >> 3) & 0x3];
+ next = 4;
+ break;
+ case 3: /* float */
+ case 4: /* float */
+ buf = floatpat[(seed >> 3) & 0x3];
+ next = 8;
+ break;
+ case 5: /* scientific */
+ case 6: /* scientific */
+ buf = scipat[(seed >> 3) & 0x3];
+ next = 8;
+ break;
+ case 7: /* invalid */
+ buf = errpat[(seed >> 3) & 0x3];
+ next = 8;
+ break;
+ default: /* Never happen, just to make some compilers happy */
+ break;
+ }
+ }
+ size++;
+ while (total < size)
+ { /* fill the rest with 0 */
+ *(p + total) = 0;
+ total++;
+ }
+#if CORE_DEBUG
+ ee_printf("State Input: %s\n", start);
+#endif
+}
+
+static ee_u8
+ee_isdigit(ee_u8 c)
+{
+ ee_u8 retval;
+ retval = ((c >= '0') & (c <= '9')) ? 1 : 0;
+ return retval;
+}
+
+/* Function: core_state_transition
+ Actual state machine.
+
+ The state machine will continue scanning until either:
+ 1 - an invalid input is detcted.
+ 2 - a valid number has been detected.
+
+ The input pointer is updated to point to the end of the token, and the
+ end state is returned (either specific format determined or invalid).
+*/
+
+enum CORE_STATE
+core_state_transition(ee_u8 **instr, ee_u32 *transition_count)
+{
+ ee_u8 * str = *instr;
+ ee_u8 NEXT_SYMBOL;
+ enum CORE_STATE state = CORE_START;
+ for (; *str && state != CORE_INVALID; str++)
+ {
+ NEXT_SYMBOL = *str;
+ if (NEXT_SYMBOL == ',') /* end of this input */
+ {
+ str++;
+ break;
+ }
+ switch (state)
+ {
+ case CORE_START:
+ if (ee_isdigit(NEXT_SYMBOL))
+ {
+ state = CORE_INT;
+ }
+ else if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-')
+ {
+ state = CORE_S1;
+ }
+ else if (NEXT_SYMBOL == '.')
+ {
+ state = CORE_FLOAT;
+ }
+ else
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_INVALID]++;
+ }
+ transition_count[CORE_START]++;
+ break;
+ case CORE_S1:
+ if (ee_isdigit(NEXT_SYMBOL))
+ {
+ state = CORE_INT;
+ transition_count[CORE_S1]++;
+ }
+ else if (NEXT_SYMBOL == '.')
+ {
+ state = CORE_FLOAT;
+ transition_count[CORE_S1]++;
+ }
+ else
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_S1]++;
+ }
+ break;
+ case CORE_INT:
+ if (NEXT_SYMBOL == '.')
+ {
+ state = CORE_FLOAT;
+ transition_count[CORE_INT]++;
+ }
+ else if (!ee_isdigit(NEXT_SYMBOL))
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_INT]++;
+ }
+ break;
+ case CORE_FLOAT:
+ if (NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e')
+ {
+ state = CORE_S2;
+ transition_count[CORE_FLOAT]++;
+ }
+ else if (!ee_isdigit(NEXT_SYMBOL))
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_FLOAT]++;
+ }
+ break;
+ case CORE_S2:
+ if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-')
+ {
+ state = CORE_EXPONENT;
+ transition_count[CORE_S2]++;
+ }
+ else
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_S2]++;
+ }
+ break;
+ case CORE_EXPONENT:
+ if (ee_isdigit(NEXT_SYMBOL))
+ {
+ state = CORE_SCIENTIFIC;
+ transition_count[CORE_EXPONENT]++;
+ }
+ else
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_EXPONENT]++;
+ }
+ break;
+ case CORE_SCIENTIFIC:
+ if (!ee_isdigit(NEXT_SYMBOL))
+ {
+ state = CORE_INVALID;
+ transition_count[CORE_INVALID]++;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ *instr = str;
+ return state;
+}
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/core_util.c b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_util.c
new file mode 100644
index 0000000..67c5d77
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/core_util.c
@@ -0,0 +1,249 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/* Function: get_seed
+ Get a values that cannot be determined at compile time.
+
+ Since different embedded systems and compilers are used, 3 different
+ methods are provided: 1 - Using a volatile variable. This method is only
+ valid if the compiler is forced to generate code that reads the value of a
+ volatile variable from memory at run time. Please note, if using this method,
+ you would need to modify core_portme.c to generate training profile. 2 -
+ Command line arguments. This is the preferred method if command line
+ arguments are supported. 3 - System function. If none of the first 2 methods
+ is available on the platform, a system function which is not a stub can be
+ used.
+
+ e.g. read the value on GPIO pins connected to switches, or invoke
+ special simulator functions.
+*/
+#if (SEED_METHOD == SEED_VOLATILE)
+extern volatile ee_s32 seed1_volatile;
+extern volatile ee_s32 seed2_volatile;
+extern volatile ee_s32 seed3_volatile;
+extern volatile ee_s32 seed4_volatile;
+extern volatile ee_s32 seed5_volatile;
+ee_s32
+get_seed_32(int i)
+{
+ ee_s32 retval;
+ switch (i)
+ {
+ case 1:
+ retval = seed1_volatile;
+ break;
+ case 2:
+ retval = seed2_volatile;
+ break;
+ case 3:
+ retval = seed3_volatile;
+ break;
+ case 4:
+ retval = seed4_volatile;
+ break;
+ case 5:
+ retval = seed5_volatile;
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+#elif (SEED_METHOD == SEED_ARG)
+ee_s32
+parseval(char *valstring)
+{
+ ee_s32 retval = 0;
+ ee_s32 neg = 1;
+ int hexmode = 0;
+ if (*valstring == '-')
+ {
+ neg = -1;
+ valstring++;
+ }
+ if ((valstring[0] == '0') && (valstring[1] == 'x'))
+ {
+ hexmode = 1;
+ valstring += 2;
+ }
+ /* first look for digits */
+ if (hexmode)
+ {
+ while (((*valstring >= '0') && (*valstring <= '9'))
+ || ((*valstring >= 'a') && (*valstring <= 'f')))
+ {
+ ee_s32 digit = *valstring - '0';
+ if (digit > 9)
+ digit = 10 + *valstring - 'a';
+ retval *= 16;
+ retval += digit;
+ valstring++;
+ }
+ }
+ else
+ {
+ while ((*valstring >= '0') && (*valstring <= '9'))
+ {
+ ee_s32 digit = *valstring - '0';
+ retval *= 10;
+ retval += digit;
+ valstring++;
+ }
+ }
+ /* now add qualifiers */
+ if (*valstring == 'K')
+ retval *= 1024;
+ if (*valstring == 'M')
+ retval *= 1024 * 1024;
+
+ retval *= neg;
+ return retval;
+}
+
+ee_s32
+get_seed_args(int i, int argc, char *argv[])
+{
+ if (argc > i)
+ return parseval(argv[i]);
+ return 0;
+}
+
+#elif (SEED_METHOD == SEED_FUNC)
+/* If using OS based function, you must define and implement the functions below
+ * in core_portme.h and core_portme.c ! */
+ee_s32
+get_seed_32(int i)
+{
+ ee_s32 retval;
+ switch (i)
+ {
+ case 1:
+ retval = portme_sys1();
+ break;
+ case 2:
+ retval = portme_sys2();
+ break;
+ case 3:
+ retval = portme_sys3();
+ break;
+ case 4:
+ retval = portme_sys4();
+ break;
+ case 5:
+ retval = portme_sys5();
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+#endif
+
+/* Function: crc*
+ Service functions to calculate 16b CRC code.
+
+*/
+ee_u16
+crcu8(ee_u8 data, ee_u16 crc)
+{
+ ee_u8 i = 0, x16 = 0, carry = 0;
+
+ for (i = 0; i < 8; i++)
+ {
+ x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1));
+ data >>= 1;
+
+ if (x16 == 1)
+ {
+ crc ^= 0x4002;
+ carry = 1;
+ }
+ else
+ carry = 0;
+ crc >>= 1;
+ if (carry)
+ crc |= 0x8000;
+ else
+ crc &= 0x7fff;
+ }
+ return crc;
+}
+ee_u16
+crcu16(ee_u16 newval, ee_u16 crc)
+{
+ crc = crcu8((ee_u8)(newval), crc);
+ crc = crcu8((ee_u8)((newval) >> 8), crc);
+ return crc;
+}
+ee_u16
+crcu32(ee_u32 newval, ee_u16 crc)
+{
+ crc = crc16((ee_s16)newval, crc);
+ crc = crc16((ee_s16)(newval >> 16), crc);
+ return crc;
+}
+ee_u16
+crc16(ee_s16 newval, ee_u16 crc)
+{
+ return crcu16((ee_u16)newval, crc);
+}
+
+ee_u8
+check_data_types()
+{
+ ee_u8 retval = 0;
+ if (sizeof(ee_u8) != 1)
+ {
+ ee_printf("ERROR: ee_u8 is not an 8b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_u16) != 2)
+ {
+ ee_printf("ERROR: ee_u16 is not a 16b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_s16) != 2)
+ {
+ ee_printf("ERROR: ee_s16 is not a 16b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_s32) != 4)
+ {
+ ee_printf("ERROR: ee_s32 is not a 32b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_u32) != 4)
+ {
+ ee_printf("ERROR: ee_u32 is not a 32b datatype!\n");
+ retval++;
+ }
+ if (sizeof(ee_ptr_int) != sizeof(int *))
+ {
+ ee_printf(
+ "ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n");
+ retval++;
+ }
+ if (retval > 0)
+ {
+ ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n");
+ }
+ return retval;
+}
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/coremark.h b/EVT/EXAM/APPLICATION/CoreMark/coremark/coremark.h
new file mode 100644
index 0000000..f7909f9
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/coremark.h
@@ -0,0 +1,183 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic: Description
+ This file contains declarations of the various benchmark functions.
+*/
+
+/* Configuration: TOTAL_DATA_SIZE
+ Define total size for data algorithms will operate on
+*/
+#ifndef TOTAL_DATA_SIZE
+#define TOTAL_DATA_SIZE 2 * 1000
+#endif
+
+#define SEED_ARG 0
+#define SEED_FUNC 1
+#define SEED_VOLATILE 2
+
+#define MEM_STATIC 0
+#define MEM_MALLOC 1
+#define MEM_STACK 2
+
+#include "core_portme.h"
+
+#if HAS_STDIO
+#include
+#endif
+#if HAS_PRINTF
+#define ee_printf printf
+#endif
+
+/* Actual benchmark execution in iterate */
+void *iterate(void *pres);
+
+/* Typedef: secs_ret
+ For machines that have floating point support, get number of seconds as
+ a double. Otherwise an unsigned int.
+*/
+#if HAS_FLOAT
+typedef double secs_ret;
+#else
+typedef ee_u32 secs_ret;
+#endif
+
+#if MAIN_HAS_NORETURN
+#define MAIN_RETURN_VAL
+#define MAIN_RETURN_TYPE void
+#else
+#define MAIN_RETURN_VAL 0
+#define MAIN_RETURN_TYPE int
+#endif
+
+void start_time(void);
+void stop_time(void);
+CORE_TICKS get_time(void);
+secs_ret time_in_secs(CORE_TICKS ticks);
+
+/* Misc useful functions */
+ee_u16 crcu8(ee_u8 data, ee_u16 crc);
+ee_u16 crc16(ee_s16 newval, ee_u16 crc);
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc);
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc);
+ee_u8 check_data_types(void);
+void * portable_malloc(ee_size_t size);
+void portable_free(void *p);
+ee_s32 parseval(char *valstring);
+
+/* Algorithm IDS */
+#define ID_LIST (1 << 0)
+#define ID_MATRIX (1 << 1)
+#define ID_STATE (1 << 2)
+#define ALL_ALGORITHMS_MASK (ID_LIST | ID_MATRIX | ID_STATE)
+#define NUM_ALGORITHMS 3
+
+/* list data structures */
+typedef struct list_data_s
+{
+ ee_s16 data16;
+ ee_s16 idx;
+} list_data;
+
+typedef struct list_head_s
+{
+ struct list_head_s *next;
+ struct list_data_s *info;
+} list_head;
+
+/*matrix benchmark related stuff */
+#define MATDAT_INT 1
+#if MATDAT_INT
+typedef ee_s16 MATDAT;
+typedef ee_s32 MATRES;
+#else
+typedef ee_f16 MATDAT;
+typedef ee_f32 MATRES;
+#endif
+
+typedef struct MAT_PARAMS_S
+{
+ int N;
+ MATDAT *A;
+ MATDAT *B;
+ MATRES *C;
+} mat_params;
+
+/* state machine related stuff */
+/* List of all the possible states for the FSM */
+typedef enum CORE_STATE
+{
+ CORE_START = 0,
+ CORE_INVALID,
+ CORE_S1,
+ CORE_S2,
+ CORE_INT,
+ CORE_FLOAT,
+ CORE_EXPONENT,
+ CORE_SCIENTIFIC,
+ NUM_CORE_STATES
+} core_state_e;
+
+/* Helper structure to hold results */
+typedef struct RESULTS_S
+{
+ /* inputs */
+ ee_u16 seed1; /* Initializing seed */
+ ee_u16 seed2; /* Initializing seed */
+ ee_u16 seed3; /* Initializing seed */
+ void * memblock[4]; /* Pointer to safe memory location */
+ ee_u32 size; /* Size of the data */
+ ee_u32 iterations; /* Number of iterations to execute */
+ ee_u32 execs; /* Bitmask of operations to execute */
+ struct list_head_s *list;
+ mat_params mat;
+ /* outputs */
+ ee_u16 crc;
+ ee_u16 crclist;
+ ee_u16 crcmatrix;
+ ee_u16 crcstate;
+ ee_u16 err;
+ /* ultithread specific */
+ core_portable port;
+} /*__attribute__((packed))*/ core_results ;
+
+/* Multicore execution handling */
+#if (MULTITHREAD > 1)
+ee_u8 core_start_parallel(core_results *res);
+ee_u8 core_stop_parallel(core_results *res);
+#endif
+
+/* list benchmark functions */
+list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed);
+ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx);
+
+/* state benchmark functions */
+void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p);
+ee_u16 core_bench_state(ee_u32 blksize,
+ ee_u8 *memblock,
+ ee_s16 seed1,
+ ee_s16 seed2,
+ ee_s16 step,
+ ee_u16 crc);
+
+/* matrix benchmark functions */
+ee_u32 core_init_matrix(ee_u32 blksize,
+ void * memblk,
+ ee_s32 seed,
+ mat_params *p);
+ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc);
diff --git a/EVT/EXAM/APPLICATION/CoreMark/coremark/syscall.c b/EVT/EXAM/APPLICATION/CoreMark/coremark/syscall.c
new file mode 100644
index 0000000..02500b7
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/coremark/syscall.c
@@ -0,0 +1,177 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
+ *
+ * @file syscall.c
+ * @author Microsemi SoC Products Group
+ * @brief Stubs for system calls.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+#undef errno
+int errno;
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+void write_hex(int fd, uint32_t hex)
+{
+ uint8_t ii;
+ uint8_t jj;
+ char towrite;
+ uint8_t digit;
+
+ write( fd , "0x", 2 );
+
+ for (ii = 8 ; ii > 0; ii--)
+ {
+ jj = ii-1;
+ digit = ((hex & (0xF << (jj*4))) >> (jj*4));
+ towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
+ write( fd, &towrite, 1);
+ }
+}
+
+
+void _exit(int code)
+{
+
+
+ while (1);
+}
+
+void *_sbrk(ptrdiff_t incr)
+{
+ extern char _end[];
+ extern char _heap_end[];
+ static char *curbrk = _end;
+
+ if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+ {
+ return ((char *) - 1);
+ }
+
+ curbrk += incr;
+ return curbrk - incr;
+}
+
+int _isatty(int fd)
+{
+ if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
+ {
+ return 1;
+ }
+
+ errno = EBADF;
+ return 0;
+}
+
+static int stub(int err)
+{
+ errno = err;
+ return -1;
+}
+
+int _open(const char* name, int flags, int mode)
+{
+ return stub(ENOENT);
+}
+
+int _openat(int dirfd, const char* name, int flags, int mode)
+{
+ return stub(ENOENT);
+}
+
+int _close(int fd)
+{
+ return stub(EBADF);
+}
+
+int _execve(const char* name, char* const argv[], char* const env[])
+{
+ return stub(ENOMEM);
+}
+
+int _fork()
+{
+ return stub(EAGAIN);
+}
+
+int _fstat(int fd, struct stat *st)
+{
+ if (isatty(fd))
+ {
+ st->st_mode = S_IFCHR;
+ return 0;
+ }
+
+ return stub(EBADF);
+}
+
+int _getpid()
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ return stub(EINVAL);
+}
+
+int _link(const char *old_name, const char *new_name)
+{
+ return stub(EMLINK);
+}
+
+off_t _lseek(int fd, off_t ptr, int dir)
+{
+ if (_isatty(fd))
+ {
+ return 0;
+ }
+
+ return stub(EBADF);
+}
+
+ssize_t _read(int fd, void* ptr, size_t len)
+{
+
+ return stub(EBADF);
+}
+
+int _stat(const char* file, struct stat* st)
+{
+ return stub(EACCES);
+}
+
+clock_t _times(struct tms* buf)
+{
+ return stub(EACCES);
+}
+
+int _unlink(const char* name)
+{
+ return stub(ENOENT);
+}
+
+int _wait(int* status)
+{
+ return stub(ECHILD);
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/EVT/EXAM/APPLICATION/CoreMark/main.c b/EVT/EXAM/APPLICATION/CoreMark/main.c
new file mode 100644
index 0000000..f9dcd92
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/CoreMark/main.c
@@ -0,0 +1,466 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* File: core_main.c
+ This file contains the framework to acquire a block of memory, seed
+ initial parameters, tun t he benchmark and report the results.
+*/
+
+/* Note:
+ * a.If the actual application must require the use of the system with a frequency greater than 120M
+ * b.This routine under 168M(12M_HSE) system conditions_only applied to CH32V20x_D6
+ * c.168M is only suitable for commercial-grade applications: -10鈩 < TA < 70鈩 with good heat dissipation
+ */
+
+#include "coremark.h"
+
+/* Function: iterate
+ Run the benchmark for a specified number of iterations.
+
+ Operation:
+ For each type of benchmarked algorithm:
+ a - Initialize the data block for the algorithm.
+ b - Execute the algorithm N times.
+
+ Returns:
+ NULL.
+*/
+
+static ee_u16 list_known_crc[] = { (ee_u16)0xd4b0,
+ (ee_u16)0x3340,
+ (ee_u16)0x6a79,
+ (ee_u16)0xe714,
+ (ee_u16)0xe3c1 };
+static ee_u16 matrix_known_crc[] = { (ee_u16)0xbe52,
+ (ee_u16)0x1199,
+ (ee_u16)0x5608,
+ (ee_u16)0x1fd7,
+ (ee_u16)0x0747 };
+static ee_u16 state_known_crc[] = { (ee_u16)0x5e47,
+ (ee_u16)0x39bf,
+ (ee_u16)0xe5a4,
+ (ee_u16)0x8e3a,
+ (ee_u16)0x8d84 };
+void *
+iterate(void *pres)
+{
+ ee_u32 i;
+ ee_u16 crc;
+ core_results *res = (core_results *)pres;
+ ee_u32 iterations = res->iterations;
+ res->crc = 0;
+ res->crclist = 0;
+ res->crcmatrix = 0;
+ res->crcstate = 0;
+
+ for (i = 0; i < iterations; i++)
+ {
+ crc = core_bench_list(res, 1);
+ res->crc = crcu16(crc, res->crc);
+ crc = core_bench_list(res, -1);
+ res->crc = crcu16(crc, res->crc);
+ if (i == 0)
+ res->crclist = res->crc;
+ }
+ return NULL;
+}
+
+#if (SEED_METHOD == SEED_ARG)
+ee_s32 get_seed_args(int i, int argc, char *argv[]);
+#define get_seed(x) (ee_s16) get_seed_args(x, argc, argv)
+#define get_seed_32(x) get_seed_args(x, argc, argv)
+#else /* via function or volatile */
+ee_s32 get_seed_32(int i);
+#define get_seed(x) (ee_s16) get_seed_32(x)
+#endif
+
+#if (MEM_METHOD == MEM_STATIC)
+ee_u8 static_memblk[TOTAL_DATA_SIZE];
+#endif
+char *mem_name[3] = { "Static", "Heap", "Stack" };
+/* Function: main
+ Main entry routine for the benchmark.
+ This function is responsible for the following steps:
+
+ 1 - Initialize input seeds from a source that cannot be determined at
+ compile time. 2 - Initialize memory block for use. 3 - Run and time the
+ benchmark. 4 - Report results, testing the validity of the output if the
+ seeds are known.
+
+ Arguments:
+ 1 - first seed : Any value
+ 2 - second seed : Must be identical to first for iterations to be
+ identical 3 - third seed : Any value, should be at least an order of
+ magnitude less then the input size, but bigger then 32. 4 - Iterations :
+ Special, if set to 0, iterations will be automatically determined such that
+ the benchmark will run between 10 to 100 secs
+
+*/
+core_results results[MULTITHREAD];
+#if MAIN_HAS_NOARGC
+MAIN_RETURN_TYPE
+main(void)
+{
+ int argc = 0;
+ char *argv[1];
+#else
+
+MAIN_RETURN_TYPE
+main(int argc, char *argv[])
+{
+#endif
+
+ ee_u16 i, j = 0, num_algorithms = 0;
+
+ ee_s16 known_id = -1, total_errors = 0;
+ ee_u16 seedcrc = 0;
+ CORE_TICKS total_time;
+// core_results results[MULTITHREAD];
+
+ #if (MEM_METHOD == MEM_STACK)
+ ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD];
+ #endif
+
+ /* first call any initializations needed */
+ portable_init(&(results[0].port), &argc, argv);
+
+ /* First some checks to make sure benchmark will run ok */
+ if (sizeof(struct list_head_s) > 128)
+ {
+ ee_printf("list_head structure too big for comparable data!\n");
+ return MAIN_RETURN_VAL;
+ }
+ results[0].seed1 = get_seed(1);
+ results[0].seed2 = get_seed(2);
+ results[0].seed3 = get_seed(3);
+ results[0].iterations = get_seed_32(4);
+#if CORE_DEBUG
+ results[0].iterations = 1;
+#endif
+ results[0].execs = get_seed_32(5);
+ if (results[0].execs == 0)
+ { /* if not supplied, execute all algorithms */
+ results[0].execs = ALL_ALGORITHMS_MASK;
+ }
+ /* put in some default values based on one seed only for easy testing */
+ if ((results[0].seed1 == 0) && (results[0].seed2 == 0)
+ && (results[0].seed3 == 0))
+ { /* perfromance run */
+ results[0].seed1 = 0;
+ results[0].seed2 = 0;
+ results[0].seed3 = 0x66;
+ }
+ if ((results[0].seed1 == 1) && (results[0].seed2 == 0)
+ && (results[0].seed3 == 0))
+ { /* validation run */
+ results[0].seed1 = 0x3415;
+ results[0].seed2 = 0x3415;
+ results[0].seed3 = 0x66;
+ }
+#if (MEM_METHOD == MEM_STATIC)
+ results[0].memblock[0] = (void *)static_memblk;
+ results[0].size = TOTAL_DATA_SIZE;
+ results[0].err = 0;
+#if (MULTITHREAD > 1)
+#error "Cannot use a static data area with multiple contexts!"
+#endif
+#elif (MEM_METHOD == MEM_MALLOC)
+ for (i = 0; i < MULTITHREAD; i++)
+ {
+ ee_s32 malloc_override = get_seed(7);
+ if (malloc_override != 0)
+ results[i].size = malloc_override;
+ else
+ results[i].size = TOTAL_DATA_SIZE;
+ results[i].memblock[0] = portable_malloc(results[i].size);
+ results[i].seed1 = results[0].seed1;
+ results[i].seed2 = results[0].seed2;
+ results[i].seed3 = results[0].seed3;
+ results[i].err = 0;
+ results[i].execs = results[0].execs;
+ }
+#elif (MEM_METHOD == MEM_STACK)
+for (i = 0; i < MULTITHREAD; i++)
+{
+ results[i].memblock[0] = stack_memblock + i * TOTAL_DATA_SIZE;
+ results[i].size = TOTAL_DATA_SIZE;
+ results[i].seed1 = results[0].seed1;
+ results[i].seed2 = results[0].seed2;
+ results[i].seed3 = results[0].seed3;
+ results[i].err = 0;
+ results[i].execs = results[0].execs;
+}
+#else
+#error "Please define a way to initialize a memory block."
+#endif
+ /* Data init */
+ /* Find out how space much we have based on number of algorithms */
+ for (i = 0; i < NUM_ALGORITHMS; i++)
+ {
+ if ((1 << (ee_u32)i) & results[0].execs)
+ num_algorithms++;
+ }
+ for (i = 0; i < MULTITHREAD; i++)
+ results[i].size = results[i].size / num_algorithms;
+ /* Assign pointers */
+ for (i = 0; i < NUM_ALGORITHMS; i++)
+ {
+ ee_u32 ctx;
+ if ((1 << (ee_u32)i) & results[0].execs)
+ {
+ for (ctx = 0; ctx < MULTITHREAD; ctx++)
+ results[ctx].memblock[i + 1]
+ = (char *)(results[ctx].memblock[0]) + results[0].size * j;
+ j++;
+ }
+ }
+ /* call inits */
+ for (i = 0; i < MULTITHREAD; i++)
+ {
+ if (results[i].execs & ID_LIST)
+ {
+ results[i].list = core_list_init(
+ results[0].size, results[i].memblock[1], results[i].seed1);
+ }
+ if (results[i].execs & ID_MATRIX)
+ {
+ core_init_matrix(results[0].size,
+ results[i].memblock[2],
+ (ee_s32)results[i].seed1
+ | (((ee_s32)results[i].seed2) << 16),
+ &(results[i].mat));
+ }
+ if (results[i].execs & ID_STATE)
+ {
+ core_init_state(
+ results[0].size, results[i].seed1, results[i].memblock[3]);
+ }
+ }
+
+ /* automatically determine number of iterations if not set */
+ if (results[0].iterations == 0)
+ {
+ secs_ret secs_passed = 0;
+ ee_u32 divisor;
+ results[0].iterations = 1;
+ while (secs_passed < (secs_ret)1)
+ {
+ results[0].iterations *= 10;
+ start_time();
+ iterate(&results[0]);
+ stop_time();
+ secs_passed = time_in_secs(get_time());
+ }
+ /* now we know it executes for at least 1 sec, set actual run time at
+ * about 10 secs */
+ divisor = (ee_u32)secs_passed;
+ if (divisor == 0) /* some machines cast float to int as 0 since this
+ conversion is not defined by ANSI, but we know at
+ least one second passed */
+ divisor = 1;
+ results[0].iterations *= 1 + 10 / divisor;
+ }
+ /* perform actual benchmark */
+ start_time();
+#if (MULTITHREAD > 1)
+ if (default_num_contexts > MULTITHREAD)
+ {
+ default_num_contexts = MULTITHREAD;
+ }
+ for (i = 0; i < default_num_contexts; i++)
+ {
+ results[i].iterations = results[0].iterations;
+ results[i].execs = results[0].execs;
+ core_start_parallel(&results[i]);
+ }
+ for (i = 0; i < default_num_contexts; i++)
+ {
+ core_stop_parallel(&results[i]);
+ }
+#else
+ iterate(&results[0]);
+#endif
+ stop_time();
+ total_time = get_time();
+ /* get a function of the input to report */
+ seedcrc = crc16(results[0].seed1, seedcrc);
+ seedcrc = crc16(results[0].seed2, seedcrc);
+ seedcrc = crc16(results[0].seed3, seedcrc);
+ seedcrc = crc16(results[0].size, seedcrc);
+
+ switch (seedcrc)
+ { /* test known output for common seeds */
+ case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */
+ known_id = 0;
+ ee_printf("6k performance run parameters for coremark.\n");
+ break;
+ case 0x7b05: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per
+ algorithm */
+ known_id = 1;
+ ee_printf("6k validation run parameters for coremark.\n");
+ break;
+ case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm
+ */
+ known_id = 2;
+ ee_printf("Profile generation run parameters for coremark.\n");
+ break;
+ case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */
+ known_id = 3;
+ ee_printf("2K performance run parameters for coremark.\n");
+ break;
+ case 0x18f2: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per
+ algorithm */
+ known_id = 4;
+ ee_printf("2K validation run parameters for coremark.\n");
+ break;
+ default:
+ total_errors = -1;
+ break;
+ }
+ if (known_id >= 0)
+ {
+ for (i = 0; i < default_num_contexts; i++)
+ {
+ results[i].err = 0;
+ if ((results[i].execs & ID_LIST)
+ && (results[i].crclist != list_known_crc[known_id]))
+ {
+ ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n",
+ i,
+ results[i].crclist,
+ list_known_crc[known_id]);
+ results[i].err++;
+ }
+ if ((results[i].execs & ID_MATRIX)
+ && (results[i].crcmatrix != matrix_known_crc[known_id]))
+ {
+ ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n",
+ i,
+ results[i].crcmatrix,
+ matrix_known_crc[known_id]);
+ results[i].err++;
+ }
+ if ((results[i].execs & ID_STATE)
+ && (results[i].crcstate != state_known_crc[known_id]))
+ {
+ ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n",
+ i,
+ results[i].crcstate,
+ state_known_crc[known_id]);
+ results[i].err++;
+ }
+ total_errors += results[i].err;
+ }
+ }
+ total_errors += check_data_types();
+ /* and report results */
+ ee_printf("CoreMark Size : %lu\n", (long unsigned)results[0].size);
+ ee_printf("Total ticks : %lu\n", (long unsigned)total_time);
+#if HAS_FLOAT
+ ee_printf("Total time (secs): %f\n", time_in_secs(total_time));
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %f\n",
+ default_num_contexts * results[0].iterations
+ / time_in_secs(total_time));
+#else
+ ee_printf("Total time (secs): %d\n", time_in_secs(total_time));
+ if (time_in_secs(total_time) > 0)
+ ee_printf("Iterations/Sec : %d\n",
+ default_num_contexts * results[0].iterations
+ / time_in_secs(total_time));
+#endif
+ if (time_in_secs(total_time) < 10)
+ {
+ ee_printf(
+ "ERROR! Must execute for at least 10 secs for a valid result!\n");
+ total_errors++;
+ }
+
+ ee_printf("Iterations : %lu\n",
+ (long unsigned)default_num_contexts * results[0].iterations);
+ ee_printf("Compiler version : %s\n", COMPILER_VERSION);
+ ee_printf("Compiler flags : %s\n", COMPILER_FLAGS);
+#if (MULTITHREAD > 1)
+ ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts);
+#endif
+
+/* changed by TempersLee */
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+ ee_printf("Memory location : %s\n", MEM_LOCATION);
+#else
+ ee_printf("Memory location : %s\n", mem_name[MEM_METHOD]);
+#endif
+ /* output for verification */
+ ee_printf("seedcrc : 0x%04x\n", seedcrc);
+ if (results[0].execs & ID_LIST)
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crclist : 0x%04x\n", i, results[i].crclist);
+ if (results[0].execs & ID_MATRIX)
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crcmatrix : 0x%04x\n", i, results[i].crcmatrix);
+ if (results[0].execs & ID_STATE)
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crcstate : 0x%04x\n", i, results[i].crcstate);
+ for (i = 0; i < default_num_contexts; i++)
+ ee_printf("[%d]crcfinal : 0x%04x\n", i, results[i].crc);
+ if (total_errors == 0)
+ {
+ ee_printf(
+ "Correct operation validated. See README.md for run and reporting "
+ "rules.\n");
+#if HAS_FLOAT
+ if (known_id == 3)
+ {
+ ee_printf("CoreMark 1.0 : %f / %s %s",
+ default_num_contexts * results[0].iterations
+ / time_in_secs(total_time),
+ COMPILER_VERSION,
+ COMPILER_FLAGS);
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+ ee_printf(" / %s", MEM_LOCATION);
+#else
+ ee_printf(" / %s", mem_name[MEM_METHOD]);
+#endif
+
+#if (MULTITHREAD > 1)
+ ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD);
+#endif
+ ee_printf("\n");
+ ee_printf("If working at 1MHz,CoreMark 1.0 : %f/MHz\n",default_num_contexts * results[0].iterations
+ / time_in_secs(total_time)/(SystemCoreClock/1000000));
+
+ }
+#endif
+ }
+ if (total_errors > 0)
+ ee_printf("Errors detected\n");
+ if (total_errors < 0)
+ ee_printf(
+ "Cannot validate operation for these seed values, please compare "
+ "with results on a known platform.\n");
+
+#if (MEM_METHOD == MEM_MALLOC)
+ for (i = 0; i < MULTITHREAD; i++)
+ portable_free(results[i].memblock[0]);
+#endif
+ /* And last call any target specific code for finalizing */
+ portable_fini(&(results[0].port));
+
+ while(1);
+// return MAIN_RETURN_VAL;
+}
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c
index 825189e..3a66f7a 100644
--- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c
@@ -1,9 +1,9 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : CH223.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2023/08/15
- * Description : CH223芯片操作相关文件
+ * Version : V1.0.1
+ * Date : 2025/10/27
+ * Description : This file provides all the CH223 functions
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
@@ -36,7 +36,6 @@ void IIC_Init(u32 bound, u16 address)
I2C_InitTypeDef I2C_InitTSturcture={0};
RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE );
-// GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE);
RCC_APB1PeriphClockCmd( RCC_APB1Periph_I2C2, ENABLE );
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
@@ -59,6 +58,7 @@ void IIC_Init(u32 bound, u16 address)
I2C_Cmd( I2C2, ENABLE );
}
+
/*********************************************************************
* @fn CH223_Init
*
@@ -192,6 +192,7 @@ void CH223_Read(u16 ReadAddr, u32 *pBuffer, u16 NumToRead)
NumToRead--;
}
}
+
/*********************************************************************
* @fn CH223_Write
*
@@ -214,7 +215,6 @@ void CH223_Write(u16 WriteAddr, u8 *pBuffer, u16 NumToWrite)
}
}
-
/*********************************************************************
* @fn Buffer_Change
*
@@ -255,6 +255,7 @@ void Buffer_Change(u32 buffer[], int n)
}
}
}
+
/*********************************************************************
* @fn Current_VI
*
@@ -275,8 +276,9 @@ void Current_VI(u8 ndo_select)
tempI = BufferI[ndo_select] % 10;
current[1] = BufferI[ndo_select] / 10;
- printf("The current regulating voltage is：%d.%dV,%d.%dA\t\r\n", current[0], tempV, current[1], tempI);
+ printf("The current regulating voltage is: %d.%dV,%d.%dA\t\r\n", current[0], tempV, current[1], tempI);
}
+
/*********************************************************************
* @fn User_Set_VI
*
@@ -287,7 +289,6 @@ void Current_VI(u8 ndo_select)
*
* @return none
*/
-
void User_Set_VI(u8 TargetData)
{
u8 ndo_select = 0, state_flag = 0;
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c
index 4ed544e..cb757b2 100644
--- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c
@@ -19,10 +19,10 @@ CH223 chip application routine
#include "debug.h"
#include"CH223.h"
-u8 ndo = 0;//Number of NDOs in SrcCap
-u8 IT_flag = 0;
-u8 rst_IT = 0, cc_IT = 0, srccap_IT = 0, ps_IT = 0;//Interrupt flag
-s16 Calibrattion_Val = 0;
+vu8 ndo = 0;//Number of NDOs in SrcCap
+vu8 IT_flag = 0;
+vu8 rst_IT = 0, cc_IT = 0, srccap_IT = 0, ps_IT = 0;//Interrupt flag
+vs16 Calibrattion_Val = 0;
u16 TxBuf[1024];
/*********************************************************************
@@ -150,7 +150,7 @@ void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsiz
*/
u16 Get_ConversionVal(s16 val)
{
- if((val + Calibrattion_Val) < 0)
+ if((val + Calibrattion_Val) < 0 || val==0)
return 0;
if((Calibrattion_Val + val) > 4095||val==4095)
return 4095;
@@ -242,12 +242,12 @@ int main(void)
CH223_Init();
ADC_Function_Init();
EXTI0_INT_INIT();
- printf("PD_CH223 Demo！\r\n");
+ printf("PD_CH223 Demo锛侊紒\r\n");
printf("\r\n");
IT_flag = CH223_ReadOneByte(0xB4);
if (IT_flag==0x0c)
{
- printf("power-on reset！！！\r\n");
+ printf("power-on reset锛侊紒锛侊紒\r\n");
printf("\r\n");
Delay_Ms(10);
printf("CC Connecting...\r\n");
@@ -258,14 +258,14 @@ int main(void)
Delay_Ms(1);
while(ps_IT) //PS_RDY -->The power supply reaches the required working state
{
- CH223_WriteOneByte(0xB6, 0x19); //The initial voltage is set to 9V：0x2D
+ CH223_WriteOneByte(0xB6, 0x19); //The initial voltage is set to 9V锛0x2D
res = CH223_ReadOneByte(0xB6);
- printf("The initial voltage is set to：%dV\r\n",res*200/1000);
+ printf("The initial voltage is set to锛%dV\r\n",res*200/1000);
printf("\r\n");
Delay_Ms(300);
if (rst_IT == 1)
{
- printf("power-on reset！！！\r\n");
+ printf("power-on reset锛侊紒锛侊紒\r\n");
printf("\r\n");
}
if (cc_IT == 1)
@@ -281,7 +281,7 @@ int main(void)
Buffer_Change(Buffer, ndo);
if (srccap_IT == 1) //Display SRCCAP message
{
- printf("Received SrcCap,NDO data is：\n");
+ printf("Received SrcCap,NDO data is锛歕n");
printf("\r\n");
for(n = 0; n < ndo; n++)
{
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/.template b/EVT/EXAM/APPLICATION/WS2812_LED/.template
index 3c7f718..b9cb595 100644
--- a/EVT/EXAM/APPLICATION/WS2812_LED/.template
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/.template
@@ -13,5 +13,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
CLKSpeed=1
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c
index ec99e9d..e3dff91 100644
--- a/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c
@@ -37,9 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
- printf("\nHardFault \n");
- printf("mepc %x \n",__get_MEPC());
- printf("mcause %x \n",__get_MCAUSE());
+ NVIC_SystemReset();
while (1)
{
}
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BKP/BKP/.template b/EVT/EXAM/BKP/BKP/.template
index fe2049d..ede429d 100644
--- a/EVT/EXAM/BKP/BKP/.template
+++ b/EVT/EXAM/BKP/BKP/.template
@@ -13,5 +13,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
CLKSpeed=1
diff --git a/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c
+++ b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c
index be44e43..e324c09 100644
--- a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c
index 2e5ce73..6fcdb92 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/HID_Consumer/Profile/scanparamservice.c b/EVT/EXAM/BLE/HID_Consumer/Profile/scanparamservice.c
index e97a6b1..0db4870 100644
--- a/EVT/EXAM/BLE/HID_Consumer/Profile/scanparamservice.c
+++ b/EVT/EXAM/BLE/HID_Consumer/Profile/scanparamservice.c
@@ -280,7 +280,7 @@ void ScanParam_RefreshNotify(uint16_t connHandle)
if(noti.pValue != NULL)
{
// send notification
- noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_CCCD_IDX].handle;
+ noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_IDX].handle;
noti.len = SCAN_PARAM_REFRESH_LEN;
noti.pValue[0] = SCAN_PARAM_REFRESH_REQ;
diff --git a/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/HID_Keyboard/Profile/scanparamservice.c b/EVT/EXAM/BLE/HID_Keyboard/Profile/scanparamservice.c
index e97a6b1..0db4870 100644
--- a/EVT/EXAM/BLE/HID_Keyboard/Profile/scanparamservice.c
+++ b/EVT/EXAM/BLE/HID_Keyboard/Profile/scanparamservice.c
@@ -280,7 +280,7 @@ void ScanParam_RefreshNotify(uint16_t connHandle)
if(noti.pValue != NULL)
{
// send notification
- noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_CCCD_IDX].handle;
+ noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_IDX].handle;
noti.len = SCAN_PARAM_REFRESH_LEN;
noti.pValue[0] = SCAN_PARAM_REFRESH_REQ;
diff --git a/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/HID_Mouse/Profile/scanparamservice.c b/EVT/EXAM/BLE/HID_Mouse/Profile/scanparamservice.c
index e97a6b1..0db4870 100644
--- a/EVT/EXAM/BLE/HID_Mouse/Profile/scanparamservice.c
+++ b/EVT/EXAM/BLE/HID_Mouse/Profile/scanparamservice.c
@@ -280,7 +280,7 @@ void ScanParam_RefreshNotify(uint16_t connHandle)
if(noti.pValue != NULL)
{
// send notification
- noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_CCCD_IDX].handle;
+ noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_IDX].handle;
noti.len = SCAN_PARAM_REFRESH_LEN;
noti.pValue[0] = SCAN_PARAM_REFRESH_REQ;
diff --git a/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/HID_Touch/Profile/scanparamservice.c b/EVT/EXAM/BLE/HID_Touch/Profile/scanparamservice.c
index e97a6b1..0db4870 100644
--- a/EVT/EXAM/BLE/HID_Touch/Profile/scanparamservice.c
+++ b/EVT/EXAM/BLE/HID_Touch/Profile/scanparamservice.c
@@ -280,7 +280,7 @@ void ScanParam_RefreshNotify(uint16_t connHandle)
if(noti.pValue != NULL)
{
// send notification
- noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_CCCD_IDX].handle;
+ noti.handle = scanParamAttrTbl[SCAN_PARAM_REFRESH_IDX].handle;
noti.len = SCAN_PARAM_REFRESH_LEN;
noti.pValue[0] = SCAN_PARAM_REFRESH_REQ;
diff --git a/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c b/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a b/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a
index 50817e9..8915140 100644
Binary files a/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a and b/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a differ
diff --git a/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a b/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a
index 6c003ef..5d20863 100644
Binary files a/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a and b/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a differ
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/include/app_mesh_config.h
index 7ed0127..499e87d 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/include/app_mesh_config.h
index 6c9e663..99d6672 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/include/app_mesh_config.h
index 6c9e663..99d6672 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/include/app_mesh_config.h
index 6c9e663..99d6672 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/include/app_mesh_config.h
index 6c9e663..99d6672 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_proxy/APP/include/app_mesh_config.h
index 8443ec8..0b31282 100644
--- a/EVT/EXAM/BLE/MESH/adv_proxy/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_proxy/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_vendor/APP/include/app_mesh_config.h
index 53b7f9d..ca20504 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_vendor/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/include/app_mesh_config.h
index 5ee0623..f135761 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/include/app_mesh_config.h
index a94045b..055fa9b 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/include/app_mesh_config.h
index 413f61c..a0dc67a 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/include/app_mesh_config.h
index 6ecbc8d..b3ab4e4 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/include/app_mesh_config.h
index 2d9cfef..985f9cf 100644
--- a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/include/app_mesh_config.h b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/include/app_mesh_config.h
index 2d9cfef..985f9cf 100644
--- a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/include/app_mesh_config.h
+++ b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/include/app_mesh_config.h
@@ -100,8 +100,8 @@ extern "C" {
// 允许同时存在的分包消息的最大发送个数
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
-#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
-#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
+#define CONFIG_MESH_TX_SEG_COUNT_DEF (1)
+#define CONFIG_MESH_TX_SEG_COUNT_MAX (1)
// 允许同时存在的分包消息的最大接收个数
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
diff --git a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MultiCentPeri/APP/multiCentral.c b/EVT/EXAM/BLE/MultiCentPeri/APP/multiCentral.c
index d869013..0ab4305 100644
--- a/EVT/EXAM/BLE/MultiCentPeri/APP/multiCentral.c
+++ b/EVT/EXAM/BLE/MultiCentPeri/APP/multiCentral.c
@@ -302,7 +302,7 @@ uint16_t Central_ProcessEvent(uint8_t task_id, uint16_t events)
{
uint8_t *pMsg;
- if((pMsg = tmos_msg_receive(centralTaskId)) != NULL)
+ if((pMsg = tmos_msg_receive(task_id)) != NULL)
{
central_ProcessTMOSMsg((tmos_event_hdr_t *)pMsg);
// Release the TMOS message
diff --git a/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/MultiCentral/APP/multiCentral.c b/EVT/EXAM/BLE/MultiCentral/APP/multiCentral.c
index a2d464c..0be5dec 100644
--- a/EVT/EXAM/BLE/MultiCentral/APP/multiCentral.c
+++ b/EVT/EXAM/BLE/MultiCentral/APP/multiCentral.c
@@ -34,7 +34,7 @@
* CONSTANTS
*/
// Maximum number of scan responses
-#define DEFAULT_MAX_SCAN_RES 10
+#define DEFAULT_MAX_SCAN_RES 80
// Scan duration in 0.625ms
#define DEFAULT_SCAN_DURATION 2400
@@ -122,8 +122,8 @@ enum
{
BLE_DISC_STATE_IDLE, // Idle
BLE_DISC_STATE_SVC, // Service discovery
- BLE_DISC_STATE_CHAR, // Characteristic discovery
- BLE_DISC_STATE_CCCD, // client characteristic configuration discovery
+ BLE_DISC_STATE_CHAR, // Characteristic discovery
+ BLE_DISC_STATE_CCCD // client characteristic configuration discovery
};
/*********************************************************************
* TYPEDEFS
@@ -305,7 +305,7 @@ uint16_t Central_ProcessEvent(uint8_t task_id, uint16_t events)
{
uint8_t *pMsg;
- if((pMsg = tmos_msg_receive(centralTaskId)) != NULL)
+ if((pMsg = tmos_msg_receive(task_id)) != NULL)
{
central_ProcessTMOSMsg((tmos_event_hdr_t *)pMsg);
// Release the TMOS message
@@ -547,7 +547,7 @@ static void centralProcessGATTMsg(gattMsgEvent_t *pMsg)
((pMsg->method == ATT_ERROR_RSP) &&
(pMsg->msg.errorRsp.reqOpcode == ATT_WRITE_REQ)))
{
- if(pMsg->method == ATT_ERROR_RSP == ATT_ERROR_RSP)
+ if(pMsg->method == ATT_ERROR_RSP)
{
uint8_t status = pMsg->msg.errorRsp.errCode;
diff --git a/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/PAwR_ADV/APP/include/adv.h b/EVT/EXAM/BLE/PAwR_ADV/APP/include/adv.h
index 68449c2..f6e1eb9 100644
--- a/EVT/EXAM/BLE/PAwR_ADV/APP/include/adv.h
+++ b/EVT/EXAM/BLE/PAwR_ADV/APP/include/adv.h
@@ -4,8 +4,10 @@
* Version : V1.0
* Date : 2018/11/12
* Description : 观察应用主函数及任务系统初始化
+ *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef CENTRAL_H
diff --git a/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c b/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/PAwR_RSP/APP/include/rsp.h b/EVT/EXAM/BLE/PAwR_RSP/APP/include/rsp.h
index b4c86f3..404fca6 100644
--- a/EVT/EXAM/BLE/PAwR_RSP/APP/include/rsp.h
+++ b/EVT/EXAM/BLE/PAwR_RSP/APP/include/rsp.h
@@ -4,8 +4,10 @@
* Version : V1.0
* Date : 2018/12/11
* Description :
+ *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * SPDX-License-Identifier: Apache-2.0
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef PERIPHERAL_H
diff --git a/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c
index f073ad1..7d52294 100644
--- a/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c b/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c
index d226b03..0d013a0 100644
--- a/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/BLE/娌佹亽浣庡姛鑰楄摑鐗欒蒋浠跺紑鍙戝弬鑰冩墜鍐.PDF b/EVT/EXAM/BLE/娌佹亽浣庡姛鑰楄摑鐗欒蒋浠跺紑鍙戝弬鑰冩墜鍐.PDF
index c5721b3..660aeca 100644
Binary files a/EVT/EXAM/BLE/娌佹亽浣庡姛鑰楄摑鐗欒蒋浠跺紑鍙戝弬鑰冩墜鍐.PDF and b/EVT/EXAM/BLE/娌佹亽浣庡姛鑰楄摑鐗欒蒋浠跺紑鍙戝弬鑰冩墜鍐.PDF differ
diff --git a/EVT/EXAM/BLE/钃濈墮鑺墖鐨勭數璺強PCB璁捐鐨勯噸瑕佹敞鎰忎簨椤.pdf b/EVT/EXAM/BLE/钃濈墮鑺墖鐨勭數璺強PCB璁捐鐨勯噸瑕佹敞鎰忎簨椤.pdf
index 8c9e367..6d0279b 100644
Binary files a/EVT/EXAM/BLE/钃濈墮鑺墖鐨勭數璺強PCB璁捐鐨勯噸瑕佹敞鎰忎簨椤.pdf and b/EVT/EXAM/BLE/钃濈墮鑺墖鐨勭數璺強PCB璁捐鐨勯噸瑕佹敞鎰忎簨椤.pdf differ
diff --git a/EVT/EXAM/CAN/Networking/.template b/EVT/EXAM/CAN/Networking/.template
index 2190c5e..3be9c57 100644
--- a/EVT/EXAM/CAN/Networking/.template
+++ b/EVT/EXAM/CAN/Networking/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/CAN/Networking/User/main.c b/EVT/EXAM/CAN/Networking/User/main.c
index 479495c..2e3d50d 100644
--- a/EVT/EXAM/CAN/Networking/User/main.c
+++ b/EVT/EXAM/CAN/Networking/User/main.c
@@ -102,7 +102,7 @@ void CAN_Mode_Init(u8 tsjw, u8 tbs2, u8 tbs1, u16 brp, u8 mode)
CAN_FilterInitSturcture.CAN_FilterMaskIdHigh = 0xFFE0;
CAN_FilterInitSturcture.CAN_FilterMaskIdLow = 0x0006;
- /* identifier/mask mode, Two 16-bit filters, StdId: 0x317锟斤拷0x316 */
+ /* identifier/mask mode, Two 16-bit filters, StdId: 0x317,0x316 */
// CAN_FilterInitSturcture.CAN_FilterMode = CAN_FilterMode_IdMask;
// CAN_FilterInitSturcture.CAN_FilterScale = CAN_FilterScale_16bit;
// CAN_FilterInitSturcture.CAN_FilterIdHigh = 0x62E0;
@@ -110,7 +110,7 @@ void CAN_Mode_Init(u8 tsjw, u8 tbs2, u8 tbs1, u16 brp, u8 mode)
// CAN_FilterInitSturcture.CAN_FilterMaskIdHigh = 0x62C0;
// CAN_FilterInitSturcture.CAN_FilterMaskIdLow = 0xFFF8;
- /* identifier list mode, One 32-bit filter, StdId: 0x317锟斤拷0x316 */
+ /* identifier list mode, One 32-bit filter, StdId: 0xC5C0000,0xC580000 */
// CAN_FilterInitSturcture.CAN_FilterMode = CAN_FilterMode_IdList;
// CAN_FilterInitSturcture.CAN_FilterScale = CAN_FilterScale_32bit;
// CAN_FilterInitSturcture.CAN_FilterIdHigh = 0x62E0;
diff --git a/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c b/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c
+++ b/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/CAN/TestMode/.template b/EVT/EXAM/CAN/TestMode/.template
index 8572c10..dc327ef 100644
--- a/EVT/EXAM/CAN/TestMode/.template
+++ b/EVT/EXAM/CAN/TestMode/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c b/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c
+++ b/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/CAN/Time-triggered/.template b/EVT/EXAM/CAN/Time-triggered/.template
index ef692cc..7b67063 100644
--- a/EVT/EXAM/CAN/Time-triggered/.template
+++ b/EVT/EXAM/CAN/Time-triggered/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/CAN/Time-triggered/User/main.c b/EVT/EXAM/CAN/Time-triggered/User/main.c
index d2ba43c..1b7f373 100644
--- a/EVT/EXAM/CAN/Time-triggered/User/main.c
+++ b/EVT/EXAM/CAN/Time-triggered/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2023/12/29
+ * Version : V1.0.1
+ * Date : 2025/10/27
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -31,7 +31,7 @@
/* Global Variable */
u8 txbuf[8];
-u8 tx;
+vu8 tx;
/*********************************************************************
* @fn CAN_Mode_Init
diff --git a/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c b/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c
+++ b/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/CRC/CRC_Calculation/.template b/EVT/EXAM/CRC/CRC_Calculation/.template
index 429ba68..e914195 100644
--- a/EVT/EXAM/CRC/CRC_Calculation/.template
+++ b/EVT/EXAM/CRC/CRC_Calculation/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/CRC/CRC_Calculation/User/main.c b/EVT/EXAM/CRC/CRC_Calculation/User/main.c
index da449e0..55d7f33 100644
--- a/EVT/EXAM/CRC/CRC_Calculation/User/main.c
+++ b/EVT/EXAM/CRC/CRC_Calculation/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
-* Version : V1.0.0
-* Date : 2024/02/21
+* Version : V1.0.1
+* Date : 2025/10/27
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -32,7 +32,7 @@ u32 SRC_BUF[Buf_Size] = {0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10,
0x61626364, 0x65666768, 0x696A6B6C, 0x6D6E6F70,
0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80};
-u32 CRCValue = 0;
+vu32 CRCValue = 0;
/*********************************************************************
* @fn main
*
diff --git a/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c b/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c
+++ b/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/.template b/EVT/EXAM/DMA/DMA_MEM2MEM/.template
index 5cfc054..17b5c6e 100644
--- a/EVT/EXAM/DMA/DMA_MEM2MEM/.template
+++ b/EVT/EXAM/DMA/DMA_MEM2MEM/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/User/main.c b/EVT/EXAM/DMA/DMA_MEM2MEM/User/main.c
index 81d89f5..86fa39d 100644
--- a/EVT/EXAM/DMA/DMA_MEM2MEM/User/main.c
+++ b/EVT/EXAM/DMA/DMA_MEM2MEM/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2023/12/29
+ * Version : V1.0.1
+ * Date : 2025/10/28
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -33,7 +33,7 @@ u32 SRC_BUF[Buf_Size] = {0x01020304, 0x05060708, 0x090A0B0C, 0x0D0E0F10,
0x71727374, 0x75767778, 0x797A7B7C, 0x7D7E7F80};
u32 DST_BUF[Buf_Size] = {0};
-u8 Flag = 0;
+vu8 Flag = 0;
/*********************************************************************
* @fn BufCmp
*
diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c b/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c
+++ b/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/DHCP/.template b/EVT/EXAM/ETH/DHCP/.template
index 87bc7b6..7f91794 100644
--- a/EVT/EXAM/ETH/DHCP/.template
+++ b/EVT/EXAM/ETH/DHCP/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/DHCP.hex
diff --git a/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c b/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/DNS/.template b/EVT/EXAM/ETH/DNS/.template
index 3b5fd1d..3ef5a4d 100644
--- a/EVT/EXAM/ETH/DNS/.template
+++ b/EVT/EXAM/ETH/DNS/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/DNS.hex
diff --git a/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c b/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/ETH_CFG/.template b/EVT/EXAM/ETH/ETH_CFG/.template
index a65c17f..959c8b5 100644
--- a/EVT/EXAM/ETH/ETH_CFG/.template
+++ b/EVT/EXAM/ETH/ETH_CFG/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/ETH_CFG.hex
diff --git a/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/ETH_IAP/.template b/EVT/EXAM/ETH/ETH_IAP/.template
index c7ca530..dba9f58 100644
--- a/EVT/EXAM/ETH/ETH_IAP/.template
+++ b/EVT/EXAM/ETH/ETH_IAP/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/ETH_IAP.hex
diff --git a/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/ETH_UART/.template b/EVT/EXAM/ETH/ETH_UART/.template
index 1dfb8e9..b6f628d 100644
--- a/EVT/EXAM/ETH/ETH_UART/.template
+++ b/EVT/EXAM/ETH/ETH_UART/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/ETH_UART.hex
diff --git a/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/IPRaw_PING/.template b/EVT/EXAM/ETH/IPRaw_PING/.template
index 676c0fb..5c146a5 100644
--- a/EVT/EXAM/ETH/IPRaw_PING/.template
+++ b/EVT/EXAM/ETH/IPRaw_PING/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/IPRaw_PING.hex
diff --git a/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c b/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/MAC_RAW/.template b/EVT/EXAM/ETH/MAC_RAW/.template
index 6b9e719..68ee1f8 100644
--- a/EVT/EXAM/ETH/MAC_RAW/.template
+++ b/EVT/EXAM/ETH/MAC_RAW/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/MAC_RAW.hex
\ No newline at end of file
diff --git a/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c b/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
index 4ba5656..a0d0446 100644
--- a/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
+++ b/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
@@ -488,10 +488,13 @@ void ETH_Configuration( uint8_t *macAddr )
uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len)
{
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
- if( DMATxDescToSet->Status & ETH_DMATxDesc_OWN )
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN))
{
- /* Return ERROR: OWN bit set */
- return ETH_ERROR;
+ if((R8_ETH_ECON1 & RB_ETH_ECON1_TXRTS) == 0)
+ {
+ DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
+ }
+ else return ETH_ERROR;
}
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
R16_ETH_ETXLN = len;
diff --git a/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c b/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/MQTT/.template b/EVT/EXAM/ETH/MQTT/.template
index bb07cb6..d734a9e 100644
--- a/EVT/EXAM/ETH/MQTT/.template
+++ b/EVT/EXAM/ETH/MQTT/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/MQTT.hex
diff --git a/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c b/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/Mail/.template b/EVT/EXAM/ETH/Mail/.template
index 1e217f5..108352b 100644
--- a/EVT/EXAM/ETH/Mail/.template
+++ b/EVT/EXAM/ETH/Mail/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/Mail.hex
diff --git a/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c b/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/NetLib/eth_driver.c b/EVT/EXAM/ETH/NetLib/eth_driver.c
index a348558..50bee7a 100644
--- a/EVT/EXAM/ETH/NetLib/eth_driver.c
+++ b/EVT/EXAM/ETH/NetLib/eth_driver.c
@@ -535,10 +535,13 @@ void ETH_Configuration( uint8_t *macAddr )
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
{
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
- if( DMATxDescToSet->Status & ETH_DMATxDesc_OWN )
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN))
{
- /* Return ERROR: OWN bit set */
- return ETH_ERROR;
+ if((R8_ETH_ECON1 & RB_ETH_ECON1_TXRTS) == 0)
+ {
+ DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
+ }
+ else return ETH_ERROR;
}
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
R16_ETH_ETXLN = len;
diff --git a/EVT/EXAM/ETH/NetLib/libwchnet.a b/EVT/EXAM/ETH/NetLib/libwchnet.a
index 1a77f93..8fa4baa 100644
Binary files a/EVT/EXAM/ETH/NetLib/libwchnet.a and b/EVT/EXAM/ETH/NetLib/libwchnet.a differ
diff --git a/EVT/EXAM/ETH/NetLib/wchnet.h b/EVT/EXAM/ETH/NetLib/wchnet.h
index f1c124c..820144b 100644
--- a/EVT/EXAM/ETH/NetLib/wchnet.h
+++ b/EVT/EXAM/ETH/NetLib/wchnet.h
@@ -21,7 +21,7 @@
extern "C" {
#endif
-#define WCHNET_LIB_VER 0x1A //the library version number
+#define WCHNET_LIB_VER 0x1B //the library version number
#define WCHNET_CFG_VALID 0x12345678 //Configuration value valid flag
/* LED state @LED_STAT */
@@ -167,6 +167,8 @@ typedef uint8_t (*dhcp_callback)( uint8_t status, void * );
struct _SOCK_INF;
typedef void (*pSockRecv)( struct _SOCK_INF *, uint32_t, uint16_t, uint8_t *, uint32_t);
+typedef uint8_t (*pTcpVerifyConnection)(uint32_t src_ip, uint16_t src_port, uint16_t dest_port);
+
/* Socket information struct */
typedef struct _SOCK_INF
{
@@ -579,6 +581,20 @@ uint8_t WCHNET_HostNameGetIp( const char *hostname, uint8_t *addr, dns_callback
*/
void WCHNET_ConfigKeepLive( struct _KEEP_CFG *cfg );
+/**
+ * @brief Configure ARP retransmission parameters.
+ *
+ * @param retry_period - ARP retransmission period, the default value is 10, the unit is 100ms
+ * retry_cnt - The number of ARP retransmissions, the default value is 3.
+ * When the value of the retry_cnt is 0xff, it will be retried
+ * until the MAC address of the device is obtained.
+ * Arp_Entry_timeout_s - the time an ARP entry stays valid after its last update.
+ * the default value is 300, the unit is 1s
+ *
+ * @return None
+ */
+void WCHNET_ARPRetryCfg(uint8_t retry_period, uint8_t retry_cnt, uint16_t Arp_Entry_timeout_s);
+
/**
* @brief Configure socket KEEP LIVE enable.
*
@@ -598,6 +614,15 @@ uint8_t WCHNET_SocketSetKeepLive( uint8_t socketid, uint8_t enable );
*/
void WCHNET_PhyStatus( uint32_t phy_stat );
+/**
+ * @brief Configure socket Nagle Func.
+ *
+ * @param socketid - socket id value
+ * @param enable - 1: Enabled. 0: Disabled.
+ *
+ * @return @ERR_T
+ */
+uint8_t WCHNET_SocketSetNagle( uint8_t socketid, uint8_t enable );
#ifdef __cplusplus
}
diff --git a/EVT/EXAM/ETH/TcpClient/.template b/EVT/EXAM/ETH/TcpClient/.template
index 2653296..2d2007f 100644
--- a/EVT/EXAM/ETH/TcpClient/.template
+++ b/EVT/EXAM/ETH/TcpClient/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/TCPClient.hex
\ No newline at end of file
diff --git a/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c b/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/TcpServer/.template b/EVT/EXAM/ETH/TcpServer/.template
index 94ee701..6d911c0 100644
--- a/EVT/EXAM/ETH/TcpServer/.template
+++ b/EVT/EXAM/ETH/TcpServer/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/TCPServer.hex
\ No newline at end of file
diff --git a/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/UdpClient/.template b/EVT/EXAM/ETH/UdpClient/.template
index 98da110..0dacbe8 100644
--- a/EVT/EXAM/ETH/UdpClient/.template
+++ b/EVT/EXAM/ETH/UdpClient/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/UDPClient.hex
\ No newline at end of file
diff --git a/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c b/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/UdpServer/.template b/EVT/EXAM/ETH/UdpServer/.template
index 9451f2e..f260fcc 100644
--- a/EVT/EXAM/ETH/UdpServer/.template
+++ b/EVT/EXAM/ETH/UdpServer/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/UDPServer.hex
\ No newline at end of file
diff --git a/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/ETH/WebServer/.template b/EVT/EXAM/ETH/WebServer/.template
index 6db9e8a..4e91393 100644
--- a/EVT/EXAM/ETH/WebServer/.template
+++ b/EVT/EXAM/ETH/WebServer/.template
@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
Target Path=obj/WebServer.hex
diff --git a/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
index 6405f25..ce40a45 100644
--- a/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/EXTI/EXTI0/.template b/EVT/EXAM/EXTI/EXTI0/.template
index c856516..b247034 100644
--- a/EVT/EXAM/EXTI/EXTI0/.template
+++ b/EVT/EXAM/EXTI/EXTI0/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c b/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c
+++ b/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/FLASH/FLASH_Program/.template b/EVT/EXAM/FLASH/FLASH_Program/.template
index c952057..10074e3 100644
--- a/EVT/EXAM/FLASH/FLASH_Program/.template
+++ b/EVT/EXAM/FLASH/FLASH_Program/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/FLASH/FLASH_Program/User/main.c b/EVT/EXAM/FLASH/FLASH_Program/User/main.c
index 6a2109c..f2beb25 100644
--- a/EVT/EXAM/FLASH/FLASH_Program/User/main.c
+++ b/EVT/EXAM/FLASH/FLASH_Program/User/main.c
@@ -49,7 +49,7 @@ typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
#define FAST_FLASH_SIZE (64*1024)
/* Global Variable */
-uint32_t EraseCounter = 0x0, Address = 0x0;
+volatile uint32_t EraseCounter = 0x0, Address = 0x0;
uint16_t Data = 0xAAAA;
uint32_t WRPR_Value = 0xFFFFFFFF, ProtectedPages = 0x0;
uint32_t NbrOfPage;
diff --git a/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c b/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c
+++ b/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.template b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.template
index ce6b101..94ddb53 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.template
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.template
@@ -13,5 +13,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
CLKSpeed=1
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S
index aaa76c5..a571384 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D6.s
;* Author : WCH
-;* Version : V1.0.1
-;* Date : 2024/01/31
-;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
-;* vector table for eclipse toolchain.
+;* Version : V1.0.2
+;* Date : 2025/10/21
+;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
+;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -208,9 +208,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
-1:
+
la sp, _eusrstack
-2:
+
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S
index 514a10a..194ec7d 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8.s
;* Author : WCH
-;* Version : V1.0.1
-;* Date : 2024/01/31
+;* Version : V1.0.2
+;* Date : 2025/10/21
;* Description : CH32V203RB
-;* vector table for eclipse toolchain.
+;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -225,9 +225,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
-1:
+
la sp, _eusrstack
-2:
+
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S
index c31123a..2443e77 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8W.s
;* Author : WCH
-;* Version : V1.0.1
-;* Date : 2023/11/20
+;* Version : V1.0.2
+;* Date : 2025/10/21
;* Description : CH32V208x
-;* vector table for eclipse toolchain.
+;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -229,9 +229,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
-1:
+
la sp, _eusrstack
-2:
+
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/GPIO/GPIO_Toggle/.template b/EVT/EXAM/GPIO/GPIO_Toggle/.template
index 4e5ff9b..5d640f7 100644
--- a/EVT/EXAM/GPIO/GPIO_Toggle/.template
+++ b/EVT/EXAM/GPIO/GPIO_Toggle/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c b/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c
+++ b/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/.template b/EVT/EXAM/HarmonyOS/LiteOS_m/.template
index ab74393..4730a08 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/.template
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/components/cpup/los_cpup.c b/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/components/cpup/los_cpup.c
index 0316cf2..928797f 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/components/cpup/los_cpup.c
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/components/cpup/los_cpup.c
@@ -100,6 +100,7 @@ LITE_OS_SEC_TEXT_MINOR VOID OsTskCycleStart(VOID)
return;
}
+
/*****************************************************************************
Function : OsTskCycleEnd
Description: quit task and get cycle count
@@ -132,6 +133,7 @@ LITE_OS_SEC_TEXT_MINOR VOID OsTskCycleEnd(VOID)
return;
}
+
/*****************************************************************************
Function : OsTskCycleEndStart
Description: start task to get cycles count in current task ending
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/kernel/arch/risc-v/V4A/gcc/los_exc.S b/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/kernel/arch/risc-v/V4A/gcc/los_exc.S
index bf6712a..e30b1fb 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/kernel/arch/risc-v/V4A/gcc/los_exc.S
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/LiteOS/kernel/arch/risc-v/V4A/gcc/los_exc.S
@@ -56,7 +56,7 @@
*/
/* Save caller registers */
.macro SAVE_CONTEXT
- csrrw sp, CSR_MSCRATCH, sp /* 把中断栈给sp,并把线程栈存到mscratch */
+ csrrw sp, CSR_MSCRATCH, sp
/* Allocate stack space for context saving */
#ifndef __riscv_32e
addi sp, sp, -20*REGBYTES
@@ -120,7 +120,7 @@
/* De-allocate the stack space */
addi sp, sp, 14*REGBYTES
#endif /* __riscv_32e */
- csrrw sp, CSR_MSCRATCH, sp /* 退出后把线程栈给sp,把中断栈存入mscratch */
+ csrrw sp, CSR_MSCRATCH, sp
.endm
@@ -155,7 +155,7 @@ irq_entry:
/* Critical section with interrupts disabled */
DISABLE_MIE
/*************************/
- /* jal irq_handler */ /* 跳转到中断处理函数 */
+ /* jal irq_handler */
/*************************/
la t0, g_intCount
lw t1, 0(t0)
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S
index aaa76c5..a571384 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D6.s
;* Author : WCH
-;* Version : V1.0.1
-;* Date : 2024/01/31
-;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
-;* vector table for eclipse toolchain.
+;* Version : V1.0.2
+;* Date : 2025/10/21
+;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
+;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -208,9 +208,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
-1:
+
la sp, _eusrstack
-2:
+
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S
index 514a10a..194ec7d 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8.s
;* Author : WCH
-;* Version : V1.0.1
-;* Date : 2024/01/31
+;* Version : V1.0.2
+;* Date : 2025/10/21
;* Description : CH32V203RB
-;* vector table for eclipse toolchain.
+;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -225,9 +225,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
-1:
+
la sp, _eusrstack
-2:
+
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S
index c31123a..2443e77 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8W.s
;* Author : WCH
-;* Version : V1.0.1
-;* Date : 2023/11/20
+;* Version : V1.0.2
+;* Date : 2025/10/21
;* Description : CH32V208x
-;* vector table for eclipse toolchain.
+;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -229,9 +229,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
-1:
+
la sp, _eusrstack
-2:
+
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/User/main.c b/EVT/EXAM/HarmonyOS/LiteOS_m/User/main.c
index 7f2382b..66475a3 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/User/main.c
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/User/main.c
@@ -185,11 +185,18 @@ LITE_OS_SEC_TEXT_INIT int main(void)
void EXTI0_IRQHandler(void) __attribute__((interrupt()));
void EXTI0_IRQHandler(void)
{
- /* 中断栈使用的是原来调用main设置的值，将中断栈和线程栈分开，这样线程跳中断，中断函数如果嵌套深度较大，不至于
- * 线程栈被压满溢出，但是采用当前方式，线程进中断时，编译器保存到的16个caller寄存器任然压入线程栈，如果需要希
- * 望caller寄存器压入中断栈，则中断函数的入口和出口需要使用汇编，中间调用用户中断处理函数即可，详见los_exc.S
- * 中的ipq_entry例子
- * */
+ /*
+ *The interrupt stack uses the value originally set when calling main,
+ *separating the interrupt stack from the thread stack. In this way,
+ *if the interrupt function is nested to a large depth, the thread
+ *stack will not be overloaded and overflow. However, in the current way,
+ *when the thread enters the interrupt, the 16 caller registers saved by
+ *the compiler are still pushed onto the thread stack.If you want the caller
+ *register to be pushed onto the interrupt stack, the entry and exit of the
+ *interrupt function need to use assembly language, and the user interrupt
+ *handling function can be called in the middle. For details,
+ *see the ipq_entry example in los_exc.S
+ * */
GET_INT_SP();
HalIntEnter();
if(EXTI_GetITStatus(EXTI_Line0)!=RESET)
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c b/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c
index a71dec8..d9ef769 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/I2C/I2C_10bit_Mode/.template b/EVT/EXAM/I2C/I2C_10bit_Mode/.template
index bd86d90..658c026 100644
--- a/EVT/EXAM/I2C/I2C_10bit_Mode/.template
+++ b/EVT/EXAM/I2C/I2C_10bit_Mode/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/I2C/I2C_10bit_Mode/User/main.c b/EVT/EXAM/I2C/I2C_10bit_Mode/User/main.c
index a7a91c2..6b150f2 100644
--- a/EVT/EXAM/I2C/I2C_10bit_Mode/User/main.c
+++ b/EVT/EXAM/I2C/I2C_10bit_Mode/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2021/06/06
+ * Version : V1.0.1
+ * Date : 2025/10/27
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -144,7 +144,8 @@ int main(void)
i++;
}
}
- I2C1->CTLR1 &= I2C1->CTLR1;
+ while(I2C_GetFlagStatus(I2C1,I2C_FLAG_STOPF)==RESET);
+ I2C1->CTLR1 &= I2C1->CTLR1;
}
printf( "RxData:\r\n" );
diff --git a/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template
index d207ca4..d13a02f 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template
@@ -13,5 +13,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
CLKSpeed=1
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c
index d6232a2..8a653de 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c
@@ -165,9 +165,6 @@ int main(void)
}
-
-
-
#elif (I2C_MODE == SLAVE_MODE)
printf("IIC Slave mode\r\n");
IIC_Init( 80000, RXAdderss);
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/I2C/I2C_7bit_Mode/.template b/EVT/EXAM/I2C/I2C_7bit_Mode/.template
index 7e662a6..b753730 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Mode/.template
+++ b/EVT/EXAM/I2C/I2C_7bit_Mode/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/I2C/I2C_7bit_Mode/User/main.c b/EVT/EXAM/I2C/I2C_7bit_Mode/User/main.c
index b511469..d0a08f0 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Mode/User/main.c
+++ b/EVT/EXAM/I2C/I2C_7bit_Mode/User/main.c
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
- * Version : V1.0.0
- * Date : 2021/06/06
+ * Version : V1.0.1
+ * Date : 2025/10/27
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -142,7 +142,8 @@ int main(void)
i++;
}
}
- I2C1->CTLR1 &= I2C1->CTLR1;
+ while(I2C_GetFlagStatus(I2C1,I2C_FLAG_STOPF)==RESET);
+ I2C1->CTLR1 &= I2C1->CTLR1;
}
printf( "RxData:\r\n" );
for(p=0; p<5; p++)
diff --git a/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/I2C/I2C_DMA/.template b/EVT/EXAM/I2C/I2C_DMA/.template
index db3bc4a..43b3e97 100644
--- a/EVT/EXAM/I2C/I2C_DMA/.template
+++ b/EVT/EXAM/I2C/I2C_DMA/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/I2C/I2C_DMA/User/main.c b/EVT/EXAM/I2C/I2C_DMA/User/main.c
index ae3e50d..541ab75 100644
--- a/EVT/EXAM/I2C/I2C_DMA/User/main.c
+++ b/EVT/EXAM/I2C/I2C_DMA/User/main.c
@@ -212,6 +212,9 @@ int main(void)
DMA_Cmd( DMA1_Channel7, ENABLE );
while( ( !DMA_GetFlagStatus( DMA1_FLAG_TC7 ) ) );
+
+ while(I2C_GetFlagStatus(I2C1,I2C_FLAG_STOPF)==RESET);
+ I2C1->CTLR1 &= I2C1->CTLR1;
printf( "RxData:\r\n" );
diff --git a/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/I2C/I2C_EEPROM/.template b/EVT/EXAM/I2C/I2C_EEPROM/.template
index 8d08dd4..6272b01 100644
--- a/EVT/EXAM/I2C/I2C_EEPROM/.template
+++ b/EVT/EXAM/I2C/I2C_EEPROM/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/I2C/I2C_PEC/.template b/EVT/EXAM/I2C/I2C_PEC/.template
index 91b55d8..bab3013 100644
--- a/EVT/EXAM/I2C/I2C_PEC/.template
+++ b/EVT/EXAM/I2C/I2C_PEC/.template
@@ -13,4 +13,4 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
-MCU=CH32V203RBT6
+MCU=CH32V203RBT
diff --git a/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c
index 7ffbdb4..7facd53 100644
--- a/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
- * For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ * For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/.cproject b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/.cproject
index 476de5d..26d952f 100644
--- a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/.cproject
+++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/.cproject
@@ -14,7 +14,7 @@
-
+
@@ -46,7 +46,7 @@
-
+