bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
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EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
+2 -2
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@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/MAC_RAW/.cproject
-1
View File
@@ -235,5 +235,4 @@
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>
EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
+106 -74
View File
@@ -114,7 +114,7 @@ void WCHNET_LinkProcess( void )
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
phy_bmsr = ReadPHYReg(PHY_BMSR);
if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) )
if(phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD)
{
if( !(phyLinkStatus&PHY_LINK_WAIT_SUC) )
{
@@ -145,7 +145,7 @@ void WCHNET_LinkProcess( void )
}
}
else{
if((phySucCnt++ == 5) && ((phy_bmsr&(1<<5)) == 0))
if((phySucCnt++ == 5) && ((phy_bmsr&PHY_AutoNego_Complete) == 0))
{
phySucCnt = 0;
phyRetryCnt = 0;
@@ -167,56 +167,64 @@ void WCHNET_LinkProcess( void )
}
else
{
if( phyLinkStatus == PHY_LINK_WAIT_SUC )
if(phy_bmsr & PHY_AutoNego_Complete)
{
if(phyLinkCnt++ == 10)
{
phyLinkCnt = 0;
phyRetryCnt = 0;
phyPNChangeCnt = 0;
phyLinkStatus = PHY_LINK_INIT;
}
phySucCnt = 0;
phyLinkCnt = 0;
phyLinkStatus = PHY_LINK_WAIT_SUC;
}
else if(phyLinkStatus == PHY_LINK_INIT)
{
if(phyPNChangeCnt++ == 10)
else {
if( phyLinkStatus == PHY_LINK_WAIT_SUC )
{
phyPNChangeCnt = 0;
phyPN = ReadPHYReg(PHY_MDIX);
phyPN &= ~0x0c;
phyPN ^= 0x03;
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
}
else {
phyPN &= ~PHY_PN_SWITCH_N;
}
WritePHYReg(PHY_MDIX, phyPN);
}
}
else if(phyLinkStatus == PHY_LINK_SUC_N)
{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
phy_bmcr = ReadPHYReg(PHY_BMCR);
phy_bmcr |= 1<<9;
WritePHYReg(PHY_BMCR, phy_bmcr);
Delay_Us(10);
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if(phyRetryCnt++ == 15)
if(phyLinkCnt++ == 10)
{
phyLinkCnt = 0;
phyRetryCnt = 0;
phyPNChangeCnt = 0;
phyLinkStatus = PHY_LINK_INIT;
}
}
else if(phyLinkStatus == PHY_LINK_INIT)
{
if(phyPNChangeCnt++ == 10)
{
phyPNChangeCnt = 0;
phyPN = ReadPHYReg(PHY_MDIX);
phyPN &= ~0x0c;
phyPN ^= 0x03;
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
}
else {
phyPN &= ~PHY_PN_SWITCH_N;
}
WritePHYReg(PHY_MDIX, phyPN);
}
}
else if(phyLinkStatus == PHY_LINK_SUC_N)
{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
phy_bmcr = ReadPHYReg(PHY_BMCR);
phy_bmcr |= 1<<9;
WritePHYReg(PHY_BMCR, phy_bmcr);
Delay_Us(10);
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if(phyRetryCnt++ == 15)
{
phyRetryCnt = 0;
phyPNChangeCnt = 0;
phyLinkStatus = PHY_LINK_INIT;
}
}
}
}
}
}
@@ -459,6 +467,7 @@ void ETH_Configuration( uint8_t *macAddr )
R8_ETH_MACON2 |= PADCFG_AUTO_3; //All short packets are automatically padded to 60 bytes
R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN; //Hardware padded CRC
R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN; //Jumbo frames are not received
R8_ETH_MACON2 |= RB_ETH_MACON2_FULDPX;
R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
R8_ETH_ECON2 &= ~(0x07 << 1);
R8_ETH_ECON2 |= 5 << 1;
@@ -496,6 +505,44 @@ uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len)
return ETH_SUCCESS;
}
/*********************************************************************
* @fn ETH_LinkUpCfg
*
* @brief When the PHY is connected, configure the relevant functions.
*
* @param regval BMSR register value
*
* @return none.
*/
void ETH_LinkUpCfg(uint16_t regval)
{
LinkSta = 1;
/* Receive CRC error packets */
R8_ETH_ERXFCON |= RB_ETH_ERXFCON_CRCEN;
CRCErrPktCnt = 0;
PhyPolarityDetect = 1;
phyLinkTime = LocalTime;
phyStatus = PHY_Linked_Status;
ETH_Start( );
}
/*********************************************************************
* @fn ETH_LinkDownCfg
*
* @brief When the PHY is disconnected, configure the relevant functions.
*
* @param regval BMSR register value
*
* @return none.
*/
void ETH_LinkDownCfg(uint16_t regval)
{
LinkSta = 0;
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
phyLinkReset = 1;
phyLinkTime = LocalTime;
}
/*********************************************************************
* @fn ETH_PHYLink
*
@@ -505,44 +552,30 @@ uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len)
*/
void ETH_PHYLink( void )
{
uint32_t phy_stat, phy_anlpar;
u16 phy_bsr, phy_anlpar;
phy_bsr = ReadPHYReg(PHY_BMSR);
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
phy_stat = ReadPHYReg(PHY_BMSR); //Read PHY Status Register
if((phy_stat&(PHY_Linked_Status))&&(phy_anlpar == 0)){ //restart negotiation
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
phyLinkReset = 1;
phyLinkTime = LocalTime;
return;
}
if( (phy_stat&(PHY_Linked_Status)) && (phy_stat&PHY_AutoNego_Complete) )
if(phy_bsr & PHY_Linked_Status) //Valid link established
{
printf("Link Suc\r\n");
if( phy_anlpar&(1<<6) )
if(phy_bsr & PHY_AutoNego_Complete) //Auto-negotiation completed -- LinkUp
{
R8_ETH_MACON2 |= RB_ETH_MACON2_FULDPX;
ETH_LinkUpCfg(phy_bsr);
}
else
{
R8_ETH_MACON2 &= ~RB_ETH_MACON2_FULDPX;
else {
if(phy_anlpar == 0) //The auto-negotiation signal of the peer device is not obtained
{
WritePHYReg(PHY_BMCR, PHY_Reset);
PHY_NEGOTIATION_PARAM_INIT();
}
else {
ETH_LinkDownCfg(phy_bsr);
}
}
/* Receive CRC error packets */
R8_ETH_ERXFCON |= RB_ETH_ERXFCON_CRCEN;
CRCErrPktCnt = 0;
PhyPolarityDetect = 1;
phyLinkTime = LocalTime;
phyStatus = PHY_Linked_Status;
ETH_Start( );
LinkSta = 1;
}
else
{
LinkSta = 0;
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
phyLinkReset = 1;
phyLinkTime = LocalTime;
else { //LinkDown
ETH_LinkDownCfg(phy_bsr);
}
}
@@ -577,7 +610,6 @@ void WCHNET_ETHIsr( void )
DMARxDescToGet->Status |= (ETH_DMARxDesc_FS|ETH_DMARxDesc_LS);
DMARxDescToGet->Status &= ~ETH_DMARxDesc_FL;
DMARxDescToGet->Status |= ((R16_ETH_ERXLN+4)<<ETH_DMARxDesc_FrameLengthShift);
/* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
/* Selects the next DMA Rx descriptor list for next buffer to read */
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/NetLib/eth_driver.c
+106 -71
View File
@@ -135,7 +135,7 @@ void WCHNET_LinkProcess( void )
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
phy_bmsr = ReadPHYReg(PHY_BMSR);
if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) )
if(phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD)
{
if( !(phyLinkStatus&PHY_LINK_WAIT_SUC) )
{
@@ -166,7 +166,7 @@ void WCHNET_LinkProcess( void )
}
}
else{
if((phySucCnt++ == 5) && ((phy_bmsr&(1<<5)) == 0))
if((phySucCnt++ == 5) && ((phy_bmsr&PHY_AutoNego_Complete) == 0))
{
phySucCnt = 0;
phyRetryCnt = 0;
@@ -188,56 +188,64 @@ void WCHNET_LinkProcess( void )
}
else
{
if( phyLinkStatus == PHY_LINK_WAIT_SUC )
if(phy_bmsr & PHY_AutoNego_Complete)
{
if(phyLinkCnt++ == 10)
{
phyLinkCnt = 0;
phyRetryCnt = 0;
phyPNChangeCnt = 0;
phyLinkStatus = PHY_LINK_INIT;
}
phySucCnt = 0;
phyLinkCnt = 0;
phyLinkStatus = PHY_LINK_WAIT_SUC;
}
else if(phyLinkStatus == PHY_LINK_INIT)
{
if(phyPNChangeCnt++ == 10)
else {
if( phyLinkStatus == PHY_LINK_WAIT_SUC )
{
phyPNChangeCnt = 0;
phyPN = ReadPHYReg(PHY_MDIX);
phyPN &= ~0x0c;
phyPN ^= 0x03;
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
}
else {
phyPN &= ~PHY_PN_SWITCH_N;
}
WritePHYReg(PHY_MDIX, phyPN);
}
}
else if(phyLinkStatus == PHY_LINK_SUC_N)
{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
phy_bmcr = ReadPHYReg(PHY_BMCR);
phy_bmcr |= 1<<9;
WritePHYReg(PHY_BMCR, phy_bmcr);
Delay_Us(10);
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if(phyRetryCnt++ == 15)
if(phyLinkCnt++ == 10)
{
phyLinkCnt = 0;
phyRetryCnt = 0;
phyPNChangeCnt = 0;
phyLinkStatus = PHY_LINK_INIT;
}
}
else if(phyLinkStatus == PHY_LINK_INIT)
{
if(phyPNChangeCnt++ == 10)
{
phyPNChangeCnt = 0;
phyPN = ReadPHYReg(PHY_MDIX);
phyPN &= ~0x0c;
phyPN ^= 0x03;
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
}
else {
phyPN &= ~PHY_PN_SWITCH_N;
}
WritePHYReg(PHY_MDIX, phyPN);
}
}
else if(phyLinkStatus == PHY_LINK_SUC_N)
{
if((phyPN&0x0C) == PHY_PN_SWITCH_P)
{
phyPN |= PHY_PN_SWITCH_N;
phy_bmcr = ReadPHYReg(PHY_BMCR);
phy_bmcr |= 1<<9;
WritePHYReg(PHY_BMCR, phy_bmcr);
Delay_Us(10);
WritePHYReg(PHY_MDIX, phyPN);
}
else{
if(phyRetryCnt++ == 15)
{
phyRetryCnt = 0;
phyPNChangeCnt = 0;
phyLinkStatus = PHY_LINK_INIT;
}
}
}
}
}
}
@@ -506,6 +514,7 @@ void ETH_Configuration( uint8_t *macAddr )
R8_ETH_MACON2 |= PADCFG_AUTO_3; //All short packets are automatically padded to 60 bytes
R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN; //Hardware padded CRC
R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN; //Jumbo frames are not received
R8_ETH_MACON2 |= RB_ETH_MACON2_FULDPX;
R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
R8_ETH_ECON2 &= ~(0x07 << 1);
R8_ETH_ECON2 |= 5 << 1;
@@ -543,6 +552,44 @@ uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
return ETH_SUCCESS;
}
/*********************************************************************
* @fn ETH_LinkUpCfg
*
* @brief When the PHY is connected, configure the relevant functions.
*
* @param regval BMSR register value
*
* @return none.
*/
void ETH_LinkUpCfg(uint16_t regval)
{
WCHNET_PhyStatus( regval );
/* Receive CRC error packets */
R8_ETH_ERXFCON |= RB_ETH_ERXFCON_CRCEN;
CRCErrPktCnt = 0;
PhyPolarityDetect = 1;
phyLinkTime = LocalTime;
phyStatus = PHY_Linked_Status;
ETH_Start( );
}
/*********************************************************************
* @fn ETH_LinkDownCfg
*
* @brief When the PHY is disconnected, configure the relevant functions.
*
* @param regval BMSR register value
*
* @return none.
*/
void ETH_LinkDownCfg(uint16_t regval)
{
WCHNET_PhyStatus( regval );
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
phyLinkReset = 1;
phyLinkTime = LocalTime;
}
/*********************************************************************
* @fn ETH_PHYLink
*
@@ -552,42 +599,30 @@ uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
*/
void ETH_PHYLink( void )
{
uint32_t phy_stat, phy_anlpar;
u16 phy_bsr, phy_anlpar;
phy_bsr = ReadPHYReg(PHY_BMSR);
phy_anlpar = ReadPHYReg(PHY_ANLPAR);
phy_stat = ReadPHYReg(PHY_BMSR); //Read PHY Status Register
if((phy_stat&(PHY_Linked_Status))&&(phy_anlpar == 0)){ //restart negotiation
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
phyLinkReset = 1;
phyLinkTime = LocalTime;
return;
}
WCHNET_PhyStatus( phy_stat );
if( (phy_stat&(PHY_Linked_Status)) && (phy_stat&PHY_AutoNego_Complete) )
if(phy_bsr & PHY_Linked_Status) //Valid link established
{
if( phy_anlpar&(1<<6) )
if(phy_bsr & PHY_AutoNego_Complete) //Auto-negotiation completed -- LinkUp
{
R8_ETH_MACON2 |= RB_ETH_MACON2_FULDPX;
ETH_LinkUpCfg(phy_bsr);
}
else
{
R8_ETH_MACON2 &= ~RB_ETH_MACON2_FULDPX;
else {
if(phy_anlpar == 0) //The auto-negotiation signal of the peer device is not obtained
{
WritePHYReg(PHY_BMCR, PHY_Reset);
PHY_NEGOTIATION_PARAM_INIT();
}
else {
ETH_LinkDownCfg(phy_bsr);
}
}
/* Receive CRC error packets */
R8_ETH_ERXFCON |= RB_ETH_ERXFCON_CRCEN;
CRCErrPktCnt = 0;
PhyPolarityDetect = 1;
phyLinkTime = LocalTime;
phyStatus = PHY_Linked_Status;
ETH_Start( );
}
else
{
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
phyLinkReset = 1;
phyLinkTime = LocalTime;
else { //LinkDown
ETH_LinkDownCfg(phy_bsr);
}
}
EVT/EXAM/ETH/NetLib/libwchnet.a
BIN
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Binary file not shown.
EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/ETH/WebServer/.cproject
-1
View File
@@ -243,5 +243,4 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="refreshScope"/>
</cproject>
EVT/EXAM/ETH/WebServer/HTTP/HTTPS.c
+26 -4
View File
@@ -2339,6 +2339,28 @@ char * DataLocate(char *buf, char *name)
return p;
}
/*********************************************************************
* @fn atoh
*
* @brief Converting character to hexadecimal number
*
* @param src - character
*
* @return hexadecimal number
*/
uint8_t atoh(uint8_t *src)
{
uint8_t desc;
if((*src >= '0') && (*src <= '9'))
desc = *src - 0x30;
else if((*src >= 'a') && (*src <= 'f'))
desc = *src - 0x57;
else if((*src >= 'A') && (*src <= 'F'))
desc = *src - 0x37;
return desc;
}
/*********************************************************************
* @fn Refresh_Basic
*
@@ -2368,10 +2390,10 @@ void Refresh_Basic(u8 *buf)
if(q == NULL) return;
memcpy(temp, p, (q - p));
p = strtok(temp, ".");
BasicCfg.mac[0] = atoi(p);
(strlen(p) == 1) ? (BasicCfg.mac[0] = atoh(p)) : (BasicCfg.mac[0] = atoh(p) << 4 | atoh(p + 1));
for (i = 1; i < 6; i++) {
p = strtok(NULL, ".");
BasicCfg.mac[i] = atoi(p);
(strlen(p) == 1) ? (BasicCfg.mac[i] = atoh(p)) : (BasicCfg.mac[i] = atoh(p) << 4 | atoh(p + 1));
}
}
else return;
@@ -2790,11 +2812,11 @@ void Init_Para_Tab(void)
Para_Basic[0].para = "__AMAC";
memset(s, 0, 30);
snprintf(s, 30, "%d.%d.%d.%d.%d.%d", Basic_CfgBuf.mac[0], Basic_CfgBuf.mac[1],
snprintf(s, 30, "%x.%x.%x.%x.%x.%x", Basic_CfgBuf.mac[0], Basic_CfgBuf.mac[1],
Basic_CfgBuf.mac[2], Basic_CfgBuf.mac[3], Basic_CfgBuf.mac[4],
Basic_CfgBuf.mac[5]);
strcpy(Para_Basic[0].value, s);
printf("__ASIP = %s\n", Para_Basic[0].value);
printf("__ASMAC = %s\n", Para_Basic[0].value);
Para_Basic[1].para = "__ASIP";
memset(s, 0, 30);
EVT/EXAM/ETH/WebServer/User/main.c
+6 -10
View File
@@ -150,6 +150,7 @@ void WCHNET_CreateCfgSocket(u8 mode, u8 *Desip, u16 Desport, u16 Srcport)
*/
void WCHNET_RestoreDefaults(void) /*WCHNET restore default settings*/
{
WCHNET_GetMacAddr(&Basic_Default[2]);
WEB_ERASE( PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE * 3);
WEB_WRITE( BASIC_CFG_ADDR, Basic_Default, BASIC_CFG_LEN);
WEB_WRITE( PORT_CFG_ADDR, Port_Default, PORT_CFG_LEN);
@@ -287,18 +288,13 @@ int main(void)
WEB_READ( BASIC_CFG_ADDR, (u8 *)&Basic_CfgBuf, BASIC_CFG_LEN ); //Read configuration information
WEB_READ( PORT_CFG_ADDR, (u8 *)&Port_CfgBuf, PORT_CFG_LEN );
WEB_READ( LOGIN_CFG_ADDR, (u8 *)&Login_CfgBuf, LOGIN_CFG_LEN );
if((Basic_CfgBuf.flag[0] != 0x57) || (Basic_CfgBuf.flag[1] != 0xAB)){ //Determine network configuration information flags
/*Determine configuration information*/
if(((Basic_CfgBuf.flag[0] != 0x57) || (Basic_CfgBuf.flag[1] != 0xAB)) ||\
((Port_CfgBuf.flag[0] != 0x57) || (Port_CfgBuf.flag[1] != 0xAB)) ||\
((Login_CfgBuf.flag[0] != 0x57) || (Login_CfgBuf.flag[1] != 0xAB)))
{
WCHNET_RestoreDefaults();
}
else {
if((Port_CfgBuf.flag[0] != 0x57) || (Port_CfgBuf.flag[1] != 0xAB)){ //Determine password configuration information
WCHNET_RestoreDefaults();
}
else {
if((Login_CfgBuf.flag[0] != 0x57) || (Login_CfgBuf.flag[1] != 0xAB)) //Determine password configuration information
WCHNET_RestoreDefaults();
}
}
memcpy(MACAddr, Basic_CfgBuf.mac, 6);
memcpy(IPAddr, Basic_CfgBuf.ip, 4);
memcpy(IPMask, Basic_CfgBuf.mask, 4);
EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}