bstanwell/ch32v20x-examples
2
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

V2.0

Browse Source
This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
Download Patch File Download Diff File Expand all files Collapse all files
EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/ch32v20x_it.c
+4 -1
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_it.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2023/12/29
* Description : Main Interrupt Service Routines.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -24,6 +24,9 @@ void EXTI2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void NMI_Handler(void)
{
while (1)
{
}
}
/*********************************************************************
EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/main.c
+2 -2
View File
@@ -2,7 +2,7 @@
* File Name : main.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2023/12/29
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -109,7 +109,7 @@ int main(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_Init(GPIOE, &GPIO_InitStructure);
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
SystemCoreClockUpdate();
Delay_Init();
USART_Printf_Init(115200);
EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}