bstanwell/ch32v20x-examples
2
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

V2.0

Browse Source
This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
Download Patch File Download Diff File Expand all files Collapse all files
EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_conf.h
+40
View File
@@ -0,0 +1,40 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_conf.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : Library configuration file.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V20x_CONF_H
#define __CH32V20x_CONF_H
#include "ch32v20x_adc.h"
#include "ch32v20x_bkp.h"
#include "ch32v20x_can.h"
#include "ch32v20x_crc.h"
#include "ch32v20x_dbgmcu.h"
#include "ch32v20x_dma.h"
#include "ch32v20x_exti.h"
#include "ch32v20x_flash.h"
#include "ch32v20x_gpio.h"
#include "ch32v20x_i2c.h"
#include "ch32v20x_iwdg.h"
#include "ch32v20x_pwr.h"
#include "ch32v20x_rcc.h"
#include "ch32v20x_rtc.h"
#include "ch32v20x_spi.h"
#include "ch32v20x_tim.h"
#include "ch32v20x_usart.h"
#include "ch32v20x_wwdg.h"
#include "ch32v20x_it.h"
#include "ch32v20x_misc.h"
#endif /* __CH32V20x_CONF_H */
EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.c
+45
View File
@@ -0,0 +1,45 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_it.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/29
* Description : Main Interrupt Service Routines.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_it.h"
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
* @fn NMI_Handler
*
* @brief This function handles NMI exception.
*
* @return none
*/
void NMI_Handler(void)
{
while (1)
{
}
}
/*********************************************************************
* @fn HardFault_Handler
*
* @brief This function handles Hard Fault exception.
*
* @return none
*/
void HardFault_Handler(void)
{
while (1)
{
}
}
EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.h
+18
View File
@@ -0,0 +1,18 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_it.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains the headers of the interrupt handlers.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __CH32V20x_IT_H
#define __CH32V20x_IT_H
#include "debug.h"
#endif /* __CH32V20x_IT_H */
EVT/EXAM/RCC/HSE_CLK/User/main.c
+303
View File
@@ -0,0 +1,303 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : main.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
/*
*@Note
*HSE frequency check routine:
*Checking the frequency value of HSE by using of HSI.
* When HSE is 3 ~ 25M,the HSE clock is effective ,When CH32F20x_D8 and CH32F20x_D6 used.
* When HSE is 32M,the HSE clock is effective ,When CH32F20x_D8C and CH32F20x_D8W used.
*HSE value -the frequency of HSE
*MCO(PA8) - outputs the HSE clock
*
*/
#include "debug.h"
uint8_t HSEFrequencyMhz;
uint8_t value;
#define F1M 1000000
#define CHECK_ERR_COUNT (8)
#define RTC_COUNT_DELAY (100)
#define HSIClock (8000000)
#define PPL2_ENABLE 1
#define HSE_ENABLE 0
#define STclk_div8 0
#define STclk_div1 1
#define CHECK_MODE STclk_div8
//#define CHECK_MODE STclk_div1
uint8_t value=0;
/*********************************************************************
* @fn HSE_FrequencyCheck
*
* @brief Checking HSE Frequency Values.
*
* @return HSEFrequencyMhz - HSE Frequency
*/
uint8_t HSE_FrequencyCheck(void) {
uint32_t rtc_val;
uint32_t tick_val;
uint32_t HSEFrequency, HSEFrequency_x, RTC_DIV_VAL,RTC_CHANGE_TIMEOUT,RTC_COUNT_MAX_TIMEOUT;
uint8_t count;
#if defined (CH32V20x_D6)
if(((*(uint32_t *) 0x40022030) & 0x0F000000) != 0)
{
RTC_DIV_VAL=128;
}
else {
RTC_DIV_VAL=512;
}
#else
RTC_DIV_VAL=512;
#endif
RTC_CHANGE_TIMEOUT=(HSIClock/F1M)*RTC_DIV_VAL;
RTC_COUNT_MAX_TIMEOUT=(HSIClock/F1M)*RTC_DIV_VAL*RTC_COUNT_DELAY;
Delay_Init();
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
PWR_BackupAccessCmd(ENABLE);
BKP_DeInit();
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
RCC_RTCCLKConfig(RCC_RTCCLKSource_HSE_Div512);
#else
RCC_RTCCLKConfig(RCC_RTCCLKSource_HSE_Div128);
#endif
RCC_RTCCLKCmd(ENABLE);
RTC_WaitForLastTask();
RTC_WaitForSynchro();
RTC_WaitForLastTask();
RTC_EnterConfigMode();
RTC_SetPrescaler(0);
RTC_WaitForLastTask();
RTC_ExitConfigMode();
while( (RCC->BDCTLR & (1<<15)) != (1<<15) ) {}
count = CHECK_ERR_COUNT;
while(1) {
SysTick->CTLR = 0;
SysTick->CNT =0;
#if (CHECK_MODE == STclk_div1)
SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
#elif (CHECK_MODE == STclk_div8)
SysTick->CTLR = (1<<5)|(1<<0);
#endif
rtc_val = RTC_GetCounter();
while( rtc_val == RTC_GetCounter()) {
if( SysTick->CNT > RTC_CHANGE_TIMEOUT ) {
return 0;
}
}
SysTick->CTLR = 0;
SysTick->CNT =0;
#if (CHECK_MODE == STclk_div1)
SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
#elif (CHECK_MODE == STclk_div8)
SysTick->CTLR = (1<<5)|(1<<0);
#endif
rtc_val += (RTC_COUNT_DELAY);
while( rtc_val >= RTC_GetCounter() ) {
if( SysTick->CNT > RTC_COUNT_MAX_TIMEOUT ) {
return 0;
}
}
tick_val = SysTick->CNT;
SysTick->CTLR = 0;
#if (CHECK_MODE == STclk_div1)
HSEFrequency = HSIClock/(tick_val/RTC_DIV_VAL)*RTC_COUNT_DELAY;
#elif (CHECK_MODE == STclk_div8)
HSEFrequency = HSIClock/(tick_val/(RTC_DIV_VAL/8))*RTC_COUNT_DELAY;
#endif
HSEFrequencyMhz = (HSEFrequency+(F1M/2))/F1M;
SysTick->CTLR = 0;
SysTick->CNT =0;
#if (CHECK_MODE == STclk_div1)
SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
#elif (CHECK_MODE == STclk_div8)
SysTick->CTLR = (1<<5)|(1<<0);
#endif
rtc_val = RTC_GetCounter();
while( rtc_val == RTC_GetCounter() ) {
if( SysTick->CNT > RTC_CHANGE_TIMEOUT ) {
return 0;
}
}
SysTick->CTLR = 0;
SysTick->CNT =0;
#if (CHECK_MODE == STclk_div1)
SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
#elif (CHECK_MODE == STclk_div8)
SysTick->CTLR = (1<<5)|(1<<0);
#endif
rtc_val += (RTC_COUNT_DELAY);
while( rtc_val >= RTC_GetCounter() ) {
if( SysTick->CNT > RTC_COUNT_MAX_TIMEOUT ) {
return 0;
}
}
tick_val = SysTick->CNT;
SysTick->CTLR = 0;
#if (CHECK_MODE == STclk_div1)
HSEFrequency = HSIClock/(tick_val/RTC_DIV_VAL)*RTC_COUNT_DELAY;
#elif (CHECK_MODE == STclk_div8)
HSEFrequency = HSIClock/(tick_val/(RTC_DIV_VAL/8))*RTC_COUNT_DELAY;
#endif
HSEFrequency_x = (HSEFrequency+(F1M/2))/F1M;
if( HSEFrequencyMhz == HSEFrequency_x ) {
break;
}
if( --count == 0 ) {
HSEFrequencyMhz = 253;
printf("HSE check error.\n");
break;
}
}
return HSEFrequencyMhz;
}
/*********************************************************************
* @fn SetSysClockTo72
*
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo72(void) {
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
USART_Printf_Init(115200);
RCC->CTLR |= ((uint32_t) RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET) {
value = HSE_FrequencyCheck();
HSEStatus = (uint32_t) 0x00;
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
if (value == 32) {
HSEStatus = (uint32_t) 0x01;
}
#else
if ((value >= 3) && (value <= 25)) {
HSEStatus = (uint32_t) 0x01;
}
#endif
} else {
HSEStatus = (uint32_t) 0x00;
}
if (HSEStatus == (uint32_t) 0x01) {
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
| RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t) RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
} else {
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t) (RCC_PLLSRC_HSI_Div2 | RCC_PLLXTPRE_HSE
| RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t) RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
}
/*********************************************************************
* @fn main
*
* @brief Main program.
*
* @return none
*/
int main(void)
{
GPIO_InitTypeDef GPIO_InitStructure={0};
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
SetSysClockTo72();
USART_Printf_Init(115200);
SystemCoreClockUpdate();
printf("SystemClk:%d\r\n",SystemCoreClock);
printf("HSE value %02d\r\n", value);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* MCO Output GPIOA 8 */
RCC_MCOConfig( RCC_MCO_HSE );
while(1);
}
EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.c
+119
View File
@@ -0,0 +1,119 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v20x.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 8Mhz (other CH32V203x)
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
#include "ch32v20x.h"
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
*/
/* Clock Definitions */
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
__I uint8_t AHBPrescTable[16] =
{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
/* system_private_function_proto_types */
static void SetSysClock(void);
/*********************************************************************
* @fn SystemInit
*
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
* the PLL and update the SystemCoreClock variable.
*
* @return none
*/
void SystemInit(void) {
RCC->CTLR |= (uint32_t) 0x00000001;
RCC->CFGR0 &= (uint32_t) 0xF8FF0000;
RCC->CTLR &= (uint32_t) 0xFEF6FFFF;
RCC->CTLR &= (uint32_t) 0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t) 0xFF80FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
/*********************************************************************
* @fn SystemCoreClockUpdate
*
* @brief Update SystemCoreClock variable according to Clock Register Values.
*
* @return none
*/
void SystemCoreClockUpdate(void) {
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
tmp = RCC->CFGR0 & RCC_SWS;
switch (tmp) {
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
case 0x04:
SystemCoreClock = HSE_VALUE;
break;
case 0x08:
pllmull = RCC->CFGR0 & RCC_PLLMULL;
pllsource = RCC->CFGR0 & RCC_PLLSRC;
pllmull = (pllmull >> 18) + 2;
if (pllmull == 17)
pllmull = 18;
if (pllsource == 0x00) {
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
} else {
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t) RESET) {
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = ((HSE_VALUE >> 2) >> 1) * pllmull;
#else
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
#endif
} else {
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = (HSE_VALUE >> 2) * pllmull;
#else
SystemCoreClock = HSE_VALUE * pllmull;
#endif
}
}
if (Pll_6_5 == 1)
SystemCoreClock = (SystemCoreClock / 2);
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
SystemCoreClock >>= tmp;
}
/*********************************************************************
* @fn SetSysClock
*
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClock(void) {
/* If none of the define above is enabled, the HSI is used as System clock
* source (default after reset)
*/
}
EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.h
+30
View File
@@ -0,0 +1,30 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Header File.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef __SYSTEM_ch32v20x_H
#define __SYSTEM_ch32v20x_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V20x_SYSTEM_H */