bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
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EVT/EXAM/SRC/Core/core_riscv.h
+7 -6
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@@ -263,13 +263,14 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* interrupt nesting enable(CSR-0x804 bit1 = 1 bit[3:2] = 1)
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:4] - Sub priority
* bit[3:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0 bit[3:2] = 0)
* priority - bit[7:4] - Sub priority
* bit[3:0] - Reserve
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+23 -12
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@@ -2,7 +2,7 @@
* File Name : ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/31
* Description : CH32V20x Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -38,8 +38,8 @@ extern "C" {
#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
/* CH32V20x Standard Peripheral Library version number */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x09) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
@@ -100,8 +100,8 @@ typedef enum IRQn
EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */
RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */
USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */
USBHD_IRQn = 59, /* USBHD global Interrupt */
USBHDWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */
USBFS_IRQn = 59, /* USBFS global Interrupt */
USBFSWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */
#ifdef CH32V20x_D6
UART4_IRQn = 61, /* UART4 global Interrupt */
@@ -130,8 +130,18 @@ typedef enum IRQn
} IRQn_Type;
#define HardFault_IRQn EXC_IRQn
#define ADC1_2_IRQn ADC_IRQn
#define HardFault_IRQn EXC_IRQn
#define ADC1_2_IRQn ADC_IRQn
#define USBHD_IRQn USBFS_IRQn
#define USBHDWakeUp_IRQn USBFSWakeUp_IRQn
#define USBHD_IRQHandler USBFS_IRQHandler
#define USBHDWakeUp_IRQHandler USBFSWakeUp_IRQHandler
#define USBOTG_FS USBFSD
#define USBOTG_H_FS USBFSH
#include <stdint.h>
#include "core_riscv.h"
@@ -686,7 +696,7 @@ typedef struct
__IO uint32_t Reserve1;
__IO uint32_t OTG_CR;
__IO uint32_t OTG_SR;
} USBOTG_FS_TypeDef;
} USBFSD_TypeDef;
typedef struct
{
@@ -728,7 +738,7 @@ typedef struct
__IO uint32_t Reserve19;
__IO uint32_t OTG_CR;
__IO uint32_t OTG_SR;
} USBOTG_FS_HOST_TypeDef;
} USBFSH_TypeDef;
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
/* ETH10M Registers */
@@ -909,8 +919,8 @@ typedef struct
#define RCC ((RCC_TypeDef *)RCC_BASE)
#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
#define CRC ((CRC_TypeDef *)CRC_BASE)
#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE)
#define USBOTG_H_FS ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE)
#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE)
#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE)
#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
#define OPA ((OPA_TypeDef *)OPA_BASE)
#define ETH10M ((ETH10M_TypeDef *)ETH10M_BASE)
@@ -4046,7 +4056,8 @@ typedef struct
#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */
#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */
#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */
#define RCC_USBHD ((uint16_t)0x1000)
#define RCC_USBFS ((uint16_t)0x1000)
#define RCC_USBHD RCC_USBFS
/****************** Bit definition for RCC_APB2PCENR register *****************/
#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_misc.h
+36 -9
View File
@@ -19,21 +19,48 @@ extern "C" {
#include "ch32v20x.h"
/* NVIC Init Structure definition */
/* CSR_INTSYSCR_INEST_definition */
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
/* Check the configuration of CSR(0x804) in the startup file(.S)
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*/
#ifndef INTSYSCR_INEST
#define INTSYSCR_INEST INTSYSCR_INEST_EN
#endif
/* NVIC Init Structure definition
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#else
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
#endif
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h
+8 -2
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/02/21
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -111,7 +111,12 @@ typedef struct
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x00000300)
#else
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#endif
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
@@ -122,7 +127,8 @@ typedef struct
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
#ifdef CH32V20x_D8W
#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040)
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usart.h
+1 -3
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/06
* Description : This file contains all the functions prototypes for the
* USART firmware library.
*********************************************************************************
@@ -171,8 +171,6 @@ void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usb.h
+1 -4
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_usb.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/10/24
* Date : 2024/01/30
* Description : This file contains all the functions prototypes for the USB
* firmware library.
*********************************************************************************
@@ -229,7 +229,6 @@ extern "C" {
#define USBFS_UC_DMA_EN 0x01
/* R8_USB_INT_EN */
#define USBFS_UIE_DEV_SOF 0x80
#define USBFS_UIE_DEV_NAK 0x40
#define USBFS_UIE_FIFO_OV 0x10
#define USBFS_UIE_HST_SOF 0x08
@@ -268,12 +267,10 @@ extern "C" {
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
#define USBFS_UIS_TOKEN_OUT 0x00
#define USBFS_UIS_TOKEN_SOF 0x10
#define USBFS_UIS_TOKEN_IN 0x20
#define USBFS_UIS_TOKEN_SETUP 0x30
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 01: SOF token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
EVT/EXAM/SRC/Peripheral/src/ch32v20x_bkp.c
+2 -2
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_bkp.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2023/01/06
* Description : This file provides all the BKP firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -128,7 +128,7 @@ void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
* @brief Sets RTC Clock Calibration value.
*
* @param CalibrationValue - specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x1F.
* This parameter must be a number between 0 and 0x7F.
*
* @return none
*/
EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c
+1 -1
View File
@@ -60,7 +60,7 @@
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00005000)
/* Flash Program Vaild Address */
/* Flash Program Valid Address */
#define ValidAddrStart (FLASH_BASE)
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
EVT/EXAM/SRC/Peripheral/src/ch32v20x_i2c.c
+5 -1
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_i2c.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2023/12/29
* Description : This file provides all the I2C firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -138,6 +138,10 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
pclk1 = rcc_clocks.PCLK1_Frequency;
freqrange = (uint16_t)(pclk1 / 1000000);
tmpreg |= freqrange;
if(freqrange >= 60)
{
freqrange = 60;
}
I2Cx->CTLR2 = tmpreg;
I2Cx->CTLR1 &= CTLR1_PE_Reset;
EVT/EXAM/SRC/Peripheral/src/ch32v20x_iwdg.c
+2 -1
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2023/12/29
* Description : This file provides all the IWDG firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -92,6 +92,7 @@ void IWDG_ReloadCounter(void)
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
while((RCC->RSTSCKR)|(0x2)!=SET);
}
/*********************************************************************
EVT/EXAM/SRC/Peripheral/src/ch32v20x_misc.c
+15 -43
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@@ -20,15 +20,9 @@ __IO uint32_t NVIC_Priority_Group = 0;
*
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 4 bits for subpriority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 3 bits for subpriority
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 2 bits for subpriority
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
* 1 bits for subpriority
* NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
* 0 bits for subpriority
*
* @return none
*/
@@ -45,58 +39,36 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
*
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral.
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
* @return none
*/
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
{
uint8_t tmppre = 0;
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
#else
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
}
else
else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
}
#endif
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
EVT/EXAM/SRC/Peripheral/src/ch32v20x_rcc.c
+6 -5
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_rcc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/30
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -82,10 +82,10 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
void RCC_DeInit(void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
}
@@ -506,7 +506,8 @@ void RCC_LSICmd(FunctionalState NewState)
* @param RCC_RTCCLKSource - specifies the RTC clock source.
* RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
* RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
* RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
* RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock(CH32V20x_D6)
* RCC_RTCCLKSource_HSE_Div512 - HSE clock divided by 512 selected as RTC clock(CH32V20x_D8,CH32V20x_D8W)
* Note-
* Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
* @return none
@@ -645,7 +646,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
* RCC_AHBPeriph_DMA2.
* RCC_AHBPeriph_SRAM.
* RCC_AHBPeriph_CRC.
* RCC_AHBPeriph_OTG_FS
* RCC_AHBPeriph_USBFS
* Note-
* SRAM clock can be disabled only during sleep mode.
* NewState: ENABLE or DISABLE.
EVT/EXAM/SRC/Peripheral/src/ch32v20x_rtc.c
+119 -57
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_rtc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/06
* Description : This file provides all the RTC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -334,6 +334,7 @@ void Calibration_LSI(Cali_LevelTypeDef cali_Lv)
int32_t cnt_offset;
int32_t Freq = 0;
uint8_t retry = 0;
uint8_t retry_all = 0;
uint32_t cnt_32k = 0;
Freq = SystemCoreClock;
// Coarse tuning
@@ -341,76 +342,137 @@ void Calibration_LSI(Cali_LevelTypeDef cali_Lv)
OSC->LSI32K_CAL_CFG |= 0;
while(1)
{
retry_all++;
while(1)
{
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
cnt_32k = RTC_GetCounter();
while(RTC_GetCounter() == cnt_32k);
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 2000 * (Freq / 1000) / CAB_LSIFQ;
if(((cnt_offset > -(20 * (Freq / 1000) / 36000)) && (cnt_offset < (20 * (Freq / 1000) / 36000))) || retry > 2)
break;
retry++;
cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) + 1) / 2 : (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) - 1) / 2;
OSC->LSI32K_TUNE += cnt_offset;
}
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
OSC->LSI32K_CAL_CFG |= 2;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
// Fine tuning
// After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
cnt_32k = RTC_GetCounter();
while(RTC_GetCounter() == cnt_32k);
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 2000 * (Freq / 1000) / CAB_LSIFQ;
if(((cnt_offset > -(20 * (Freq / 1000) / 36000)) && (cnt_offset < (20 * (Freq / 1000) / 36000))) || retry > 2)
break;
retry++;
cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) + 1) / 2 : (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) - 1) / 2;
OSC->LSI32K_TUNE += cnt_offset;
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << 2) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) + 1) / 2) : ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) - 1) / 2);
if((cnt_offset > 0)&&(((OSC->LSI32K_TUNE>>5)+cnt_offset)>0x7FF))
{
if(retry_all>2)
{
OSC->LSI32K_TUNE |= (0xFF<<5);
}
else
{
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3FF<<5);
continue;
}
}
else if((cnt_offset < 0)&&((OSC->LSI32K_TUNE>>5)<(-cnt_offset)))
{
if(retry_all>2)
{
OSC->LSI32K_TUNE &= 0x1F;
}
else
{
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x7F<<5);
continue;
}
}
else
{
OSC->LSI32K_TUNE += (cnt_offset<<5);
}
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
OSC->LSI32K_CAL_CFG |= cali_Lv;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
// Fine tuning
// After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
cnt_32k = RTC_GetCounter();
while(RTC_GetCounter() == cnt_32k);
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
i = OSC->LSI32K_CAL_STATR;
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << cali_Lv) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) + 1) / 2) : ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) - 1) / 2);
if((cnt_offset > 0)&&(((OSC->LSI32K_TUNE>>5)+cnt_offset)>0x7FF))
{
if(retry_all>2)
{
OSC->LSI32K_TUNE |= (0xFF<<5);
return;
}
else
{
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3FF<<5);
continue;
}
}
else if((cnt_offset < 0)&&((OSC->LSI32K_TUNE>>5)<(-cnt_offset)))
{
if(retry_all>2)
{
OSC->LSI32K_TUNE &= 0x1F;
return;
}
else
{
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3F<<5);
continue;
}
}
else
{
OSC->LSI32K_TUNE += (cnt_offset<<5);
return;
}
}
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
OSC->LSI32K_CAL_CFG |= 2;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
// Fine tuning
// After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
cnt_32k = RTC_GetCounter();
while(RTC_GetCounter() == cnt_32k);
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << 2) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) + 1) / 2) << 5 : ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) - 1) / 2) << 5;
OSC->LSI32K_TUNE += cnt_offset;
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
OSC->LSI32K_CAL_CFG |= cali_Lv;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
// Fine tuning
// After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
i = OSC->LSI32K_CAL_STATR;
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
cnt_32k = RTC_GetCounter();
while(RTC_GetCounter() == cnt_32k);
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
i = OSC->LSI32K_CAL_STATR;
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << cali_Lv) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) + 1) / 2) << 5 : ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) - 1) / 2) << 5;
OSC->LSI32K_TUNE += cnt_offset;
}
#endif
EVT/EXAM/SRC/Peripheral/src/ch32v20x_tim.c
+1 -1
View File
@@ -2344,7 +2344,7 @@ static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
}
else
{
tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP));
tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P ));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E);
}
EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c
+3 -75
View File
@@ -2,7 +2,7 @@
* File Name : ch32v20x_usart.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/06
* Description : This file provides all the USART firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -49,14 +49,6 @@
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
/* USART OverSampling-8 Mask */
#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
/* USART One Bit Sampling Mask */
#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
/*********************************************************************
* @fn USART_DeInit
*
@@ -143,28 +135,10 @@ void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
{
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
}
if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
{
integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
}
else
{
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
}
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
tmpreg = (integerdivider / 100) << 4;
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
{
tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
}
else
{
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
}
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
USARTx->BRR = (uint16_t)tmpreg;
}
@@ -568,52 +542,6 @@ void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
}
}
/*********************************************************************
* @fn USART_OverSampling8Cmd
*
* @brief Enables or disables the USART's 8x oversampling mode.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
* Note-
* This function has to be called before calling USART_Init()
* function in order to have correct baudrate Divider value.
* @return none
*/
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_OVER8_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_OVER8_Reset;
}
}
/*********************************************************************
* @fn USART_OneBitMethodCmd
*
* @brief Enables or disables the USART's one bit sampling method.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
}
}
/*********************************************************************
* @fn USART_IrDAConfig
*
EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S
+7 -7
View File
@@ -2,7 +2,7 @@
;* File Name : startup_ch32v20x_D6.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2023/11/11
;* Date : 2024/01/31
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
;* vector table for eclipse toolchain.
;*********************************************************************************
@@ -81,8 +81,8 @@ _vector_base:
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
.word USBHD_IRQHandler /* USBHD Break */
.word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */
.word USBFS_IRQHandler /* USBFS Break */
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
.word UART4_IRQHandler /* UART4 */
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
@@ -138,8 +138,8 @@ _vector_base:
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.weak USBHD_IRQHandler /* USBHD */
.weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */
.weak USBFS_IRQHandler /* USBFS */
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
.weak UART4_IRQHandler /* UART4 */
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
@@ -193,8 +193,8 @@ USART3_IRQHandler:
EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler:
USBHD_IRQHandler:
USBHDWakeUp_IRQHandler:
USBFS_IRQHandler:
USBFSWakeUp_IRQHandler:
UART4_IRQHandler:
DMA1_Channel8_IRQHandler:
1:
EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S
+7 -7
View File
@@ -2,7 +2,7 @@
;* File Name : startup_ch32v20x_D8.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2023/11/11
;* Date : 2024/01/31
;* Description : CH32V203RB
;* vector table for eclipse toolchain.
;*********************************************************************************
@@ -81,8 +81,8 @@ _vector_base:
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
.word USBHD_IRQHandler /* USBHD Break */
.word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */
.word USBFS_IRQHandler /* USBFS Break */
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
.word ETH_IRQHandler /* ETH global */
.word ETHWakeUp_IRQHandler /* ETH Wake up */
.word 0 /* BLE BB */
@@ -145,8 +145,8 @@ _vector_base:
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.weak USBHD_IRQHandler /* USBHD */
.weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */
.weak USBFS_IRQHandler /* USBFS */
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
.weak ETH_IRQHandler /* ETH global */
.weak ETHWakeUp_IRQHandler /* ETHWakeUp */
.weak TIM5_IRQHandler /* TIM5 */
@@ -205,8 +205,8 @@ USART3_IRQHandler:
EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler:
USBHD_IRQHandler:
USBHDWakeUp_IRQHandler:
USBFS_IRQHandler:
USBFSWakeUp_IRQHandler:
ETH_IRQHandler:
ETHWakeUp_IRQHandler:
TIM5_IRQHandler:
EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S
+6 -6
View File
@@ -81,8 +81,8 @@ _vector_base:
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
.word USBHD_IRQHandler /* USBHD Break */
.word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */
.word USBFS_IRQHandler /* USBFS Break */
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
.word ETH_IRQHandler /* ETH global */
.word ETHWakeUp_IRQHandler /* ETH Wake up */
.word BB_IRQHandler /* BLE BB */
@@ -145,8 +145,8 @@ _vector_base:
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.weak USBHD_IRQHandler /* USBHD */
.weak USBHDWakeUp_IRQHandler /* USBHD Wake Up */
.weak USBFS_IRQHandler /* USBFS */
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
.weak ETH_IRQHandler /* ETH global */
.weak ETHWakeUp_IRQHandler /* ETHWakeUp */
.weak BB_IRQHandler /* BLE BB */
@@ -207,8 +207,8 @@ USART3_IRQHandler:
EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler:
USBHD_IRQHandler:
USBHDWakeUp_IRQHandler:
USBFS_IRQHandler:
USBFSWakeUp_IRQHandler:
ETH_IRQHandler:
ETHWakeUp_IRQHandler:
BB_IRQHandler: