bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
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EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+23 -12
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@@ -2,7 +2,7 @@
* File Name : ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/31
* Description : CH32V20x Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -38,8 +38,8 @@ extern "C" {
#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
/* CH32V20x Standard Peripheral Library version number */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x09) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
@@ -100,8 +100,8 @@ typedef enum IRQn
EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */
RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */
USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */
USBHD_IRQn = 59, /* USBHD global Interrupt */
USBHDWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */
USBFS_IRQn = 59, /* USBFS global Interrupt */
USBFSWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */
#ifdef CH32V20x_D6
UART4_IRQn = 61, /* UART4 global Interrupt */
@@ -130,8 +130,18 @@ typedef enum IRQn
} IRQn_Type;
#define HardFault_IRQn EXC_IRQn
#define ADC1_2_IRQn ADC_IRQn
#define HardFault_IRQn EXC_IRQn
#define ADC1_2_IRQn ADC_IRQn
#define USBHD_IRQn USBFS_IRQn
#define USBHDWakeUp_IRQn USBFSWakeUp_IRQn
#define USBHD_IRQHandler USBFS_IRQHandler
#define USBHDWakeUp_IRQHandler USBFSWakeUp_IRQHandler
#define USBOTG_FS USBFSD
#define USBOTG_H_FS USBFSH
#include <stdint.h>
#include "core_riscv.h"
@@ -686,7 +696,7 @@ typedef struct
__IO uint32_t Reserve1;
__IO uint32_t OTG_CR;
__IO uint32_t OTG_SR;
} USBOTG_FS_TypeDef;
} USBFSD_TypeDef;
typedef struct
{
@@ -728,7 +738,7 @@ typedef struct
__IO uint32_t Reserve19;
__IO uint32_t OTG_CR;
__IO uint32_t OTG_SR;
} USBOTG_FS_HOST_TypeDef;
} USBFSH_TypeDef;
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
/* ETH10M Registers */
@@ -909,8 +919,8 @@ typedef struct
#define RCC ((RCC_TypeDef *)RCC_BASE)
#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
#define CRC ((CRC_TypeDef *)CRC_BASE)
#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE)
#define USBOTG_H_FS ((USBOTG_FS_HOST_TypeDef *)USBFS_BASE)
#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE)
#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE)
#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
#define OPA ((OPA_TypeDef *)OPA_BASE)
#define ETH10M ((ETH10M_TypeDef *)ETH10M_BASE)
@@ -4046,7 +4056,8 @@ typedef struct
#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */
#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */
#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */
#define RCC_USBHD ((uint16_t)0x1000)
#define RCC_USBFS ((uint16_t)0x1000)
#define RCC_USBHD RCC_USBFS
/****************** Bit definition for RCC_APB2PCENR register *****************/
#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_misc.h
+36 -9
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@@ -19,21 +19,48 @@ extern "C" {
#include "ch32v20x.h"
/* NVIC Init Structure definition */
/* CSR_INTSYSCR_INEST_definition */
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
/* Check the configuration of CSR(0x804) in the startup file(.S)
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*/
#ifndef INTSYSCR_INEST
#define INTSYSCR_INEST INTSYSCR_INEST_EN
#endif
/* NVIC Init Structure definition
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#else
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
#endif
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h
+8 -2
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/02/21
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -111,7 +111,12 @@ typedef struct
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x00000300)
#else
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#endif
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
@@ -122,7 +127,8 @@ typedef struct
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
#ifdef CH32V20x_D8W
#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040)
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usart.h
+1 -3
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/01/06
* Description : This file contains all the functions prototypes for the
* USART firmware library.
*********************************************************************************
@@ -171,8 +171,6 @@ void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usb.h
+1 -4
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_usb.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/10/24
* Date : 2024/01/30
* Description : This file contains all the functions prototypes for the USB
* firmware library.
*********************************************************************************
@@ -229,7 +229,6 @@ extern "C" {
#define USBFS_UC_DMA_EN 0x01
/* R8_USB_INT_EN */
#define USBFS_UIE_DEV_SOF 0x80
#define USBFS_UIE_DEV_NAK 0x40
#define USBFS_UIE_FIFO_OV 0x10
#define USBFS_UIE_HST_SOF 0x08
@@ -268,12 +267,10 @@ extern "C" {
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
#define USBFS_UIS_TOKEN_OUT 0x00
#define USBFS_UIS_TOKEN_SOF 0x10
#define USBFS_UIS_TOKEN_IN 0x20
#define USBFS_UIS_TOKEN_SETUP 0x30
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 01: SOF token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode