bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
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EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_it.c
+3
View File
@@ -23,6 +23,9 @@ void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void NMI_Handler(void)
{
while (1)
{
}
}
/*********************************************************************
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c
+58 -62
View File
@@ -49,7 +49,7 @@ volatile uint8_t USBFS_Endp_Busy[ DEF_UEP_NUM ];
/******************************************************************************/
/* Interrupt Service Routine Declaration*/
void USBHD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
* @fn USBFS_RCC_Init
@@ -72,7 +72,7 @@ void USBFS_RCC_Init( void )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE );
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
/*********************************************************************
@@ -84,17 +84,17 @@ void USBFS_RCC_Init( void )
*/
void USBFS_Device_Endp_Init( void )
{
USBOTG_FS->UEP4_1_MOD = USBFS_UEP1_TX_EN;
USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_TX_EN;
USBFSD->UEP4_1_MOD = USBFS_UEP1_TX_EN;
USBFSD->UEP2_3_MOD = USBFS_UEP2_TX_EN;
USBOTG_FS->UEP0_DMA = (uint32_t)USBFS_EP0_Buf;
USBOTG_FS->UEP1_DMA = (uint32_t)USBFS_EP1_Buf;
USBOTG_FS->UEP2_DMA = (uint32_t)USBFS_EP2_Buf;
USBFSD->UEP0_DMA = (uint32_t)USBFS_EP0_Buf;
USBFSD->UEP1_DMA = (uint32_t)USBFS_EP1_Buf;
USBFSD->UEP2_DMA = (uint32_t)USBFS_EP2_Buf;
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK;
/* Clear End-points Busy Status */
for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
@@ -115,23 +115,23 @@ void USBFS_Device_Init( FunctionalState sta )
if( sta )
{
/* Reset USB module */
USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
USBFSH->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
Delay_Us( 10 );
USBOTG_H_FS->BASE_CTRL = 0;
USBFSH->BASE_CTRL = 0;
/* Initialize USB device configuration */
USBFS_Device_Endp_Init( );
USBOTG_FS->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER;
USBOTG_FS->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
USBOTG_FS->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN;
NVIC_EnableIRQ( USBHD_IRQn );
USBFSD->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER;
USBFSD->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
USBFSD->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN;
NVIC_EnableIRQ( USBFS_IRQn );
}
else
{
USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
USBFSH->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
Delay_Us( 10 );
USBOTG_FS->BASE_CTRL = 0;
NVIC_DisableIRQ( USBHD_IRQn );
USBFSD->BASE_CTRL = 0;
NVIC_DisableIRQ( USBFS_IRQn );
}
}
@@ -262,19 +262,19 @@ uint8_t USBFS_Endp_DataUp(uint8_t endp, uint8_t *pbuf, uint16_t len, uint8_t mod
}
/*********************************************************************
* @fn USBHD_IRQHandler
* @fn USBFS_IRQHandler
*
* @brief USB device transfer process.
*
* @return none
*/
void USBHD_IRQHandler( void )
void USBFS_IRQHandler( void )
{
uint8_t intflag, intst, errflag;
uint16_t len;
intflag = USBOTG_FS->INT_FG;
intst = USBOTG_FS->INT_ST;
intflag = USBFSD->INT_FG;
intst = USBFSD->INT_ST;
if( intflag & USBFS_UIF_TRANSFER )
{
@@ -288,7 +288,7 @@ void USBHD_IRQHandler( void )
case USBFS_UIS_TOKEN_IN | DEF_UEP0:
if( USBFS_SetupReqLen == 0 )
{
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
}
if ( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD )
@@ -304,12 +304,12 @@ void USBHD_IRQHandler( void )
memcpy( USBFS_EP0_Buf, pUSBFS_Descr, len );
USBFS_SetupReqLen -= len;
pUSBFS_Descr += len;
USBOTG_FS->UEP0_TX_LEN = len;
USBOTG_FS->UEP0_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFSD->UEP0_TX_LEN = len;
USBFSD->UEP0_TX_CTRL ^= USBFS_UEP_T_TOG;
break;
case USB_SET_ADDRESS:
USBOTG_FS->DEV_ADDR = ( USBOTG_FS->DEV_ADDR & USBFS_UDA_GP_BIT ) | USBFS_DevAddr;
USBFSD->DEV_ADDR = ( USBFSD->DEV_ADDR & USBFS_UDA_GP_BIT ) | USBFS_DevAddr;
break;
default:
@@ -320,15 +320,15 @@ void USBHD_IRQHandler( void )
/* end-point 1 data in interrupt */
case USBFS_UIS_TOKEN_IN | DEF_UEP1:
USBOTG_FS->UEP1_TX_CTRL = ( USBOTG_FS->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP1_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFSD->UEP1_TX_CTRL = ( USBFSD->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_NAK;
USBFSD->UEP1_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFS_Endp_Busy[ DEF_UEP1 ] = 0;
break;
/* end-point 2 data in interrupt */
case USBFS_UIS_TOKEN_IN | DEF_UEP2:
USBOTG_FS->UEP2_TX_CTRL = ( USBOTG_FS->UEP2_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP2_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFSD->UEP2_TX_CTRL = ( USBFSD->UEP2_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_NAK;
USBFSD->UEP2_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFS_Endp_Busy[ DEF_UEP2 ] = 0;
break;
@@ -368,8 +368,8 @@ void USBHD_IRQHandler( void )
}
if( USBFS_SetupReqLen == 0 )
{
USBOTG_FS->UEP0_TX_LEN = 0;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
USBFSD->UEP0_TX_LEN = 0;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
}
break;
@@ -380,8 +380,8 @@ void USBHD_IRQHandler( void )
/* Setup stage processing */
case USBFS_UIS_TOKEN_SETUP:
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_NAK;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_NAK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_NAK;
/* Store All Setup Values */
USBFS_SetupReqType = pUSBFS_SetupReqPak->bRequestType;
@@ -622,12 +622,12 @@ void USBHD_IRQHandler( void )
{
case ( DEF_UEP_IN | DEF_UEP1 ):
/* Set End-point 1 OUT ACK */
USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
break;
case ( DEF_UEP_IN | DEF_UEP2 ):
/* Set End-point 2 IN NAK */
USBOTG_FS->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK;
break;
default:
@@ -676,11 +676,11 @@ void USBHD_IRQHandler( void )
switch( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) )
{
case ( DEF_UEP_IN | DEF_UEP1 ):
USBOTG_FS->UEP1_TX_CTRL = ( USBOTG_FS->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
USBFSD->UEP1_TX_CTRL = ( USBFSD->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
break;
case ( DEF_UEP_IN | DEF_UEP2 ):
USBOTG_FS->UEP2_TX_CTRL = ( USBOTG_FS->UEP2_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
USBFSD->UEP2_TX_CTRL = ( USBFSD->UEP2_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
break;
default:
@@ -730,14 +730,14 @@ void USBHD_IRQHandler( void )
{
if( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) == ( DEF_UEP_IN | DEF_UEP1 ) )
{
if( ( USBOTG_FS->UEP1_TX_CTRL & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
if( ( USBFSD->UEP1_TX_CTRL & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
{
USBFS_EP0_Buf[ 0 ] = 0x01;
}
}
else if( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) == ( DEF_UEP_IN | DEF_UEP2 ) )
{
if( ( USBOTG_FS->UEP2_TX_CTRL & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
if( ( USBFSD->UEP2_TX_CTRL & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
{
USBFS_EP0_Buf[ 0 ] = 0x01;
}
@@ -767,8 +767,8 @@ void USBHD_IRQHandler( void )
if( errflag == 0xFF )
{
/* if one request not support, return stall */
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL;
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL;
}
else
{
@@ -777,32 +777,28 @@ void USBHD_IRQHandler( void )
{
len = ( USBFS_SetupReqLen > DEF_USBD_UEP0_SIZE )? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen;
USBFS_SetupReqLen -= len;
USBOTG_FS->UEP0_TX_LEN = len;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
USBFSD->UEP0_TX_LEN = len;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
}
else
{
if( USBFS_SetupReqLen == 0 )
{
USBOTG_FS->UEP0_TX_LEN = 0;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
USBFSD->UEP0_TX_LEN = 0;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
}
else
{
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
}
}
}
break;
/* Sof pack processing */
case USBFS_UIS_TOKEN_SOF:
break;
default :
break;
}
USBOTG_FS->INT_FG = USBFS_UIF_TRANSFER;
USBFSD->INT_FG = USBFS_UIF_TRANSFER;
}
else if( intflag & USBFS_UIF_BUS_RST )
{
@@ -812,16 +808,16 @@ void USBHD_IRQHandler( void )
USBFS_DevSleepStatus = 0;
USBFS_DevEnumStatus = 0;
USBOTG_FS->DEV_ADDR = 0;
USBFSD->DEV_ADDR = 0;
USBFS_Device_Endp_Init( );
USBOTG_FS->INT_FG = USBFS_UIF_BUS_RST;
USBFSD->INT_FG = USBFS_UIF_BUS_RST;
}
else if( intflag & USBFS_UIF_SUSPEND )
{
USBOTG_FS->INT_FG = USBFS_UIF_SUSPEND;
USBFSD->INT_FG = USBFS_UIF_SUSPEND;
Delay_Us(10);
/* usb suspend interrupt processing */
if( USBOTG_FS->MIS_ST & USBFS_UMS_SUSPEND )
if( USBFSD->MIS_ST & USBFS_UMS_SUSPEND )
{
USBFS_DevSleepStatus |= 0x02;
if( USBFS_DevSleepStatus == 0x03 )
@@ -838,7 +834,7 @@ void USBHD_IRQHandler( void )
else
{
/* other interrupts */
USBOTG_FS->INT_FG = intflag;
USBFSD->INT_FG = intflag;
}
}
@@ -852,8 +848,8 @@ void USBHD_IRQHandler( void )
*/
void USBFS_Send_Resume( void )
{
USBOTG_FS->UDEV_CTRL ^= USBFS_UD_LOW_SPEED;
USBFSD->UDEV_CTRL ^= USBFS_UD_LOW_SPEED;
Delay_Ms( 8 );
USBOTG_FS->UDEV_CTRL ^= USBFS_UD_LOW_SPEED;
USBFSD->UDEV_CTRL ^= USBFS_UD_LOW_SPEED;
Delay_Ms( 1 );
}
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/main.c
+3 -3
View File
@@ -46,7 +46,7 @@
int main( void )
{
/* Initialize system configuration */
NVIC_PriorityGroupConfig( NVIC_PriorityGroup_2 );
NVIC_PriorityGroupConfig( NVIC_PriorityGroup_1 );
Delay_Init( );
USART_Printf_Init( 115200 );
printf( "SystemClk:%d\r\n", SystemCoreClock );
@@ -69,12 +69,12 @@ int main( void )
TIM3_Init( 1, SystemCoreClock / 10000 - 1 );
printf( "TIM3 Init OK!\r\n" );
/* Initialize USBHD interface to communicate with the host */
/* Initialize USBFS interface to communicate with the host */
USBFS_RCC_Init( );
USBFS_Device_Init( ENABLE );
USB_Sleep_Wakeup_CFG( );
printf("USBHD Composite KM Device Test\r\n");
printf("USBFS Composite KM Device Test\r\n");
while( 1 )
{
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/usbd_compostie_km.c
+2 -2
View File
@@ -71,7 +71,7 @@ void TIM3_Init( uint16_t arr, uint16_t psc )
NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init( &NVIC_InitStructure );
@@ -137,7 +137,7 @@ void USART2_Init( uint32_t baudrate )
NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init( &NVIC_InitStructure );