bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-02-26 13:22:09 +08:00
parent 0ad592325e
commit 9596a13c17
573 changed files with 36301 additions and 23003 deletions
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EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/UART/UART.c
+17 -17
View File
@@ -323,9 +323,9 @@ void UART2_USB_Init( void )
UART2_Init( 0, baudrate, stopbits, parity );
/* restart usb receive */
USBOTG_FS->UEP2_DMA = (uint32_t)(uint8_t *)&UART2_Tx_Buf[ 0 ];
USBOTG_FS->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK;
USBOTG_FS->UEP2_RX_CTRL |= USBFS_UEP_R_RES_ACK;
USBFSD->UEP2_DMA = (uint32_t)(uint8_t *)&UART2_Tx_Buf[ 0 ];
USBFSD->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK;
USBFSD->UEP2_RX_CTRL |= USBFS_UEP_R_RES_ACK;
}
/*********************************************************************
@@ -350,8 +350,8 @@ void UART2_DataTx_Deal( void )
Uart.Tx_Flag = 0x00;
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
/* Calculate the variables of last data */
count = Uart.Tx_CurPackLen - DEF_UART2_TX_DMA_CH->CNTR;
@@ -371,12 +371,12 @@ void UART2_DataTx_Deal( void )
/* If the current serial port has suspended the downlink, restart the driver downlink */
if( ( Uart.USB_Down_StopFlag == 0x01 ) && ( Uart.Tx_RemainNum < 2 ) )
{
USBOTG_FS->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK;
USBOTG_FS->UEP2_RX_CTRL |= USBFS_UEP_R_RES_ACK;
USBFSD->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK;
USBFSD->UEP2_RX_CTRL |= USBFS_UEP_R_RES_ACK;
Uart.USB_Down_StopFlag = 0x00;
}
NVIC_EnableIRQ( USBHD_IRQn );
NVIC_EnableIRQ( USBFS_IRQn );
}
}
else
@@ -416,8 +416,8 @@ void UART2_DataRx_Deal( void )
uint16_t packlen;
/* Serial port 1 data DMA receive processing */
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
UARTx_Rx_DMACurCount = DEF_UART2_RX_DMA_CH->CNTR;
if( UARTx_Rx_DMALastCount != UARTx_Rx_DMACurCount )
@@ -446,7 +446,7 @@ void UART2_DataRx_Deal( void )
/* Setting reception status */
Uart.Rx_TimeOut = 0x00;
}
NVIC_EnableIRQ( USBHD_IRQn );
NVIC_EnableIRQ( USBFS_IRQn );
/*****************************************************************/
/* Serial port 1 data processing via USB upload and reception */
@@ -476,8 +476,8 @@ void UART2_DataRx_Deal( void )
/* Upload serial data via usb */
if( packlen )
{
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
Uart.USB_Up_IngFlag = 0x01;
Uart.USB_Up_TimeOut = 0x00;
USBFS_Endp_DataUp( DEF_UEP3, &UART2_Rx_Buf[ Uart.Rx_DealPtr ], packlen, DEF_UEP_CPY_LOAD );
@@ -495,7 +495,7 @@ void UART2_DataRx_Deal( void )
Uart.USB_Up_Pack0_Flag = 0x01;
}
NVIC_EnableIRQ( USBHD_IRQn );
NVIC_EnableIRQ( USBFS_IRQn );
}
}
else
@@ -517,14 +517,14 @@ void UART2_DataRx_Deal( void )
{
if( Uart.USB_Up_TimeOut >= ( DEF_UARTx_RX_TIMEOUT * 20 ) )
{
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBHD_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
NVIC_DisableIRQ( USBFS_IRQn );
Uart.USB_Up_IngFlag = 0x01;
Uart.USB_Up_TimeOut = 0x00;
USBFS_Endp_DataUp( DEF_UEP3, &UART2_Rx_Buf[ Uart.Rx_DealPtr ], 0, DEF_UEP_CPY_LOAD );
Uart.USB_Up_IngFlag = 0;
Uart.USB_Up_Pack0_Flag = 0x00;
NVIC_EnableIRQ( USBHD_IRQn );
NVIC_EnableIRQ( USBFS_IRQn );
}
}
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c
+72 -75
View File
@@ -3,7 +3,7 @@
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/20
* Description : This file provides all the USBOTG firmware functions.
* Description : This file provides all the USBFS firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
@@ -41,12 +41,12 @@ volatile uint8_t USBFS_Endp_Busy[ DEF_UEP_NUM ];
/******************************************************************************/
/* Interrupt Service Routine Declaration*/
void USBHD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Initializes the usbotg clock configuration.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
@@ -64,7 +64,7 @@ void USBFS_RCC_Init( void )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE );
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
/*********************************************************************
@@ -77,24 +77,24 @@ void USBFS_RCC_Init( void )
void USBFS_Device_Endp_Init( void )
{
USBOTG_FS->UEP4_1_MOD = USBFS_UEP1_TX_EN;
USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_RX_EN|USBFS_UEP3_TX_EN;
USBFSD->UEP4_1_MOD = USBFS_UEP1_TX_EN;
USBFSD->UEP2_3_MOD = USBFS_UEP2_RX_EN|USBFS_UEP3_TX_EN;
USBOTG_FS->UEP0_DMA = (uint32_t)USBFS_EP0_Buf;
USBFSD->UEP0_DMA = (uint32_t)USBFS_EP0_Buf;
USBOTG_FS->UEP1_DMA = (uint32_t)USBFS_EP1_Buf;
USBOTG_FS->UEP2_DMA = (uint32_t)UART2_Tx_Buf;
USBOTG_FS->UEP3_DMA = (uint32_t)USBFS_EP3_Buf;
USBFSD->UEP1_DMA = (uint32_t)USBFS_EP1_Buf;
USBFSD->UEP2_DMA = (uint32_t)UART2_Tx_Buf;
USBFSD->UEP3_DMA = (uint32_t)USBFS_EP3_Buf;
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBOTG_FS->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBFSD->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBOTG_FS->UEP1_TX_LEN = 0;
USBOTG_FS->UEP3_TX_LEN = 0;
USBFSD->UEP1_TX_LEN = 0;
USBFSD->UEP3_TX_LEN = 0;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
/* Clear End-points Busy Status */
for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
@@ -114,21 +114,21 @@ void USBFS_Device_Init( FunctionalState sta )
{
if( sta )
{
USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
USBFSH->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
Delay_Us( 10 );
USBOTG_H_FS->BASE_CTRL = 0x00;
USBOTG_FS->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER;
USBOTG_FS->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
USBFSH->BASE_CTRL = 0x00;
USBFSD->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER;
USBFSD->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
USBFS_Device_Endp_Init( );
USBOTG_FS->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN;
NVIC_EnableIRQ( USBHD_IRQn );
USBFSD->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN;
NVIC_EnableIRQ( USBFS_IRQn );
}
else
{
USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
USBFSH->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
Delay_Us( 10 );
USBOTG_FS->BASE_CTRL = 0x00;
NVIC_DisableIRQ( USBHD_IRQn );
USBFSD->BASE_CTRL = 0x00;
NVIC_DisableIRQ( USBFS_IRQn );
}
}
@@ -232,20 +232,20 @@ uint8_t USBFS_Endp_DataUp(uint8_t endp, uint8_t *pbuf, uint16_t len, uint8_t mod
/*********************************************************************
* @fn USBHD_IRQHandler
* @fn USBFS_IRQHandler
*
* @brief This function handles HD-FS exception.
*
* @return none
*/
void USBHD_IRQHandler( void )
void USBFS_IRQHandler( void )
{
uint8_t intflag, intst, errflag;
uint16_t len;
uint32_t baudrate;
intflag = USBOTG_FS->INT_FG;
intst = USBOTG_FS->INT_ST;
intflag = USBFSD->INT_FG;
intst = USBFSD->INT_ST;
if( intflag & USBFS_UIF_TRANSFER )
{
@@ -259,7 +259,7 @@ void USBHD_IRQHandler( void )
case USBFS_UIS_TOKEN_IN | DEF_UEP0:
if( USBFS_SetupReqLen == 0 )
{
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
}
if ( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD )
{
@@ -275,12 +275,12 @@ void USBHD_IRQHandler( void )
memcpy( USBFS_EP0_Buf, pUSBFS_Descr, len );
USBFS_SetupReqLen -= len;
pUSBFS_Descr += len;
USBOTG_FS->UEP0_TX_LEN = len;
USBOTG_FS->UEP0_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFSD->UEP0_TX_LEN = len;
USBFSD->UEP0_TX_CTRL ^= USBFS_UEP_T_TOG;
break;
case USB_SET_ADDRESS:
USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR & USBFS_UDA_GP_BIT) | USBFS_DevAddr;
USBFSD->DEV_ADDR = (USBFSD->DEV_ADDR & USBFS_UDA_GP_BIT) | USBFS_DevAddr;
break;
default:
@@ -291,15 +291,15 @@ void USBHD_IRQHandler( void )
/* end-point 1 data in interrupt */
case ( USBFS_UIS_TOKEN_IN | DEF_UEP1 ):
USBOTG_FS->UEP1_TX_CTRL ^= USBFS_UEP_T_TOG;
USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK;
USBFSD->UEP1_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFSD->UEP1_TX_CTRL = (USBFSD->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK;
USBFS_Endp_Busy[ DEF_UEP1 ] = 0;
break;
/* end-point 3 data in interrupt */
case ( USBFS_UIS_TOKEN_IN | DEF_UEP3 ):
USBOTG_FS->UEP3_TX_CTRL ^= USBFS_UEP_T_TOG;
USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK;
USBFSD->UEP3_TX_CTRL ^= USBFS_UEP_T_TOG;
USBFSD->UEP3_TX_CTRL = (USBFSD->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK;
USBFS_Endp_Busy[ DEF_UEP3 ] = 0;
Uart.USB_Up_IngFlag = 0x00;
break;
@@ -315,7 +315,7 @@ void USBHD_IRQHandler( void )
{
/* end-point 0 data out interrupt */
case USBFS_UIS_TOKEN_OUT | DEF_UEP0:
len = USBOTG_FS->RX_LEN;
len = USBFSD->RX_LEN;
if ( intst & USBFS_UIS_TOG_OK )
{
if ( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD )
@@ -356,28 +356,28 @@ void USBHD_IRQHandler( void )
}
if( USBFS_SetupReqLen == 0 )
{
USBOTG_FS->UEP0_TX_LEN = 0;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
USBFSD->UEP0_TX_LEN = 0;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
}
}
break;
/* end-point 1 data out interrupt */
case USBFS_UIS_TOKEN_OUT | DEF_UEP2:
USBOTG_FS->UEP2_RX_CTRL ^= USBFS_UEP_R_TOG;
Uart.Tx_PackLen[ Uart.Tx_LoadNum ] = USBOTG_FS->RX_LEN;
USBFSD->UEP2_RX_CTRL ^= USBFS_UEP_R_TOG;
Uart.Tx_PackLen[ Uart.Tx_LoadNum ] = USBFSD->RX_LEN;
Uart.Tx_LoadNum++;
USBOTG_FS->UEP2_DMA = (uint32_t)(uint8_t *)&UART2_Tx_Buf[ ( Uart.Tx_LoadNum * DEF_USB_FS_PACK_LEN ) ];
USBFSD->UEP2_DMA = (uint32_t)(uint8_t *)&UART2_Tx_Buf[ ( Uart.Tx_LoadNum * DEF_USB_FS_PACK_LEN ) ];
if( Uart.Tx_LoadNum >= DEF_UARTx_TX_BUF_NUM_MAX )
{
Uart.Tx_LoadNum = 0x00;
USBOTG_FS->UEP2_DMA = (uint32_t)(uint8_t *)&UART2_Tx_Buf[ 0 ];
USBFSD->UEP2_DMA = (uint32_t)(uint8_t *)&UART2_Tx_Buf[ 0 ];
}
Uart.Tx_RemainNum++;
if( Uart.Tx_RemainNum >= ( DEF_UARTx_TX_BUF_NUM_MAX - 2 ) )
{
USBOTG_FS->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK;
USBOTG_FS->UEP2_RX_CTRL |= USBFS_UEP_R_RES_NAK;
USBFSD->UEP2_RX_CTRL &= ~USBFS_UEP_R_RES_MASK;
USBFSD->UEP2_RX_CTRL |= USBFS_UEP_R_RES_NAK;
Uart.USB_Down_StopFlag = 0x01;
}
break;
@@ -389,8 +389,8 @@ void USBHD_IRQHandler( void )
/* Setup stage processing */
case USBFS_UIS_TOKEN_SETUP:
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_NAK;
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_NAK;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_NAK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_NAK;
/* Store All Setup Values */
USBFS_SetupReqType = pUSBFS_SetupReqPak->bRequestType;
USBFS_SetupReqCode = pUSBFS_SetupReqPak->bRequest;
@@ -550,17 +550,17 @@ void USBHD_IRQHandler( void )
{
case ( DEF_UEP_IN | DEF_UEP1 ):
/* Set End-point 1 IN NAK */
USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
break;
case ( DEF_UEP_OUT | DEF_UEP2 ):
/* Set End-point 2 OUT ACK */
USBOTG_FS->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK;
USBFSD->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK;
break;
case ( DEF_UEP_IN | DEF_UEP3 ):
/* Set End-point 3 IN NAK */
USBOTG_FS->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
USBFSD->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
break;
default:
@@ -611,17 +611,17 @@ void USBHD_IRQHandler( void )
{
case ( DEF_UEP_IN | DEF_UEP1 ):
/* Set End-point 1 IN STALL */
USBOTG_FS->UEP1_TX_CTRL = ( USBOTG_FS->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
USBFSD->UEP1_TX_CTRL = ( USBFSD->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
break;
case ( DEF_UEP_OUT | DEF_UEP2 ):
/* Set End-point 2 OUT STALL */
USBOTG_FS->UEP2_RX_CTRL = ( USBOTG_FS->UEP2_RX_CTRL & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_STALL;
USBFSD->UEP2_RX_CTRL = ( USBFSD->UEP2_RX_CTRL & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_STALL;
break;
case ( DEF_UEP_IN | DEF_UEP3 ):
/* Set End-point 3 IN STALL */
USBOTG_FS->UEP3_TX_CTRL = ( USBOTG_FS->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
USBFSD->UEP3_TX_CTRL = ( USBFSD->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
break;
default:
@@ -668,21 +668,21 @@ void USBHD_IRQHandler( void )
switch( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) )
{
case ( DEF_UEP_IN | DEF_UEP1 ):
if( ( (USBOTG_FS->UEP1_TX_CTRL) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
if( ( (USBFSD->UEP1_TX_CTRL) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
{
USBFS_EP0_Buf[ 0 ] = 0x01;
}
break;
case ( DEF_UEP_OUT | DEF_UEP2 ):
if( ( (USBOTG_FS->UEP2_RX_CTRL) & USBFS_UEP_R_RES_MASK ) == USBFS_UEP_R_RES_STALL )
if( ( (USBFSD->UEP2_RX_CTRL) & USBFS_UEP_R_RES_MASK ) == USBFS_UEP_R_RES_STALL )
{
USBFS_EP0_Buf[ 0 ] = 0x01;
}
break;
case ( DEF_UEP_IN | DEF_UEP3 ):
if( ( (USBOTG_FS->UEP3_TX_CTRL) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
if( ( (USBFSD->UEP3_TX_CTRL) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
{
USBFS_EP0_Buf[ 0 ] = 0x01;
}
@@ -714,8 +714,8 @@ void USBHD_IRQHandler( void )
if( errflag == 0xff)
{
/* if one request not support, return stall */
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_STALL;
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_STALL;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_STALL;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_STALL;
}
else
{
@@ -725,33 +725,29 @@ void USBHD_IRQHandler( void )
/* tx */
len = (USBFS_SetupReqLen>DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen;
USBFS_SetupReqLen -= len;
USBOTG_FS->UEP0_TX_LEN = len;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK;
USBFSD->UEP0_TX_LEN = len;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK;
}
else
{
/* rx */
if( USBFS_SetupReqLen == 0 )
{
USBOTG_FS->UEP0_TX_LEN = 0;
USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK;
USBFSD->UEP0_TX_LEN = 0;
USBFSD->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK;
}
else
{
USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_ACK;
USBFSD->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_ACK;
}
}
}
break;
/* Sof pack processing */
case USBFS_UIS_TOKEN_SOF:
break;
default :
break;
}
USBOTG_FS->INT_FG = USBFS_UIF_TRANSFER;
USBFSD->INT_FG = USBFS_UIF_TRANSFER;
}
else if( intflag & USBFS_UIF_BUS_RST )
{
@@ -761,15 +757,17 @@ void USBHD_IRQHandler( void )
USBFS_DevSleepStatus = 0;
USBFS_DevEnumStatus = 0;
USBOTG_FS->DEV_ADDR = 0;
USBFSD->DEV_ADDR = 0;
USBFS_Device_Endp_Init( );
UART2_ParaInit( 1 );
USBOTG_FS->INT_FG = USBFS_UIF_BUS_RST;
USBFSD->INT_FG = USBFS_UIF_BUS_RST;
}
else if( intflag & USBFS_UIF_SUSPEND )
{
USBFSD->INT_FG = USBFS_UIF_SUSPEND;
Delay_Us(10);
/* usb suspend interrupt processing */
if ( USBOTG_FS->MIS_ST & USBFS_UMS_SUSPEND )
if ( USBFSD->MIS_ST & USBFS_UMS_SUSPEND )
{
USBFS_DevSleepStatus |= 0x02;
if( USBFS_DevSleepStatus == 0x03 )
@@ -781,12 +779,11 @@ void USBHD_IRQHandler( void )
{
USBFS_DevSleepStatus &= ~0x02;
}
USBOTG_FS->INT_FG = USBFS_UIF_SUSPEND;
}
else
{
/* other interrupts */
USBOTG_FS->INT_FG = intflag;
USBFSD->INT_FG = intflag;
}
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.h
+1 -1
View File
@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2022/08/20
* Description : This file contains all the functions prototypes for the
* USBOTG firmware library.
* USBFS firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/ch32v20x_it.c
+3
View File
@@ -25,6 +25,9 @@ void TIM2_IRQHandler( void )__attribute__((interrupt("WCH-Interrupt-fast")));
*/
void NMI_Handler(void)
{
while (1)
{
}
}
/*********************************************************************
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/system_ch32v20x.c
+2 -2
View File
@@ -111,10 +111,10 @@ static void SetSysClockTo144_HSI( void );
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}