V2.2

EVT/EXAM/BLE/BLE_UART/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/BLE_USB/APP/ch32v20x_usbfs_device.c

@@ -185,11 +185,29 @@ void USBDeviceInit(void)
  *
  * @return  none
  */
-void USBFS_RCC_Init(void)
+void USBFS_RCC_Init( void )
 {
-    RCC->CFGR2 &= ~RCC_USBFS_CLK_SRC; //usbfs clock selection: 0 = systick, 1 = usb20_phy
-    RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div2);
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBFS, ENABLE);
+    RCC_ClocksTypeDef RCC_ClocksStatus={0};
+    RCC_GetClocksFreq(&RCC_ClocksStatus);
+    if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
+    }
+    else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) 
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
+    }
+    else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) 
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
+    }
+#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
+    else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
+    }
+#endif
+    RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
 }
 
 /*********************************************************************

EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/BackupUpgrade_IAP/APP/ch32v20x_it.c

@@ -42,6 +42,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/BackupUpgrade_IAP/Ld/Link.ld

@@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size );
 
 MEMORY
 {  
-/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
 /*
 	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
 	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K

EVT/EXAM/BLE/BackupUpgrade_IAP/Startup/startup_ch32v20x_D8W.S

@@ -93,8 +93,8 @@ _vector_base:
     .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
-    .word   USBHD_IRQHandler           /* USBHD Break */
-    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   USBFS_IRQHandler           /* USBFS Break */
+    .word   USBFSWakeUp_IRQHandler     /* USBFS Wake up from suspend */
     .word   ETH_IRQHandler             /* ETH global */
     .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
     .word   BB_IRQHandler              /* BLE BB */
@@ -158,8 +158,8 @@ _vector_base:
     .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
-    .weak   USBHD_IRQHandler           /* USBHD */
-    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   USBFS_IRQHandler           /* USBFS */
+    .weak   USBFSWakeUp_IRQHandler     /* USBFS Wake Up */
     .weak   ETH_IRQHandler             /* ETH global */
     .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
     .weak   BB_IRQHandler              /* BB */
@@ -220,8 +220,8 @@ USART3_IRQHandler:  1:  j 1b
 EXTI15_10_IRQHandler:  1:  j 1b
 RTCAlarm_IRQHandler:  1:  j 1b
 USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
+USBFS_IRQHandler:  1:  j 1b
+USBFSWakeUp_IRQHandler:  1:  j 1b
 ETH_IRQHandler:  1:  j 1b
 ETHWakeUp_IRQHandler:  1:  j 1b
 BB_IRQHandler:  1:  j 1b

EVT/EXAM/BLE/BackupUpgrade_OTA/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/BackupUpgrade_OTA/Ld/Link.ld

@@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size );
 
 MEMORY
 {  
-/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
 /*
 	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
 	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K

EVT/EXAM/BLE/BackupUpgrade_OTA/Startup/startup_ch32v20x_D8W.S

@@ -93,8 +93,8 @@ _vector_base:
     .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
-    .word   USBHD_IRQHandler           /* USBHD Break */
-    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   USBFS_IRQHandler           /* USBFS Break */
+    .word   USBFSWakeUp_IRQHandler     /* USBFS Wake up from suspend */
     .word   ETH_IRQHandler             /* ETH global */
     .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
     .word   BB_IRQHandler              /* BLE BB */
@@ -158,8 +158,8 @@ _vector_base:
     .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
-    .weak   USBHD_IRQHandler           /* USBHD */
-    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   USBFS_IRQHandler           /* USBFS */
+    .weak   USBFSWakeUp_IRQHandler     /* USBFS Wake Up */
     .weak   ETH_IRQHandler             /* ETH global */
     .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
     .weak   BB_IRQHandler              /* BB */
@@ -220,8 +220,8 @@ USART3_IRQHandler:  1:  j 1b
 EXTI15_10_IRQHandler:  1:  j 1b
 RTCAlarm_IRQHandler:  1:  j 1b
 USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
+USBFS_IRQHandler:  1:  j 1b
+USBFSWakeUp_IRQHandler:  1:  j 1b
 ETH_IRQHandler:  1:  j 1b
 ETHWakeUp_IRQHandler:  1:  j 1b
 BB_IRQHandler:  1:  j 1b

EVT/EXAM/BLE/Broadcaster/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/CentPeri/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/Central/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/Central/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/CyclingSensor/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c

@@ -53,18 +53,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  */
 void USBFS_RCC_Init( void )
 {
-    if( SystemCoreClock == 144000000 )
+    RCC_ClocksTypeDef RCC_ClocksStatus={0};
+    RCC_GetClocksFreq(&RCC_ClocksStatus);
+    if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
     {
         RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
     }
-    else if( SystemCoreClock == 96000000 )
+    else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 ) 
     {
         RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
     }
-    else if( SystemCoreClock == 48000000 )
+    else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 ) 
     {
         RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
     }
+#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
+    else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
+    }
+#endif
     RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
 }
 

EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/HAL/Link.ld

@@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size );
 
 MEMORY
 {  
-/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
 /*
 	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
 	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K

EVT/EXAM/BLE/HID_Consumer/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/HID_Keyboard/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/HID_Mouse/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/HID_Touch/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/HeartRate/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/LWNS/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_ali_light/APP/app_main.c

@@ -95,6 +95,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_ali_light/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/app_main.c

@@ -95,6 +95,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/app_main.c

@@ -95,6 +95,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/app_main.c

@@ -95,6 +95,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/app_main.c

@@ -95,6 +95,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_proxy/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_proxy/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_vendor/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/ch32v20x_it.c

@@ -42,6 +42,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Ld/Link.ld

@@ -7,7 +7,7 @@ PROVIDE( _stack_size = __stack_size );
 
 MEMORY
 {  
-/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
 /*
 	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
 	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/Startup/startup_ch32v20x_D8W.S

@@ -93,8 +93,8 @@ _vector_base:
     .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
-    .word   USBHD_IRQHandler           /* USBHD Break */
-    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   USBFS_IRQHandler           /* USBFS Break */
+    .word   USBFSWakeUp_IRQHandler     /* USBFS Wake up from suspend */
     .word   ETH_IRQHandler             /* ETH global */
     .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
     .word   BB_IRQHandler              /* BLE BB */
@@ -158,8 +158,8 @@ _vector_base:
     .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
-    .weak   USBHD_IRQHandler           /* USBHD */
-    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   USBFS_IRQHandler           /* USBFS */
+    .weak   USBFSWakeUp_IRQHandler     /* USBFS Wake Up */
     .weak   ETH_IRQHandler             /* ETH global */
     .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
     .weak   BB_IRQHandler              /* BB */
@@ -220,8 +220,8 @@ USART3_IRQHandler:  1:  j 1b
 EXTI15_10_IRQHandler:  1:  j 1b
 RTCAlarm_IRQHandler:  1:  j 1b
 USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
+USBFS_IRQHandler:  1:  j 1b
+USBFSWakeUp_IRQHandler:  1:  j 1b
 ETH_IRQHandler:  1:  j 1b
 ETHWakeUp_IRQHandler:  1:  j 1b
 BB_IRQHandler:  1:  j 1b

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Ld/Link.ld

@@ -1 +1,202 @@
-ENTRY( _start )

__stack_size = 2048;

PROVIDE( _stack_size = __stack_size );


MEMORY
{  
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/ 

/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
*/ 
  
/* CH32V20x_D8 - CH32V203RB
   CH32V20x_D8W - CH32V208x
   FLASH + RAM supports the following configuration
   FLASH-128K + RAM-64K
   FLASH-144K + RAM-48K
   FLASH-160K + RAM-32K
*/
	FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 152K
	RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K

}

    PROVIDE( __global_pointer$ = 0x20004000 );

SECTIONS
{

	.init :
	{
		_sinit = .;
		. = ALIGN(4);
		KEEP(*(SORT_NONE(.init)))
		KEEP(*(.ImageFlag))
		KEEP(*(.ImageFlag.*))
		. = ALIGN(4);
		_einit = .;
	} >FLASH AT>FLASH

  .vector :
  {
      *(.vector);
	  . = ALIGN(64);
		KEEP(*(SORT_NONE(.handle_reset)))
  } >FLASH AT>FLASH
  
     .highcode : 
    {
        . = ALIGN(4);
        *(.highcode);
        *(.highcode.*);
		. = ALIGN(4); 
    } >FLASH AT>FLASH
    
	.text :
	{
		. = ALIGN(4);
		*(.text)
		*(.text.*)
		*(.rodata)
		*(.rodata*)
        *(.sdata2.*)
		*(.gnu.linkonce.t.*)
		. = ALIGN(4);
	} >FLASH AT>FLASH 

	.fini :
	{
		KEEP(*(SORT_NONE(.fini)))
		. = ALIGN(4);
	} >FLASH AT>FLASH

	PROVIDE( _etext = . );
	PROVIDE( _eitcm = . );	

	.preinit_array  :
	{
	  PROVIDE_HIDDEN (__preinit_array_start = .);
	  KEEP (*(.preinit_array))
	  PROVIDE_HIDDEN (__preinit_array_end = .);
	} >FLASH AT>FLASH 
	
	.init_array     :
	{
	  PROVIDE_HIDDEN (__init_array_start = .);
	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
	  PROVIDE_HIDDEN (__init_array_end = .);
	} >FLASH AT>FLASH 
	
	.fini_array     :
	{
	  PROVIDE_HIDDEN (__fini_array_start = .);
	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
	  PROVIDE_HIDDEN (__fini_array_end = .);
	} >FLASH AT>FLASH 
	
	.ctors          :
	{
	  /* gcc uses crtbegin.o to find the start of
	     the constructors, so we make sure it is
	     first.  Because this is a wildcard, it
	     doesn't matter if the user does not
	     actually link against crtbegin.o; the
	     linker won't look for a file to match a
	     wildcard.  The wildcard also means that it
	     doesn't matter which directory crtbegin.o
	     is in.  */
	  KEEP (*crtbegin.o(.ctors))
	  KEEP (*crtbegin?.o(.ctors))
	  /* We don't want to include the .ctor section from
	     the crtend.o file until after the sorted ctors.
	     The .ctor section from the crtend file contains the
	     end of ctors marker and it must be last */
	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
	  KEEP (*(SORT(.ctors.*)))
	  KEEP (*(.ctors))
	} >FLASH AT>FLASH 
	
	.dtors          :
	{
	  KEEP (*crtbegin.o(.dtors))
	  KEEP (*crtbegin?.o(.dtors))
	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
	  KEEP (*(SORT(.dtors.*)))
	  KEEP (*(.dtors))
	} >FLASH AT>FLASH 

	.dalign :
	{
		. = ALIGN(4);
		PROVIDE(_data_vma = .);
	} >RAM AT>FLASH	

	.dlalign :
	{
		. = ALIGN(4); 
		PROVIDE(_data_lma = .);
	} >FLASH AT>FLASH

	.data :
	{
    	*(.gnu.linkonce.r.*)
    	*(.data .data.*)
    	*(.gnu.linkonce.d.*)
		. = ALIGN(8);
    	/*PROVIDE( __global_pointer$ = . + 0x800 );*/
    	*(.sdata .sdata.*)
    	*(.gnu.linkonce.s.*)
    	. = ALIGN(8);
    	*(.srodata.cst16)
    	*(.srodata.cst8)
    	*(.srodata.cst4)
    	*(.srodata.cst2)
    	*(.srodata .srodata.*)
    	. = ALIGN(4);
		PROVIDE( _edata = .);
	} >RAM AT>FLASH

	.bss :
	{
		. = ALIGN(4);
		PROVIDE( _sbss = .);
  	    *(.sbss*)
        *(.gnu.linkonce.sb.*)
		*(.bss*)
     	*(.gnu.linkonce.b.*)		
		*(COMMON*)
		. = ALIGN(4);
		PROVIDE( _ebss = .);
	} >RAM AT>FLASH

	PROVIDE( _end = _ebss);
	PROVIDE( end = . );

    /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
    {
        PROVIDE( _heap_end = . );   
        . = ALIGN(4);
        PROVIDE(_susrstack = . );
        . = . + __stack_size;
        PROVIDE( _eusrstack = .);
    } >RAM */

	.stack ORIGIN(RAM)+LENGTH(RAM) :
	{
        PROVIDE( _heap_end = . );   
		. = ALIGN(4);
		PROVIDE(_eusrstack = . );
	} >RAM  
}
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{  
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
+*/ 
+
+/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+*/ 
+  
+/* CH32V20x_D8 - CH32V203RB
+   CH32V20x_D8W - CH32V208x
+   FLASH + RAM supports the following configuration
+   FLASH-128K + RAM-64K
+   FLASH-144K + RAM-48K
+   FLASH-160K + RAM-32K
+*/
+	FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 152K
+	RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K
+
+}
+
+    PROVIDE( __global_pointer$ = 0x20004000 );
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		KEEP(*(.ImageFlag))
+		KEEP(*(.ImageFlag.*))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+		KEEP(*(SORT_NONE(.handle_reset)))
+  } >FLASH AT>FLASH
+  
+     .highcode : 
+    {
+        . = ALIGN(4);
+        *(.highcode);
+        *(.highcode.*);
+		. = ALIGN(4); 
+    } >FLASH AT>FLASH
+    
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+        *(.sdata2.*)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	/*PROVIDE( __global_pointer$ = . + 0x800 );*/
+    	*(.sdata .sdata.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );   
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM */
+
+	.stack ORIGIN(RAM)+LENGTH(RAM) :
+	{
+        PROVIDE( _heap_end = . );   
+		. = ALIGN(4);
+		PROVIDE(_eusrstack = . );
+	} >RAM  
+}

EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/Startup/startup_ch32v20x_D8W.S

@@ -93,8 +93,8 @@ _vector_base:
     .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
-    .word   USBHD_IRQHandler           /* USBHD Break */
-    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   USBFS_IRQHandler           /* USBFS Break */
+    .word   USBFSWakeUp_IRQHandler     /* USBFS Wake up from suspend */
     .word   ETH_IRQHandler             /* ETH global */
     .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
     .word   BB_IRQHandler              /* BLE BB */
@@ -158,8 +158,8 @@ _vector_base:
     .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
-    .weak   USBHD_IRQHandler           /* USBHD */
-    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   USBFS_IRQHandler           /* USBFS */
+    .weak   USBFSWakeUp_IRQHandler     /* USBFS Wake Up */
     .weak   ETH_IRQHandler             /* ETH global */
     .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
     .weak   BB_IRQHandler              /* BB */
@@ -220,8 +220,8 @@ USART3_IRQHandler:  1:  j 1b
 EXTI15_10_IRQHandler:  1:  j 1b
 RTCAlarm_IRQHandler:  1:  j 1b
 USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
+USBFS_IRQHandler:  1:  j 1b
+USBFSWakeUp_IRQHandler:  1:  j 1b
 ETH_IRQHandler:  1:  j 1b
 ETHWakeUp_IRQHandler:  1:  j 1b
 BB_IRQHandler:  1:  j 1b

EVT/EXAM/BLE/MESH/provisioner_vendor/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/provisioner_vendor/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/provisioner_vendor/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/app_main.c

@@ -97,6 +97,7 @@ int main(void)
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
+    PRINT("%s\n", VER_MESH_LIB);
     WCHBLE_Init();
     HAL_Init();
     bt_mesh_lib_init();

EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MESH/provisioner_vendor_with_peripheral/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MultiCentPeri/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/MultiCentral/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/Observer/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/OnlyUpdateApp_IAP/Ld/Link.ld

@@ -1 +1,199 @@
-ENTRY( _start )

__stack_size = 2048;

PROVIDE( _stack_size = __stack_size );


MEMORY
{  
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/ 

/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
*/ 
  
/* CH32V20x_D8 - CH32V203RB
   CH32V20x_D8W - CH32V208x
   FLASH + RAM supports the following configuration
   FLASH-128K + RAM-64K
   FLASH-144K + RAM-48K
   FLASH-160K + RAM-32K
*/
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K
	RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K
}

    PROVIDE( __global_pointer$ = 0x20004000 );

SECTIONS
{

	.init :
	{
		_sinit = .;
		. = ALIGN(4);
		KEEP(*(SORT_NONE(.init)))
		. = ALIGN(4);
		_einit = .;
	} >FLASH AT>FLASH

  .vector :
  {
      *(.vector);
	  . = ALIGN(64);
		KEEP(*(SORT_NONE(.handle_reset)))
  } >FLASH AT>FLASH
  
     .highcode : 
    {
        . = ALIGN(4);
        *(.highcode);
        *(.highcode.*);
		. = ALIGN(4); 
    } >FLASH AT>FLASH
    
	.text :
	{
		. = ALIGN(4);
		*(.text)
		*(.text.*)
		*(.rodata)
		*(.rodata*)
        *(.sdata2.*)
		*(.gnu.linkonce.t.*)
		. = ALIGN(4);
	} >FLASH AT>FLASH 

	.fini :
	{
		KEEP(*(SORT_NONE(.fini)))
		. = ALIGN(4);
	} >FLASH AT>FLASH

	PROVIDE( _etext = . );
	PROVIDE( _eitcm = . );	

	.preinit_array  :
	{
	  PROVIDE_HIDDEN (__preinit_array_start = .);
	  KEEP (*(.preinit_array))
	  PROVIDE_HIDDEN (__preinit_array_end = .);
	} >FLASH AT>FLASH 
	
	.init_array     :
	{
	  PROVIDE_HIDDEN (__init_array_start = .);
	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
	  PROVIDE_HIDDEN (__init_array_end = .);
	} >FLASH AT>FLASH 
	
	.fini_array     :
	{
	  PROVIDE_HIDDEN (__fini_array_start = .);
	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
	  PROVIDE_HIDDEN (__fini_array_end = .);
	} >FLASH AT>FLASH 
	
	.ctors          :
	{
	  /* gcc uses crtbegin.o to find the start of
	     the constructors, so we make sure it is
	     first.  Because this is a wildcard, it
	     doesn't matter if the user does not
	     actually link against crtbegin.o; the
	     linker won't look for a file to match a
	     wildcard.  The wildcard also means that it
	     doesn't matter which directory crtbegin.o
	     is in.  */
	  KEEP (*crtbegin.o(.ctors))
	  KEEP (*crtbegin?.o(.ctors))
	  /* We don't want to include the .ctor section from
	     the crtend.o file until after the sorted ctors.
	     The .ctor section from the crtend file contains the
	     end of ctors marker and it must be last */
	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
	  KEEP (*(SORT(.ctors.*)))
	  KEEP (*(.ctors))
	} >FLASH AT>FLASH 
	
	.dtors          :
	{
	  KEEP (*crtbegin.o(.dtors))
	  KEEP (*crtbegin?.o(.dtors))
	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
	  KEEP (*(SORT(.dtors.*)))
	  KEEP (*(.dtors))
	} >FLASH AT>FLASH 

	.dalign :
	{
		. = ALIGN(4);
		PROVIDE(_data_vma = .);
	} >RAM AT>FLASH	

	.dlalign :
	{
		. = ALIGN(4); 
		PROVIDE(_data_lma = .);
	} >FLASH AT>FLASH

	.data :
	{
    	*(.gnu.linkonce.r.*)
    	*(.data .data.*)
    	*(.gnu.linkonce.d.*)
		. = ALIGN(8);
    	PROVIDE( __global_pointer$ = . + 0x800 );
    	*(.sdata .sdata.*)
    	*(.gnu.linkonce.s.*)
    	. = ALIGN(8);
    	*(.srodata.cst16)
    	*(.srodata.cst8)
    	*(.srodata.cst4)
    	*(.srodata.cst2)
    	*(.srodata .srodata.*)
    	. = ALIGN(4);
		PROVIDE( _edata = .);
	} >RAM AT>FLASH

	.bss :
	{
		. = ALIGN(4);
		PROVIDE( _sbss = .);
  	    *(.sbss*)
        *(.gnu.linkonce.sb.*)
		*(.bss*)
     	*(.gnu.linkonce.b.*)		
		*(COMMON*)
		. = ALIGN(4);
		PROVIDE( _ebss = .);
	} >RAM AT>FLASH

	PROVIDE( _end = _ebss);
	PROVIDE( end = . );

    /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
    {
        PROVIDE( _heap_end = . );   
        . = ALIGN(4);
        PROVIDE(_susrstack = . );
        . = . + __stack_size;
        PROVIDE( _eusrstack = .);
    } >RAM */

	.stack ORIGIN(RAM)+LENGTH(RAM) :
	{
        PROVIDE( _heap_end = . );   
		. = ALIGN(4);
		PROVIDE(_eusrstack = . );
	} >RAM  
}
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{  
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
+*/ 
+
+/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+*/ 
+  
+/* CH32V20x_D8 - CH32V203RB
+   CH32V20x_D8W - CH32V208x
+   FLASH + RAM supports the following configuration
+   FLASH-128K + RAM-64K
+   FLASH-144K + RAM-48K
+   FLASH-160K + RAM-32K
+*/
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K
+	RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K
+}
+
+    PROVIDE( __global_pointer$ = 0x20004000 );
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+		KEEP(*(SORT_NONE(.handle_reset)))
+  } >FLASH AT>FLASH
+  
+     .highcode : 
+    {
+        . = ALIGN(4);
+        *(.highcode);
+        *(.highcode.*);
+		. = ALIGN(4); 
+    } >FLASH AT>FLASH
+    
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+        *(.sdata2.*)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );   
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM */
+
+	.stack ORIGIN(RAM)+LENGTH(RAM) :
+	{
+        PROVIDE( _heap_end = . );   
+		. = ALIGN(4);
+		PROVIDE(_eusrstack = . );
+	} >RAM  
+}

EVT/EXAM/BLE/OnlyUpdateApp_IAP/Startup/startup_ch32v20x_D8W.S

@@ -93,8 +93,8 @@ _vector_base:
     .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
-    .word   USBHD_IRQHandler           /* USBHD Break */
-    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   USBFS_IRQHandler           /* USBFS Break */
+    .word   USBFSWakeUp_IRQHandler     /* USBFS Wake up from suspend */
     .word   ETH_IRQHandler             /* ETH global */
     .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
     .word   BB_IRQHandler              /* BLE BB */
@@ -158,8 +158,8 @@ _vector_base:
     .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
-    .weak   USBHD_IRQHandler           /* USBHD */
-    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   USBFS_IRQHandler           /* USBFS */
+    .weak   USBFSWakeUp_IRQHandler     /* USBFS Wake Up */
     .weak   ETH_IRQHandler             /* ETH global */
     .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
     .weak   BB_IRQHandler              /* BB */
@@ -220,8 +220,8 @@ USART3_IRQHandler:  1:  j 1b
 EXTI15_10_IRQHandler:  1:  j 1b
 RTCAlarm_IRQHandler:  1:  j 1b
 USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
+USBFS_IRQHandler:  1:  j 1b
+USBFSWakeUp_IRQHandler:  1:  j 1b
 ETH_IRQHandler:  1:  j 1b
 ETHWakeUp_IRQHandler:  1:  j 1b
 BB_IRQHandler:  1:  j 1b

EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Ld/Link.ld

@@ -1 +1,201 @@
-ENTRY( _start )

__stack_size = 2048;

PROVIDE( _stack_size = __stack_size );


MEMORY
{  
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/ 

/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/*
	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
*/ 
  
/* CH32V20x_D8 - CH32V203RB
   CH32V20x_D8W - CH32V208x
   FLASH + RAM supports the following configuration
   FLASH-128K + RAM-64K
   FLASH-144K + RAM-48K
   FLASH-160K + RAM-32K
*/
	FLASH (rx) : ORIGIN = 0x00004000, LENGTH = 240K
	RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K
}

    PROVIDE( __global_pointer$ = 0x20004000 );

SECTIONS
{

	.init :
	{
		_sinit = .;
		. = ALIGN(4);
		KEEP(*(SORT_NONE(.init)))
		KEEP(*(.ImageFlag))
		KEEP(*(.ImageFlag.*))
		. = ALIGN(4);
		_einit = .;
	} >FLASH AT>FLASH

  .vector :
  {
      *(.vector);
	  . = ALIGN(64);
		KEEP(*(SORT_NONE(.handle_reset)))
  } >FLASH AT>FLASH
  
     .highcode : 
    {
        . = ALIGN(4);
        *(.highcode);
        *(.highcode.*);
		. = ALIGN(4); 
    } >FLASH AT>FLASH
    
	.text :
	{
		. = ALIGN(4);
		*(.text)
		*(.text.*)
		*(.rodata)
		*(.rodata*)
        *(.sdata2.*)
		*(.gnu.linkonce.t.*)
		. = ALIGN(4);
	} >FLASH AT>FLASH 

	.fini :
	{
		KEEP(*(SORT_NONE(.fini)))
		. = ALIGN(4);
	} >FLASH AT>FLASH

	PROVIDE( _etext = . );
	PROVIDE( _eitcm = . );	

	.preinit_array  :
	{
	  PROVIDE_HIDDEN (__preinit_array_start = .);
	  KEEP (*(.preinit_array))
	  PROVIDE_HIDDEN (__preinit_array_end = .);
	} >FLASH AT>FLASH 
	
	.init_array     :
	{
	  PROVIDE_HIDDEN (__init_array_start = .);
	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
	  PROVIDE_HIDDEN (__init_array_end = .);
	} >FLASH AT>FLASH 
	
	.fini_array     :
	{
	  PROVIDE_HIDDEN (__fini_array_start = .);
	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
	  PROVIDE_HIDDEN (__fini_array_end = .);
	} >FLASH AT>FLASH 
	
	.ctors          :
	{
	  /* gcc uses crtbegin.o to find the start of
	     the constructors, so we make sure it is
	     first.  Because this is a wildcard, it
	     doesn't matter if the user does not
	     actually link against crtbegin.o; the
	     linker won't look for a file to match a
	     wildcard.  The wildcard also means that it
	     doesn't matter which directory crtbegin.o
	     is in.  */
	  KEEP (*crtbegin.o(.ctors))
	  KEEP (*crtbegin?.o(.ctors))
	  /* We don't want to include the .ctor section from
	     the crtend.o file until after the sorted ctors.
	     The .ctor section from the crtend file contains the
	     end of ctors marker and it must be last */
	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
	  KEEP (*(SORT(.ctors.*)))
	  KEEP (*(.ctors))
	} >FLASH AT>FLASH 
	
	.dtors          :
	{
	  KEEP (*crtbegin.o(.dtors))
	  KEEP (*crtbegin?.o(.dtors))
	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
	  KEEP (*(SORT(.dtors.*)))
	  KEEP (*(.dtors))
	} >FLASH AT>FLASH 

	.dalign :
	{
		. = ALIGN(4);
		PROVIDE(_data_vma = .);
	} >RAM AT>FLASH	

	.dlalign :
	{
		. = ALIGN(4); 
		PROVIDE(_data_lma = .);
	} >FLASH AT>FLASH

	.data :
	{
    	*(.gnu.linkonce.r.*)
    	*(.data .data.*)
    	*(.gnu.linkonce.d.*)
		. = ALIGN(8);
    	/*PROVIDE( __global_pointer$ = . + 0x800 );*/
    	*(.sdata .sdata.*)
    	*(.gnu.linkonce.s.*)
    	. = ALIGN(8);
    	*(.srodata.cst16)
    	*(.srodata.cst8)
    	*(.srodata.cst4)
    	*(.srodata.cst2)
    	*(.srodata .srodata.*)
    	. = ALIGN(4);
		PROVIDE( _edata = .);
	} >RAM AT>FLASH

	.bss :
	{
		. = ALIGN(4);
		PROVIDE( _sbss = .);
  	    *(.sbss*)
        *(.gnu.linkonce.sb.*)
		*(.bss*)
     	*(.gnu.linkonce.b.*)		
		*(COMMON*)
		. = ALIGN(4);
		PROVIDE( _ebss = .);
	} >RAM AT>FLASH

	PROVIDE( _end = _ebss);
	PROVIDE( end = . );

    /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
    {
        PROVIDE( _heap_end = . );   
        . = ALIGN(4);
        PROVIDE(_susrstack = . );
        . = . + __stack_size;
        PROVIDE( _eusrstack = .);
    } >RAM */

	.stack ORIGIN(RAM)+LENGTH(RAM) :
	{
        PROVIDE( _heap_end = . );   
		. = ALIGN(4);
		PROVIDE(_eusrstack = . );
	} >RAM  
}
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{  
+/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
+*/ 
+
+/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
+/*
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+*/ 
+  
+/* CH32V20x_D8 - CH32V203RB
+   CH32V20x_D8W - CH32V208x
+   FLASH + RAM supports the following configuration
+   FLASH-128K + RAM-64K
+   FLASH-144K + RAM-48K
+   FLASH-160K + RAM-32K
+*/
+	FLASH (rx) : ORIGIN = 0x00004000, LENGTH = 240K
+	RAM (xrw) : ORIGIN = 0x20004000, LENGTH = 48K
+}
+
+    PROVIDE( __global_pointer$ = 0x20004000 );
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		KEEP(*(.ImageFlag))
+		KEEP(*(.ImageFlag.*))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+		KEEP(*(SORT_NONE(.handle_reset)))
+  } >FLASH AT>FLASH
+  
+     .highcode : 
+    {
+        . = ALIGN(4);
+        *(.highcode);
+        *(.highcode.*);
+		. = ALIGN(4); 
+    } >FLASH AT>FLASH
+    
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+        *(.sdata2.*)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	/*PROVIDE( __global_pointer$ = . + 0x800 );*/
+    	*(.sdata .sdata.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    /*.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );   
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAM */
+
+	.stack ORIGIN(RAM)+LENGTH(RAM) :
+	{
+        PROVIDE( _heap_end = . );   
+		. = ALIGN(4);
+		PROVIDE(_eusrstack = . );
+	} >RAM  
+}

EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/Startup/startup_ch32v20x_D8W.S

@@ -93,8 +93,8 @@ _vector_base:
     .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
-    .word   USBHD_IRQHandler           /* USBHD Break */
-    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   USBFS_IRQHandler           /* USBFS Break */
+    .word   USBFSWakeUp_IRQHandler     /* USBFS Wake up from suspend */
     .word   ETH_IRQHandler             /* ETH global */
     .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
     .word   BB_IRQHandler              /* BLE BB */
@@ -158,8 +158,8 @@ _vector_base:
     .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
     .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
     .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
-    .weak   USBHD_IRQHandler           /* USBHD */
-    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   USBFS_IRQHandler           /* USBFS */
+    .weak   USBFSWakeUp_IRQHandler     /* USBFS Wake Up */
     .weak   ETH_IRQHandler             /* ETH global */
     .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
     .weak   BB_IRQHandler              /* BB */
@@ -220,8 +220,8 @@ USART3_IRQHandler:  1:  j 1b
 EXTI15_10_IRQHandler:  1:  j 1b
 RTCAlarm_IRQHandler:  1:  j 1b
 USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
+USBFS_IRQHandler:  1:  j 1b
+USBFSWakeUp_IRQHandler:  1:  j 1b
 ETH_IRQHandler:  1:  j 1b
 ETHWakeUp_IRQHandler:  1:  j 1b
 BB_IRQHandler:  1:  j 1b

EVT/EXAM/BLE/PAwR_ADV/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }

EVT/EXAM/BLE/PAwR_RSP/APP/ch32v20x_it.c

@@ -43,6 +43,7 @@ void NMI_Handler(void)
  */
 void HardFault_Handler(void)
 {
+    NVIC_SystemReset();
     while(1)
     {
     }

EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c

@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
       }
       else
       {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
+        if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
         {
           SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
         }