V2.2
This commit is contained in:
qiyongshuang
+187
-1
@@ -1 +1,187 @@
|
||||
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{ ␍/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */␍/*␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K␍*/ ␍␍/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */␍/**/␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍ ␍ ␍/* CH32V20x_D8 - CH32V203RB␍ CH32V20x_D8W - CH32V208x␍ FLASH + RAM supports the following configuration␍ FLASH-128K + RAM-64K␍ FLASH-144K + RAM-48K␍ FLASH-160K + RAM-32K␍␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K␍*/␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.gnu.linkonce.t.*)␍ . = ALIGN(4);␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . ); ␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
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ENTRY( _start )
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__stack_size = 2048;
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PROVIDE( _stack_size = __stack_size );
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MEMORY
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{
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/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
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/*
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
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*/
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/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
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/**/
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
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/* CH32V20x_D8 - CH32V203RB
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CH32V20x_D8W - CH32V208x
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FLASH + RAM supports the following configuration
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FLASH-128K + RAM-64K
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FLASH-144K + RAM-48K
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FLASH-160K + RAM-32K
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
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*/
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}
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SECTIONS
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{
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||||
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.init :
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{
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_sinit = .;
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. = ALIGN(4);
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KEEP(*(SORT_NONE(.init)))
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||||
. = ALIGN(4);
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_einit = .;
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} >FLASH AT>FLASH
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.vector :
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||||
{
|
||||
*(.vector);
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||||
. = ALIGN(64);
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||||
} >FLASH AT>FLASH
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||||
|
||||
.text :
|
||||
{
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||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
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||||
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(SORT_NONE(.fini)))
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||||
. = ALIGN(4);
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||||
} >FLASH AT>FLASH
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||||
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||||
PROVIDE( _etext = . );
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PROVIDE( _eitcm = . );
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||||
|
||||
.preinit_array :
|
||||
{
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||||
PROVIDE_HIDDEN (__preinit_array_start = .);
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||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH AT>FLASH
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||||
|
||||
.init_array :
|
||||
{
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||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
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||||
PROVIDE_HIDDEN (__init_array_end = .);
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} >FLASH AT>FLASH
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||||
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||||
.fini_array :
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||||
{
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||||
PROVIDE_HIDDEN (__fini_array_start = .);
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||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
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||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
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||||
PROVIDE_HIDDEN (__fini_array_end = .);
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||||
} >FLASH AT>FLASH
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||||
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||||
.ctors :
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||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
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||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
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KEEP (*(SORT(.ctors.*)))
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||||
KEEP (*(.ctors))
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||||
} >FLASH AT>FLASH
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||||
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||||
.dtors :
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||||
{
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||||
KEEP (*crtbegin.o(.dtors))
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||||
KEEP (*crtbegin?.o(.dtors))
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||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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} >FLASH AT>FLASH
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||||
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.dalign :
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{
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. = ALIGN(4);
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PROVIDE(_data_vma = .);
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} >RAM AT>FLASH
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||||
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.dlalign :
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{
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. = ALIGN(4);
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PROVIDE(_data_lma = .);
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} >FLASH AT>FLASH
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||||
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||||
.data :
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||||
{
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||||
*(.gnu.linkonce.r.*)
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||||
*(.data .data.*)
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||||
*(.gnu.linkonce.d.*)
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||||
. = ALIGN(8);
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||||
PROVIDE( __global_pointer$ = . + 0x800 );
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*(.sdata .sdata.*)
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||||
*(.sdata2.*)
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||||
*(.gnu.linkonce.s.*)
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||||
. = ALIGN(8);
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||||
*(.srodata.cst16)
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*(.srodata.cst8)
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*(.srodata.cst4)
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*(.srodata.cst2)
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*(.srodata .srodata.*)
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. = ALIGN(4);
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PROVIDE( _edata = .);
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} >RAM AT>FLASH
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.bss :
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||||
{
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||||
. = ALIGN(4);
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PROVIDE( _sbss = .);
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*(.sbss*)
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||||
*(.gnu.linkonce.sb.*)
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||||
*(.bss*)
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||||
*(.gnu.linkonce.b.*)
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||||
*(COMMON*)
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||||
. = ALIGN(4);
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||||
PROVIDE( _ebss = .);
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} >RAM AT>FLASH
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||||
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PROVIDE( _end = _ebss);
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PROVIDE( end = . );
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.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
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||||
{
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PROVIDE( _heap_end = . );
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. = ALIGN(4);
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||||
PROVIDE(_susrstack = . );
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||||
. = . + __stack_size;
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||||
PROVIDE( _eusrstack = .);
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} >RAM
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||||
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||||
}
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||||
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||||
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||||
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||||
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@@ -2,7 +2,7 @@
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* File Name : ch32v20x.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/01/31
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* Date : 2024/07/04
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* Description : CH32V20x Device Peripheral Access Layer Header File.
|
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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@@ -17,7 +17,7 @@ extern "C" {
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#endif
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#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6)
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#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
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#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
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//#define CH32V20x_D8 /* CH32V203RBT6 */
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//#define CH32V20x_D8W /* CH32V208 */
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@@ -26,10 +26,12 @@ extern "C" {
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#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */
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#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
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#else
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#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
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#ifndef HSE_VALUE
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
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#else
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||||
#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
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||||
#endif
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||||
#endif
|
||||
|
||||
/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
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||||
@@ -39,7 +41,7 @@ extern "C" {
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||||
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||||
/* CH32V20x Standard Peripheral Library version number */
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#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
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||||
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x01) /* [7:0] sub version */
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||||
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */
|
||||
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|
||||
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
|
||||
|
||||
@@ -53,7 +55,7 @@ typedef enum IRQn
|
||||
Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */
|
||||
Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */
|
||||
Break_Point_IRQn = 9, /* 9 Break Point Interrupt */
|
||||
SysTicK_IRQn = 12, /* 12 System timer Interrupt */
|
||||
SysTick_IRQn = 12, /* 12 System timer Interrupt */
|
||||
Software_IRQn = 14, /* 14 software Interrupt */
|
||||
|
||||
/****** RISC-V specific Interrupt Numbers *********************************************************/
|
||||
@@ -132,7 +134,7 @@ typedef enum IRQn
|
||||
|
||||
#define HardFault_IRQn EXC_IRQn
|
||||
#define ADC1_2_IRQn ADC_IRQn
|
||||
|
||||
#define SysTicK_IRQn SysTick_IRQn
|
||||
#define USBHD_IRQn USBFS_IRQn
|
||||
#define USBHDWakeUp_IRQn USBFSWakeUp_IRQn
|
||||
|
||||
@@ -3168,7 +3170,6 @@ typedef struct
|
||||
#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */
|
||||
#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */
|
||||
#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */
|
||||
#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */
|
||||
#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */
|
||||
|
||||
/******************* Bit definition for FLASH_ADDR register *******************/
|
||||
@@ -3853,14 +3854,23 @@ typedef struct
|
||||
#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */
|
||||
#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */
|
||||
|
||||
#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */
|
||||
#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */
|
||||
#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */
|
||||
#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */
|
||||
#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */
|
||||
#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */
|
||||
#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */
|
||||
#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */
|
||||
#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000)
|
||||
#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020)
|
||||
#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040)
|
||||
#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060)
|
||||
#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080)
|
||||
#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0)
|
||||
#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0)
|
||||
#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0)
|
||||
|
||||
#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0
|
||||
#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1
|
||||
#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2
|
||||
#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3
|
||||
#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4
|
||||
#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5
|
||||
#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6
|
||||
#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7
|
||||
|
||||
#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */
|
||||
|
||||
|
||||
@@ -33,38 +33,38 @@ typedef enum
|
||||
} FLASH_Status;
|
||||
|
||||
/* Write Protect */
|
||||
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */
|
||||
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
|
||||
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */
|
||||
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */
|
||||
|
||||
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
|
||||
|
||||
@@ -124,7 +124,6 @@ void FLASH_Unlock_Fast(void);
|
||||
void FLASH_Lock_Fast(void);
|
||||
void FLASH_ErasePage_Fast(uint32_t Page_Address);
|
||||
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
|
||||
void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
|
||||
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf);
|
||||
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
|
||||
void FLASH_Enhance_Mode(FunctionalState NewState);
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* File Name : ch32v20x_gpio.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/03/02
|
||||
* Date : 2024/07/23
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* GPIO firmware library.
|
||||
*********************************************************************************
|
||||
@@ -97,7 +97,7 @@ typedef enum
|
||||
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
|
||||
#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
|
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
|
||||
@@ -112,6 +112,7 @@ typedef enum
|
||||
to TIM2 Internal Trigger 1 for calibration \
|
||||
(only for Connectivity line devices) */
|
||||
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||
#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
|
||||
|
||||
/* PCFR2 */
|
||||
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
|
||||
|
||||
@@ -20,14 +20,24 @@ extern "C" {
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/* PVD_detection_level */
|
||||
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
|
||||
|
||||
#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0)
|
||||
|
||||
#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0
|
||||
#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1
|
||||
#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2
|
||||
#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3
|
||||
#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4
|
||||
#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5
|
||||
#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6
|
||||
#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7
|
||||
|
||||
/* Regulator_state_is_STOP_mode */
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
|
||||
@@ -92,7 +92,7 @@ typedef struct
|
||||
#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
|
||||
|
||||
#ifdef CH32V20x_D8W
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03)
|
||||
|
||||
#endif
|
||||
@@ -250,6 +250,7 @@ void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
void RCC_ADCCLKADJcmd(FunctionalState NewState);
|
||||
FlagStatus RCC_USB5PRE_JUDGE();
|
||||
|
||||
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
|
||||
void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div);
|
||||
|
||||
@@ -109,7 +109,6 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
* CH32V203C8T6-0x203105x0
|
||||
* CH32V203K8T6-0x203205x0
|
||||
* CH32V203C6T6-0x203305x0
|
||||
* CH32V203K6T6-0x203505x0
|
||||
* CH32V203G6U6-0x203605x0
|
||||
* CH32V203G8R6-0x203B05x0
|
||||
* CH32V203F8U6-0x203E05x0
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#define CR_PAGE_PG ((uint32_t)0x00010000)
|
||||
#define CR_PAGE_ER ((uint32_t)0x00020000)
|
||||
#define CR_BER32 ((uint32_t)0x00040000)
|
||||
#define CR_BER64 ((uint32_t)0x00080000)
|
||||
#define CR_PG_STRT ((uint32_t)0x00200000)
|
||||
|
||||
/* FLASH Status Register bits */
|
||||
@@ -521,6 +520,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint
|
||||
uint32_t Addr = 0x1FFFF800;
|
||||
__IO uint8_t i;
|
||||
uint16_t pbuf[8];
|
||||
uint16_t temp;
|
||||
|
||||
FLASH->OBKEYR = FLASH_KEY1;
|
||||
FLASH->OBKEYR = FLASH_KEY2;
|
||||
@@ -533,6 +533,8 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint
|
||||
pbuf[i] = *(uint16_t *)(Addr + 2 * i);
|
||||
}
|
||||
|
||||
temp=pbuf[1]&(~0x7);
|
||||
|
||||
/* Erase optionbytes */
|
||||
FLASH->CTLR |= CR_OPTER_Set;
|
||||
FLASH->CTLR |= CR_STRT_Set;
|
||||
@@ -540,7 +542,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint
|
||||
FLASH->CTLR &= ~CR_OPTER_Set;
|
||||
|
||||
/* Write optionbytes */
|
||||
pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
|
||||
pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)temp)));
|
||||
|
||||
FLASH->CTLR |= CR_OPTPG_Set;
|
||||
for(i = 0; i < 8; i++){
|
||||
@@ -864,26 +866,6 @@ void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
|
||||
FLASH->CTLR &= ~CR_BER32;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_EraseBlock_64K_Fast
|
||||
*
|
||||
* @brief Erases a specified FLASH Block (1Block = 64KByte).
|
||||
*
|
||||
* @param Block_Address - The block address to be erased.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address)
|
||||
{
|
||||
Block_Address &= 0xFFFF0000;
|
||||
|
||||
FLASH->CTLR |= CR_BER64;
|
||||
FLASH->ADDR = Block_Address;
|
||||
FLASH->CTLR |= CR_STRT_Set;
|
||||
while(FLASH->STATR & SR_BSY);
|
||||
FLASH->CTLR &= ~CR_BER64;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ProgramPage_Fast
|
||||
*
|
||||
|
||||
@@ -509,7 +509,7 @@ void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
|
||||
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
|
||||
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
|
||||
* GPIO_Remap_PD01 - PD01 Alternate Function mapping
|
||||
* GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping
|
||||
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
|
||||
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
|
||||
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
|
||||
@@ -840,34 +840,6 @@ void GPIO_IPD_Unused(void)
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20350500: //CH32V203K6T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20320500: //CH32V203K8T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
|
||||
@@ -81,14 +81,14 @@ void PWR_PVDCmd(FunctionalState NewState)
|
||||
* Detector(PVD).
|
||||
*
|
||||
* @param PWR_PVDLevel - specifies the PVD detection level
|
||||
* PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
|
||||
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
|
||||
* PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
|
||||
* PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
|
||||
* PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
|
||||
* PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
|
||||
* PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
|
||||
* PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
|
||||
* PWR_PVDLevel_MODE0 - PVD detection level set to mode 0.
|
||||
* PWR_PVDLevel_MODE1 - PVD detection level set to mode 1.
|
||||
* PWR_PVDLevel_MODE2 - PVD detection level set to mode 2.
|
||||
* PWR_PVDLevel_MODE3 - PVD detection level set to mode 3.
|
||||
* PWR_PVDLevel_MODE4 - PVD detection level set to mode 4.
|
||||
* PWR_PVDLevel_MODE5 - PVD detection level set to mode 5.
|
||||
* PWR_PVDLevel_MODE6 - PVD detection level set to mode 6.
|
||||
* PWR_PVDLevel_MODE7 - PVD detection level set to mode 7.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
|
||||
@@ -585,8 +585,8 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
|
||||
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
|
||||
{
|
||||
RCC_Clocks->SYSCLK_Frequency = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
@@ -1028,5 +1028,34 @@ void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div)
|
||||
RCC->CFGR0 |= RCC_ETHPRE_Div<<28;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_USB5PRE_JUDGE()
|
||||
*
|
||||
* @brief Judge MCU supports PLLCLK/5 for USB.
|
||||
*
|
||||
* @param FlagStatus - SET or RESET.
|
||||
* SET - support
|
||||
* RESET - not support
|
||||
* @return none
|
||||
*/
|
||||
FlagStatus RCC_USB5PRE_JUDGE()
|
||||
{
|
||||
|
||||
#if defined (CH32V20x_D8W)
|
||||
return SET;
|
||||
#elif defined (CH32V20x_D8)
|
||||
RCC->AHBPCENR |= (1<<17);
|
||||
*(vu32*)0x400250A0 = 0x55aaaa55;
|
||||
if(*(vu32*)0x400250A0 == 0x55aaaa55)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
#endif
|
||||
return RESET;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.1
|
||||
;* Date : 2024/01/31
|
||||
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
|
||||
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
|
||||
;* vector table for eclipse toolchain.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
|
||||
Reference in New Issue
Block a user