V2.2
This commit is contained in:
qiyongshuang
@@ -2,7 +2,7 @@
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* File Name : ch32v20x.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/01/31
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* Date : 2024/07/04
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* Description : CH32V20x Device Peripheral Access Layer Header File.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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@@ -17,7 +17,7 @@ extern "C" {
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#endif
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#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6)
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#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
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#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
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//#define CH32V20x_D8 /* CH32V203RBT6 */
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//#define CH32V20x_D8W /* CH32V208 */
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@@ -26,10 +26,12 @@ extern "C" {
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#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */
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#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
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#else
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#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
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#ifndef HSE_VALUE
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
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#else
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#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
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#endif
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#endif
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/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
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@@ -39,7 +41,7 @@ extern "C" {
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/* CH32V20x Standard Peripheral Library version number */
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#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
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#define __CH32V20x_STDPERIPH_VERSION_SUB (0x01) /* [7:0] sub version */
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#define __CH32V20x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */
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#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
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|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
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@@ -53,7 +55,7 @@ typedef enum IRQn
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Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */
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Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */
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Break_Point_IRQn = 9, /* 9 Break Point Interrupt */
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SysTicK_IRQn = 12, /* 12 System timer Interrupt */
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SysTick_IRQn = 12, /* 12 System timer Interrupt */
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Software_IRQn = 14, /* 14 software Interrupt */
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/****** RISC-V specific Interrupt Numbers *********************************************************/
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@@ -132,7 +134,7 @@ typedef enum IRQn
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#define HardFault_IRQn EXC_IRQn
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#define ADC1_2_IRQn ADC_IRQn
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#define SysTicK_IRQn SysTick_IRQn
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#define USBHD_IRQn USBFS_IRQn
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#define USBHDWakeUp_IRQn USBFSWakeUp_IRQn
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@@ -3168,7 +3170,6 @@ typedef struct
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#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */
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#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */
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#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */
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#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */
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#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */
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/******************* Bit definition for FLASH_ADDR register *******************/
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@@ -3853,14 +3854,23 @@ typedef struct
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#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */
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#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */
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#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */
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#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */
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#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */
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#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */
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#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */
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#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */
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#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */
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#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */
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#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000)
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#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020)
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#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040)
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#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060)
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#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080)
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#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0)
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#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0)
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#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0)
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#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0
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#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1
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#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2
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#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3
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#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4
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#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5
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#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6
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#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7
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#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */
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@@ -33,38 +33,38 @@ typedef enum
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} FLASH_Status;
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/* Write Protect */
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#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */
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#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
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#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */
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#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */
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#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
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@@ -124,7 +124,6 @@ void FLASH_Unlock_Fast(void);
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void FLASH_Lock_Fast(void);
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void FLASH_ErasePage_Fast(uint32_t Page_Address);
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void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
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void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
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void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf);
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void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
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void FLASH_Enhance_Mode(FunctionalState NewState);
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@@ -2,7 +2,7 @@
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* File Name : ch32v20x_gpio.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/03/02
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* Date : 2024/07/23
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* Description : This file contains all the functions prototypes for the
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* GPIO firmware library.
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*********************************************************************************
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@@ -97,7 +97,7 @@ typedef enum
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#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
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#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
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#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
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#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
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#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */
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#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
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#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
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#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
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@@ -112,6 +112,7 @@ typedef enum
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to TIM2 Internal Trigger 1 for calibration \
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(only for Connectivity line devices) */
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#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
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#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
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/* PCFR2 */
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#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
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@@ -20,14 +20,24 @@ extern "C" {
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#include "ch32v20x.h"
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/* PVD_detection_level */
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#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
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#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
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#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
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#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
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#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
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#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
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#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
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#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
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#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000)
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#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020)
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#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040)
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#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060)
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#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080)
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#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0)
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#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0)
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#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0)
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#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0
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#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1
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#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2
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#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3
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#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4
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#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5
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#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6
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#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7
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/* Regulator_state_is_STOP_mode */
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#define PWR_Regulator_ON ((uint32_t)0x00000000)
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@@ -92,7 +92,7 @@ typedef struct
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#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
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#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
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#ifdef CH32V20x_D8W
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#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
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#define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03)
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#endif
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@@ -250,6 +250,7 @@ void RCC_ClearFlag(void);
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ITStatus RCC_GetITStatus(uint8_t RCC_IT);
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void RCC_ClearITPendingBit(uint8_t RCC_IT);
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void RCC_ADCCLKADJcmd(FunctionalState NewState);
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FlagStatus RCC_USB5PRE_JUDGE();
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div);
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