bstanwell/ch32v20x-examples
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qiyongshuang
2024-11-11 14:32:11 +08:00
parent c4c38f507e
commit 961943f623
452 changed files with 9316 additions and 862 deletions
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EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+28 -18
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@@ -2,7 +2,7 @@
* File Name : ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/31
* Date : 2024/07/04
* Description : CH32V20x Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -17,7 +17,7 @@ extern "C" {
#endif
#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6)
#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
//#define CH32V20x_D8 /* CH32V203RBT6 */
//#define CH32V20x_D8W /* CH32V208 */
@@ -26,10 +26,12 @@ extern "C" {
#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
#ifndef HSE_VALUE
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
#endif
#endif
/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
@@ -39,7 +41,7 @@ extern "C" {
/* CH32V20x Standard Peripheral Library version number */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x01) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
@@ -53,7 +55,7 @@ typedef enum IRQn
Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */
Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */
Break_Point_IRQn = 9, /* 9 Break Point Interrupt */
SysTicK_IRQn = 12, /* 12 System timer Interrupt */
SysTick_IRQn = 12, /* 12 System timer Interrupt */
Software_IRQn = 14, /* 14 software Interrupt */
/****** RISC-V specific Interrupt Numbers *********************************************************/
@@ -132,7 +134,7 @@ typedef enum IRQn
#define HardFault_IRQn EXC_IRQn
#define ADC1_2_IRQn ADC_IRQn
#define SysTicK_IRQn SysTick_IRQn
#define USBHD_IRQn USBFS_IRQn
#define USBHDWakeUp_IRQn USBFSWakeUp_IRQn
@@ -3168,7 +3170,6 @@ typedef struct
#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */
#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */
#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */
#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */
#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */
/******************* Bit definition for FLASH_ADDR register *******************/
@@ -3853,14 +3854,23 @@ typedef struct
#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */
#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */
#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */
#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */
#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */
#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */
#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */
#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */
#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */
#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */
#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000)
#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020)
#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040)
#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060)
#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080)
#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0)
#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0)
#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0)
#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0
#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1
#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2
#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3
#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4
#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5
#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6
#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7
#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */