bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-11-11 14:32:11 +08:00
parent c4c38f507e
commit 961943f623
452 changed files with 9316 additions and 862 deletions
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EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -55,19 +55,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/CH372/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/CH372/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/CompatibilityHID/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/CompatibilityHID/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/CompositeKM/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/CompositeKM/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/MSC_CD-ROM/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/MSC_CD-ROM/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -56,19 +56,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/MSC_U-Disk/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/MSC_U-Disk/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -55,19 +55,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/SimulateCDC-HID/User/ch32v20x_it.c
+1
View File
@@ -55,6 +55,7 @@ void TIM2_IRQHandler( void )
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/SimulateCDC-HID/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/hw_config.c
+12 -4
View File
@@ -55,19 +55,27 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
*/
void Set_USBConfig( )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
EVT/EXAM/USB/USBD/SimulateCDC/User/ch32v20x_it.c
+1
View File
@@ -55,6 +55,7 @@ void TIM2_IRQHandler( void )
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBD/SimulateCDC/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject
+539 -141
View File
@@ -1,143 +1,541 @@
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EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.template
+16 -9
View File
@@ -1,16 +1,23 @@
Vendor=WCH
Toolchain=RISC-V
Series=CH32V203
RTOS=NoneOS
MCU=CH32V203RBT6
Link=WCH-Link
PeripheralVersion=1.0
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
Mcu Type=CH32V20x
Address=0x08000000
Target Path=obj/CH372Device.hex
Exe Path=
Exe Arguments=
CLKSpeed=1
DebugInterfaceMode=0
Erase All=true
Program=true
Verify=true
Reset=true
Vendor=WCH
Link=WCH-Link
Toolchain=RISC-V
Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
SDIPrintf=false
Disable Power Output=false
Clear CodeFlash=false
Disable Code-Protect=false
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/CH372Device.wvproj
+709 -2
View File
@@ -1,2 +1,709 @@
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"svdpath": "${WCH:SDK:default}/RISC-V/CH32V203/NoneOS/CH32V203xx.svd",
"output": {
"showDebugGDBTrace": true,
"saveDebugOutputToFile": false,
"showDebugOutputTimestamps": true
},
"reserve": {
"PROGRAM_NAME": "obj/CH372Device.elf",
"PROJECT_ATTR": "CH372Device",
"PROJECT_BUILD_CONFIG_AUTO_ATTR": true,
"PROJECT_BUILD_CONFIG_ID_ATTR": "",
"ATTR_BUILD_BEFORE_LAUNCH_ATTR": 2,
"GdbServerAllocateConsole": true,
"GdbServerAllocateTelnetConsole": false,
"StartGdbCLient": true,
"UPDATE_THREADLIST_ON_SUSPEND": false
}
}
}
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usbfs_device.c
+12 -4
View File
@@ -55,20 +55,28 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*
* @return none
*/
void USBFS_RCC_Init(void)
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/system_ch32v20x.c
+5 -5
View File
@@ -22,8 +22,8 @@
//#define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_56MHz_HSE 56000000
//#define SYSCLK_FREQ_72MHz_HSE 72000000
#define SYSCLK_FREQ_96MHz_HSE 96000000
//#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_96MHz_HSE 96000000
#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
//#define SYSCLK_FREQ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHz_HSI 48000000
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
@@ -624,7 +624,7 @@ static void SetSysClockTo120_HSE(void)
if(HSEStatus == (uint32_t)0x01)
{
#if defined (CH32V20x_D8W)
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
RCC->CFGR0 |= (uint32_t)(3<<22);
/* HCLK = SYSCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c
+12 -4
View File
@@ -54,24 +54,32 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Set USB clock.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c
+12 -4
View File
@@ -54,24 +54,32 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Set USB clock.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c
+11 -3
View File
@@ -51,18 +51,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c
+11 -3
View File
@@ -51,18 +51,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c
+11 -3
View File
@@ -61,18 +61,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/ch32v20x_it.c
+1
View File
@@ -60,6 +60,7 @@ void TIM2_IRQHandler( void )
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c
+11 -3
View File
@@ -52,18 +52,26 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/ch32v20x_it.c
+1
View File
@@ -60,6 +60,7 @@ void TIM2_IRQHandler( void )
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/HOST_IAP/APP/Ld_APP/Link.ld
+192 -1
View File
@@ -1 +1,192 @@
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{ ␍/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */␍/*␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K␍*/ ␍␍/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */␍/**/␍/*␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍*/␍ FLASH (rx) : ORIGIN = 0x00005000, LENGTH = 44K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍ ␍/* CH32V20x_D8 - CH32V203RB␍ CH32V20x_D8W - CH32V208x␍ FLASH + RAM supports the following configuration␍ FLASH-128K + RAM-64K␍ FLASH-144K + RAM-48K␍ FLASH-160K + RAM-32K␍␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K␍*/␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.glue_7)␍ *(.glue_7t)␍ *(.gnu.linkonce.t.*)␍ . = ALIGN(4);␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . ); ␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
MEMORY
{
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/
/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/**/
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
*/
FLASH (rx) : ORIGIN = 0x00005000, LENGTH = 44K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
/* CH32V20x_D8 - CH32V203RB
CH32V20x_D8W - CH32V208x
FLASH + RAM supports the following configuration
FLASH-128K + RAM-64K
FLASH-144K + RAM-48K
FLASH-160K + RAM-32K
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
*/
}
SECTIONS
{
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{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
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PROVIDE_HIDDEN (__preinit_array_start = .);
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PROVIDE_HIDDEN (__preinit_array_end = .);
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PROVIDE_HIDDEN (__init_array_start = .);
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PROVIDE_HIDDEN (__init_array_end = .);
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
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{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
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KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
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KEEP (*crtbegin?.o(.dtors))
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}
EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/ch32v20x_it.c
+1
View File
@@ -36,6 +36,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/HOST_IAP/APP/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/USB_Host/ch32v20x_usbfs_host.c
+12 -4
View File
@@ -23,24 +23,32 @@ __attribute__((aligned(4))) uint8_t TxBuffer[ MAX_PACKET_SIZE ]; // O
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Set USB port clock.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
/*********************************************************************
EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_it.c
+1
View File
@@ -38,6 +38,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c
+12 -6
View File
@@ -23,26 +23,32 @@ __attribute__((aligned(4))) uint8_t USBFS_TX_Buf[ USBFS_MAX_PACKET_SIZE ];
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Set USB port clock.
* Note: If the SystemCoreClock is selected as the USB clock source,
* only the frequency specified below can be used.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
/*********************************************************************
EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_it.c
+1
View File
@@ -36,6 +36,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/HOST_KM/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c
+12 -6
View File
@@ -23,26 +23,32 @@ __attribute__((aligned(4))) uint8_t USBFS_TX_Buf[ USBFS_MAX_PACKET_SIZE ];
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Set USB port clock.
* Note: If the SystemCoreClock is selected as the USB clock source,
* only the frequency specified below can be used.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
/*********************************************************************
EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_it.c
+1
View File
@@ -36,6 +36,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/USB/USBFS/HOST_Udisk/User/USB_Host/ch32v20x_usbfs_host.c
+12 -4
View File
@@ -23,24 +23,32 @@ __attribute__((aligned(4))) uint8_t TxBuffer[ MAX_PACKET_SIZE ]; // O
/*********************************************************************
* @fn USBFS_RCC_Init
*
* @brief Set USB port clock.
* @brief Initializes the usbfs clock configuration.
*
* @return none
*/
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
/*********************************************************************
EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_it.c
+1
View File
@@ -36,6 +36,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/HOST_Udisk/User/system_ch32v20x.c
+2 -2
View File
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}