bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-11-11 14:32:11 +08:00
parent c4c38f507e
commit 961943f623
452 changed files with 9316 additions and 862 deletions
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EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_it.c
+1
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@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usbfs_device.c
+12 -4
View File
@@ -55,20 +55,28 @@ void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
*
* @return none
*/
void USBFS_RCC_Init(void)
void USBFS_RCC_Init( void )
{
if( SystemCoreClock == 144000000 )
RCC_ClocksTypeDef RCC_ClocksStatus={0};
RCC_GetClocksFreq(&RCC_ClocksStatus);
if( RCC_ClocksStatus.SYSCLK_Frequency == 144000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
}
else if( SystemCoreClock == 96000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 96000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
}
else if( SystemCoreClock == 48000000 )
else if( RCC_ClocksStatus.SYSCLK_Frequency == 48000000 )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
}
#if defined(CH32V20x_D8W) || defined(CH32V20x_D8)
else if ( RCC_ClocksStatus.SYSCLK_Frequency == 240000000 && RCC_USB5PRE_JUDGE() == SET )
{
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div5 );
}
#endif
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_USBFS, ENABLE );
}
EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/system_ch32v20x.c
+5 -5
View File
@@ -22,8 +22,8 @@
//#define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_56MHz_HSE 56000000
//#define SYSCLK_FREQ_72MHz_HSE 72000000
#define SYSCLK_FREQ_96MHz_HSE 96000000
//#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_96MHz_HSE 96000000
#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
//#define SYSCLK_FREQ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHz_HSI 48000000
@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
@@ -624,7 +624,7 @@ static void SetSysClockTo120_HSE(void)
if(HSEStatus == (uint32_t)0x01)
{
#if defined (CH32V20x_D8W)
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
RCC->CFGR0 |= (uint32_t)(3<<22);
/* HCLK = SYSCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;