first submission
This commit is contained in:
qiyongshuang
@@ -0,0 +1,428 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : app.c
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* Author : WCH
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* Version : V1.1
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* Date : 2022/01/18
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* Description :
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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/******************************************************************************/
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#include "CONFIG.h"
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#include "MESH_LIB.h"
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#include "app_generic_onoff_model.h"
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#include "app.h"
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#include "HAL.h"
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/*********************************************************************
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* GLOBAL TYPEDEFS
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*/
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/*********************************************************************
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* GLOBAL TYPEDEFS
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*/
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static uint8_t MESH_MEM[1024 * 2] = {0};
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extern const ble_mesh_cfg_t app_mesh_cfg;
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extern const struct device app_dev;
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static uint8_t App_TaskID = 0; // Task ID for internal task/event processing
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static uint16_t App_ProcessEvent(uint8_t task_id, uint16_t events);
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#if(!CONFIG_BLE_MESH_PB_GATT)
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NET_BUF_SIMPLE_DEFINE_STATIC(rx_buf, 65);
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#endif /* !PB_GATT */
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/*********************************************************************
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* LOCAL FUNCION
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*/
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static void cfg_srv_rsp_handler( const cfg_srv_status_t *val );
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static void link_open(bt_mesh_prov_bearer_t bearer);
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static void link_close(bt_mesh_prov_bearer_t bearer, uint8_t reason);
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static void prov_complete(uint16_t net_idx, uint16_t addr, uint8_t flags, uint32_t iv_index);
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static void prov_reset(void);
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static struct bt_mesh_cfg_srv cfg_srv = {
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.relay = BLE_MESH_RELAY_ENABLED,
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.beacon = BLE_MESH_BEACON_ENABLED,
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#if(CONFIG_BLE_MESH_FRIEND)
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.frnd = BLE_MESH_FRIEND_ENABLED,
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#endif
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#if(CONFIG_BLE_MESH_PROXY)
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.gatt_proxy = BLE_MESH_GATT_PROXY_ENABLED,
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#endif
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/* 默认TTL为3 */
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.default_ttl = 3,
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/* 底层发送数据重试7次，每次间隔10ms（不含内部随机数） */
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.net_transmit = BLE_MESH_TRANSMIT(7, 10),
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/* 底层转发数据重试7次，每次间隔10ms（不含内部随机数） */
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.relay_retransmit = BLE_MESH_TRANSMIT(7, 10),
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.handler = cfg_srv_rsp_handler,
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};
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static struct bt_mesh_health_srv health_srv;
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BLE_MESH_HEALTH_PUB_DEFINE(health_pub, 8);
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uint16_t cfg_srv_keys[CONFIG_MESH_MOD_KEY_COUNT_DEF] = {BLE_MESH_KEY_UNUSED};
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uint16_t cfg_srv_groups[CONFIG_MESH_MOD_GROUP_COUNT_DEF] = {BLE_MESH_ADDR_UNASSIGNED};
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uint16_t health_srv_keys[CONFIG_MESH_MOD_KEY_COUNT_DEF] = {BLE_MESH_KEY_UNUSED};
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uint16_t health_srv_groups[CONFIG_MESH_MOD_GROUP_COUNT_DEF] = {BLE_MESH_ADDR_UNASSIGNED};
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uint16_t gen_onoff_srv_keys[CONFIG_MESH_MOD_KEY_COUNT_DEF] = {BLE_MESH_KEY_UNUSED};
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uint16_t gen_onoff_srv_groups[CONFIG_MESH_MOD_GROUP_COUNT_DEF] = {BLE_MESH_ADDR_UNASSIGNED};
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static struct bt_mesh_model root_models[] = {
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BLE_MESH_MODEL_CFG_SRV(cfg_srv_keys, cfg_srv_groups, &cfg_srv),
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BLE_MESH_MODEL_HEALTH_SRV(health_srv_keys, health_srv_groups, &health_srv, &health_pub),
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BLE_MESH_MODEL(BLE_MESH_MODEL_ID_GEN_ONOFF_SRV, gen_onoff_op, NULL, gen_onoff_srv_keys, gen_onoff_srv_groups, NULL),
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};
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static struct bt_mesh_elem elements[] = {
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{
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/* Location Descriptor (GATT Bluetooth Namespace Descriptors) */
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.loc = (0),
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.model_count = ARRAY_SIZE(root_models),
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.models = (root_models),
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}
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};
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static uint8_t dev_uuid[16];
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uint8_t MACAddr[6];
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// elements 构成 Node Composition
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const struct bt_mesh_comp app_comp = {
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.cid = 0x07D7, // WCH 公司id
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.elem = elements,
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.elem_count = ARRAY_SIZE(elements),
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};
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// 配网参数和回调
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static const struct bt_mesh_prov app_prov = {
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.uuid = dev_uuid,
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.link_open = link_open,
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.link_close = link_close,
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.complete = prov_complete,
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.reset = prov_reset,
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};
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/*********************************************************************
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* GLOBAL TYPEDEFS
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*/
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/*********************************************************************
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* @fn prov_enable
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*
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* @brief 使能配网功能
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*
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* @return none
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*/
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static void prov_enable(void)
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{
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if(bt_mesh_is_provisioned())
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{
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return;
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}
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// Make sure we're scanning for provisioning inviations
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bt_mesh_scan_enable();
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// Enable unprovisioned beacon sending
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bt_mesh_beacon_enable();
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if(CONFIG_BLE_MESH_PB_GATT)
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{
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bt_mesh_proxy_prov_enable();
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}
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}
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/*********************************************************************
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* @fn link_open
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*
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* @brief 配网时后的link打开回调
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*
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* @param bearer - 当前link是PB_ADV还是PB_GATT
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*
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* @return none
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*/
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static void link_open(bt_mesh_prov_bearer_t bearer)
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{
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APP_DBG(" ");
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}
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/*********************************************************************
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* @fn link_close
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*
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* @brief 配网后的link关闭回调
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*
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* @param bearer - 当前link是PB_ADV还是PB_GATT
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* @param reason - link关闭原因
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*
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* @return none
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*/
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static void link_close(bt_mesh_prov_bearer_t bearer, uint8_t reason)
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{
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APP_DBG("reason %x", reason);
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if(!bt_mesh_is_provisioned())
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{
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prov_enable();
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}
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else
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{
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}
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}
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/*********************************************************************
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* @fn prov_complete
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*
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* @brief 配网完成回调，重新开始广播
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*
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* @param net_idx - 网络key的index
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* @param addr - link关闭原因网络地址
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* @param flags - 是否处于key refresh状态
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* @param iv_index - 当前网络iv的index
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*
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* @return none
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*/
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static void prov_complete(uint16_t net_idx, uint16_t addr, uint8_t flags, uint32_t iv_index)
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{
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APP_DBG(" ");
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}
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/*********************************************************************
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* @fn prov_reset
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*
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* @brief 复位配网功能回调
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*
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* @return none
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*/
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static void prov_reset(void)
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{
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APP_DBG("");
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prov_enable();
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}
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/*********************************************************************
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* @fn cfg_srv_rsp_handler
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*
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* @brief config 模型服务回调
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*
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* @param val - 回调参数，包括命令类型、配置命令执行状态
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*
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* @return none
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*/
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static void cfg_srv_rsp_handler( const cfg_srv_status_t *val )
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{
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if(val->cfgHdr.status)
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{
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// 配置命令执行不成功
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APP_DBG("warning opcode 0x%02x", val->cfgHdr.opcode);
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return;
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}
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if(val->cfgHdr.opcode == OP_APP_KEY_ADD)
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{
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APP_DBG("App Key Added");
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}
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else if(val->cfgHdr.opcode == OP_MOD_APP_BIND)
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{
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APP_DBG("Vendor Model Binded");
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}
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else if(val->cfgHdr.opcode == OP_MOD_SUB_ADD)
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{
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APP_DBG("Vendor Model Subscription Set");
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}
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else
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{
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APP_DBG("Unknow opcode 0x%02x", val->cfgHdr.opcode);
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}
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}
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/*********************************************************************
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* @fn keyPress
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*
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* @brief 按键回调
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*
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* @param keys - 按键类型
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*
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* @return none
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*/
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void keyPress(uint8_t keys)
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{
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APP_DBG("keys %d ", keys);
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switch(keys)
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{
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default:
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break;
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}
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}
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/*********************************************************************
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* @fn blemesh_on_sync
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*
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* @brief 同步mesh参数，启用对应功能，不建议修改
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*
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* @return none
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*/
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void blemesh_on_sync(void)
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{
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int err;
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mem_info_t info;
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uint8_t i;
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if(tmos_memcmp(VER_MESH_LIB, VER_MESH_FILE, strlen(VER_MESH_FILE)) == FALSE)
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{
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PRINT("head file error...\n");
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while(1);
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}
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info.base_addr = MESH_MEM;
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info.mem_len = ARRAY_SIZE(MESH_MEM);
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#if(CONFIG_BLE_MESH_FRIEND)
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friend_init_register(bt_mesh_friend_init, friend_state);
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#endif /* FRIEND */
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#if(CONFIG_BLE_MESH_LOW_POWER)
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lpn_init_register(bt_mesh_lpn_init, lpn_state);
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#endif /* LPN */
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#if(defined(BLE_MAC)) && (BLE_MAC == TRUE)
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for(i = 0; i < 6; i++)
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MACAddr[i] = MacAddr[5 - i];
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tmos_memcpy(dev_uuid, MACAddr, 6);
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#else
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FLASH_GetMACAddress(MACAddr);
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tmos_memcpy(dev_uuid, MACAddr, 6);
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#endif
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err = bt_mesh_cfg_set(&app_mesh_cfg, &app_dev, MACAddr, &info);
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if(err)
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{
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APP_DBG("Unable set configuration (err:%d)", err);
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return;
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}
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hal_rf_init();
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err = bt_mesh_comp_register(&app_comp);
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#if(CONFIG_BLE_MESH_RELAY)
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bt_mesh_relay_init();
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#endif /* RELAY */
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#if(CONFIG_BLE_MESH_PROXY || CONFIG_BLE_MESH_PB_GATT)
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#if(CONFIG_BLE_MESH_PROXY)
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bt_mesh_proxy_beacon_init_register((void *)bt_mesh_proxy_beacon_init);
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gatts_notify_register(bt_mesh_gatts_notify);
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proxy_gatt_enable_register(bt_mesh_proxy_gatt_enable);
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#endif /* PROXY */
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#if(CONFIG_BLE_MESH_PB_GATT)
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proxy_prov_enable_register(bt_mesh_proxy_prov_enable);
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#endif /* PB_GATT */
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bt_mesh_proxy_init();
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#endif /* PROXY || PB-GATT */
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#if(CONFIG_BLE_MESH_PROXY_CLI)
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bt_mesh_proxy_client_init(cli); //待添加
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#endif /* PROXY_CLI */
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bt_mesh_prov_retransmit_init();
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#if(!CONFIG_BLE_MESH_PB_GATT)
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adv_link_rx_buf_register(&rx_buf);
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#endif /* !PB_GATT */
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err = bt_mesh_prov_init(&app_prov);
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bt_mesh_mod_init();
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bt_mesh_net_init();
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bt_mesh_trans_init();
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bt_mesh_beacon_init();
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bt_mesh_adv_init();
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#if((CONFIG_BLE_MESH_PB_GATT) || (CONFIG_BLE_MESH_PROXY) || (CONFIG_BLE_MESH_OTA))
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bt_mesh_conn_adv_init();
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#endif /* PROXY || PB-GATT || OTA */
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#if(CONFIG_BLE_MESH_SETTINGS)
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bt_mesh_settings_init();
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#endif /* SETTINGS */
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#if(CONFIG_BLE_MESH_PROXY_CLI)
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bt_mesh_proxy_cli_adapt_init();
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#endif /* PROXY_CLI */
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#if((CONFIG_BLE_MESH_PROXY) || (CONFIG_BLE_MESH_PB_GATT) || \
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(CONFIG_BLE_MESH_PROXY_CLI) || (CONFIG_BLE_MESH_OTA))
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bt_mesh_adapt_init();
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#endif /* PROXY || PB-GATT || PROXY_CLI || OTA */
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if(err)
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{
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APP_DBG("Initializing mesh failed (err %d)", err);
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return;
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}
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APP_DBG("Bluetooth initialized");
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#if(CONFIG_BLE_MESH_SETTINGS)
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settings_load();
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#endif /* SETTINGS */
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if(bt_mesh_is_provisioned())
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{
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APP_DBG("Mesh network restored from flash");
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}
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else
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{
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prov_enable();
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}
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APP_DBG("Mesh initialized");
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}
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/*********************************************************************
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* @fn App_Init
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*
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* @brief 应用层初始化
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*
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* @return none
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*/
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void App_Init()
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{
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App_TaskID = TMOS_ProcessEventRegister(App_ProcessEvent);
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blemesh_on_sync();
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HAL_KeyInit();
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HalKeyConfig(keyPress);
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tmos_set_event(App_TaskID, APP_USER_EVT);
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}
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/*********************************************************************
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* @fn App_ProcessEvent
|
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*
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* @brief 应用层事件处理函数
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*
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* @param task_id - The TMOS assigned task ID.
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* @param events - events to process. This is a bit map and can
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* contain more than one event.
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*
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* @return events not processed
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*/
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static uint16_t App_ProcessEvent(uint8_t task_id, uint16_t events)
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{
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if(events & APP_USER_EVT)
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{
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return (events ^ APP_USER_EVT);
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}
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||||
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||||
// Discard unknown events
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return 0;
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||||
}
|
||||
|
||||
/******************************** endfile @ main ******************************/
|
||||
@@ -0,0 +1,186 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : app_generic_onoff_model.c
|
||||
* Author : WCH
|
||||
* Version : V1.0
|
||||
* Date : 2021/03/24
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
#include "CONFIG.h"
|
||||
#include "MESH_LIB.h"
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||||
#include "app_mesh_config.h"
|
||||
#include "app_generic_onoff_model.h"
|
||||
|
||||
/*********************************************************************
|
||||
* GLOBAL TYPEDEFS
|
||||
*/
|
||||
|
||||
#define ALI_DEF_TTL (10)
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||||
|
||||
/*********************************************************************
|
||||
* @fn read_led_state
|
||||
*
|
||||
* @brief 获取当前灯状态.
|
||||
*
|
||||
* @param led_pin - 引脚.
|
||||
*
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||||
* @return 灯状态
|
||||
*/
|
||||
BOOL read_led_state(uint32_t led_pin)
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||||
{
|
||||
return (GPIO_ReadOutputDataBit(MSG_GPIO, led_pin) > 0) ? 0 : 1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn set_led_state
|
||||
*
|
||||
* @brief 设置当前灯状态.
|
||||
*
|
||||
* @param led_pin - 引脚.
|
||||
* @param on - 状态.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void set_led_state(uint32_t led_pin, BOOL on)
|
||||
{
|
||||
RCC_APB2PeriphClockCmd(MSG_PCENR, ENABLE);
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = led_pin;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(MSG_GPIO, &GPIO_InitStructure);
|
||||
|
||||
on ? GPIO_WriteBit(MSG_GPIO, led_pin, Bit_RESET) : GPIO_WriteBit(MSG_GPIO, led_pin, Bit_SET);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn toggle_led_state
|
||||
*
|
||||
* @brief 翻转当前灯状态
|
||||
*
|
||||
* @param led_pin - 引脚.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void toggle_led_state(uint32_t led_pin)
|
||||
{
|
||||
RCC_APB2PeriphClockCmd(MSG_PCENR, ENABLE);
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = led_pin;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
GPIO_WriteBit(MSG_GPIO, led_pin, Bit_SET-GPIO_ReadOutputDataBit(MSG_GPIO, led_pin));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn gen_onoff_status
|
||||
*
|
||||
* @brief 回复天猫精灵开关状态
|
||||
*
|
||||
* @param model - 模型参数.
|
||||
* @param ctx - 数据参数.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void gen_onoff_status(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx)
|
||||
{
|
||||
NET_BUF_SIMPLE_DEFINE(msg, 32);
|
||||
int err;
|
||||
|
||||
bt_mesh_model_msg_init(&msg, BLE_MESH_MODEL_OP_GEN_ONOFF_STATUS);
|
||||
net_buf_simple_add_u8(&msg, read_led_state(MSG_PIN));
|
||||
|
||||
APP_DBG("ttl: 0x%02x dst: 0x%04x", ctx->recv_ttl, ctx->recv_dst);
|
||||
|
||||
if(ctx->recv_ttl != ALI_DEF_TTL)
|
||||
{
|
||||
ctx->send_ttl = BLE_MESH_TTL_DEFAULT;
|
||||
}
|
||||
else
|
||||
{
|
||||
ctx->send_ttl = 0;
|
||||
}
|
||||
|
||||
err = bt_mesh_model_send(model, ctx, &msg, NULL, NULL);
|
||||
if(err)
|
||||
{
|
||||
APP_DBG("send status failed: %d", err);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn gen_onoff_get
|
||||
*
|
||||
* @brief 天猫精灵下发的获取开关状态命令
|
||||
*
|
||||
* @param model - 模型参数.
|
||||
* @param ctx - 数据参数.
|
||||
* @param buf - 数据内容.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void gen_onoff_get(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf)
|
||||
{
|
||||
APP_DBG(" ");
|
||||
|
||||
gen_onoff_status(model, ctx);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn gen_onoff_set
|
||||
*
|
||||
* @brief 天猫精灵下发的设置开关状态命令，如果与当前状态不同,还需要发送ind给天猫
|
||||
*
|
||||
* @param model - 模型参数.
|
||||
* @param ctx - 数据参数.
|
||||
* @param buf - 数据内容.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void gen_onoff_set(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf)
|
||||
{
|
||||
APP_DBG("ttl: 0x%02x dst: 0x%04x rssi: %d", ctx->recv_ttl, ctx->recv_dst, ctx->recv_rssi);
|
||||
|
||||
set_led_state(MSG_PIN, buf->data[0]);
|
||||
gen_onoff_status(model, ctx);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn gen_onoff_set_unack
|
||||
*
|
||||
* @brief 天猫精灵下发的设置开关状态命令(无应答)
|
||||
*
|
||||
* @param model - 模型参数.
|
||||
* @param ctx - 数据参数.
|
||||
* @param buf - 数据内容.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void gen_onoff_set_unack(struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf)
|
||||
{
|
||||
uint8_t status;
|
||||
|
||||
APP_DBG(" ");
|
||||
|
||||
status = read_led_state(MSG_PIN);
|
||||
if(status != buf->data[0])
|
||||
{
|
||||
set_led_state(MSG_PIN, buf->data[0]);
|
||||
}
|
||||
}
|
||||
|
||||
const struct bt_mesh_model_op gen_onoff_op[] = {
|
||||
{BLE_MESH_MODEL_OP_GEN_ONOFF_GET, 0, gen_onoff_get},
|
||||
{BLE_MESH_MODEL_OP_GEN_ONOFF_SET, 2, gen_onoff_set},
|
||||
{BLE_MESH_MODEL_OP_GEN_ONOFF_SET_UNACK, 2, gen_onoff_set_unack},
|
||||
BLE_MESH_MODEL_OP_END,
|
||||
};
|
||||
|
||||
/******************************** endfile @ main ******************************/
|
||||
@@ -0,0 +1,106 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.2
|
||||
* Date : 2022/06/22
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Header file contains */
|
||||
#include "CONFIG.h"
|
||||
#include "MESH_LIB.h"
|
||||
#include "HAL.h"
|
||||
#include "app_mesh_config.h"
|
||||
#include "app.h"
|
||||
|
||||
/*********************************************************************
|
||||
* GLOBAL TYPEDEFS
|
||||
*/
|
||||
__attribute__((aligned(4))) uint32_t MEM_BUF[BLE_MEMHEAP_SIZE / 4];
|
||||
#if(defined(BLE_MAC)) && (BLE_MAC == TRUE)
|
||||
const uint8_t MacAddr[6] = {0x84, 0xC2, 0xE4, 0x03, 0x02, 0x02};
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn bt_mesh_lib_init
|
||||
*
|
||||
* @brief mesh ¿â³õʼ»¯
|
||||
*
|
||||
* @return state
|
||||
*/
|
||||
uint8_t bt_mesh_lib_init(void)
|
||||
{
|
||||
uint8_t ret;
|
||||
|
||||
if(tmos_memcmp(VER_MESH_LIB, VER_MESH_FILE, strlen(VER_MESH_FILE)) == FALSE)
|
||||
{
|
||||
PRINT("mesh head file error...\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
ret = RF_RoleInit();
|
||||
|
||||
#if((CONFIG_BLE_MESH_PROXY) || \
|
||||
(CONFIG_BLE_MESH_PB_GATT) || \
|
||||
(CONFIG_BLE_MESH_OTA))
|
||||
ret = GAPRole_PeripheralInit();
|
||||
#endif /* PROXY || PB-GATT || OTA */
|
||||
|
||||
#if(CONFIG_BLE_MESH_PROXY_CLI)
|
||||
ret = GAPRole_CentralInit();
|
||||
#endif /* CONFIG_BLE_MESH_PROXY_CLI */
|
||||
|
||||
MeshTimer_Init();
|
||||
MeshDeamon_Init();
|
||||
ble_sm_alg_ecc_init();
|
||||
|
||||
#if(CONFIG_BLE_MESH_IV_UPDATE_TEST)
|
||||
bt_mesh_iv_update_test(TRUE);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Main_Circulation
|
||||
*
|
||||
* @brief Main loop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((section(".highcode")))
|
||||
__attribute__((noinline))
|
||||
void Main_Circulation(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
TMOS_SystemProcess();
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main function
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
Delay_Init();
|
||||
#ifdef DEBUG
|
||||
USART_Printf_Init( 115200 );
|
||||
#endif
|
||||
PRINT("%s\n", VER_LIB);
|
||||
WCHBLE_Init();
|
||||
HAL_Init();
|
||||
bt_mesh_lib_init();
|
||||
App_Init();
|
||||
Main_Circulation();
|
||||
}
|
||||
|
||||
/******************************** endfile @ main ******************************/
|
||||
@@ -0,0 +1,182 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : app_mesh_config.c
|
||||
* Author : WCH
|
||||
* Version : V1.2
|
||||
* Date : 2022/06/22
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Header file contains */
|
||||
#include "CONFIG.h"
|
||||
#include "app_mesh_config.h"
|
||||
#include "MESH_LIB.h"
|
||||
|
||||
/*********************************************************************
|
||||
* GLOBAL TYPEDEFS
|
||||
*/
|
||||
const ble_mesh_cfg_t app_mesh_cfg = {
|
||||
.common_cfg.adv_buf_count = CONFIG_MESH_ADV_BUF_COUNT_DEF,
|
||||
.common_cfg.rpl_count = CONFIG_MESH_RPL_COUNT_DEF,
|
||||
.common_cfg.allow_rpl_cycle = CONFIG_MESH_ALLOW_RPL_CYCLE,
|
||||
.common_cfg.allow_same_addr = CONFIG_MESH_ALLOW_SAME_ADDR,
|
||||
.common_cfg.ivu_divider = CONFIG_MESH_IVU_DIVIDER_DEF,
|
||||
.common_cfg.mod_key_count = CONFIG_MESH_MOD_KEY_COUNT_DEF,
|
||||
.common_cfg.mod_group_count = CONFIG_MESH_MOD_GROUP_COUNT_DEF,
|
||||
|
||||
.proxy_cfg.pxyfilter_count = CONFIG_MESH_PROXY_FILTER_DEF,
|
||||
|
||||
.net_cfg.msgcache_count = CONFIG_MESH_MSG_CACHE_DEF,
|
||||
.net_cfg.subnet_count = CONFIG_MESH_SUBNET_COUNT_DEF,
|
||||
.net_cfg.appkey_count = CONFIG_MESH_APPKEY_COUNT_DEF,
|
||||
.net_cfg.unseg_length = CONFIG_MESH_UNSEG_LENGTH_DEF,
|
||||
.net_cfg.txseg_max = CONFIG_MESH_TX_SEG_DEF,
|
||||
.net_cfg.txseg_count = CONFIG_MESH_TX_SEG_COUNT_DEF,
|
||||
.net_cfg.rxseg_count = CONFIG_MESH_RX_SEG_COUNT_DEF,
|
||||
.net_cfg.rxsdu_max = CONFIG_MESH_RX_SDU_DEF,
|
||||
.net_cfg.label_count = CONFIG_MESH_LABEL_COUNT_DEF,
|
||||
|
||||
.store_cfg.seq_store_rate = CONFIG_MESH_SEQ_STORE_RATE_DEF,
|
||||
.store_cfg.rpl_store_rate = CONFIG_MESH_RPL_STORE_RATE_DEF,
|
||||
.store_cfg.store_rate = CONFIG_MESH_STORE_RATE_DEF,
|
||||
|
||||
.friend_cfg.frndseg_rx = CONFIG_MESH_FRIEND_SEG_RX_COUNT_DEF,
|
||||
.friend_cfg.frndsub_size = CONFIG_MESH_FRIEND_SUB_SIZE_DEF,
|
||||
.friend_cfg.frndlpn_count = CONFIG_MESH_FRIEND_LPN_COUNT_DEF,
|
||||
.friend_cfg.frndqueue_size = CONFIG_MESH_QUEUE_SIZE_DEF,
|
||||
.friend_cfg.frndrecv_win = CONFIG_MESH_FRIEND_RECV_WIN_DEF,
|
||||
|
||||
.lpn_cfg.lpnmin_size = CONFIG_MESH_LPN_REQ_QUEUE_SIZE_DEF,
|
||||
.lpn_cfg.lpnrssi_factor = 0,
|
||||
.lpn_cfg.lpnrecv_factor = 0,
|
||||
.lpn_cfg.lpnpoll_interval = CONFIG_MESH_LPN_POLLINTERVAL_DEF,
|
||||
.lpn_cfg.lpnpoll_timeout = CONFIG_MESH_LPN_POLLTIMEOUT_DEF,
|
||||
.lpn_cfg.lpnrecv_delay = CONFIG_MESH_LPN_RECV_DELAY_DEF,
|
||||
.lpn_cfg.lpnretry_timeout = CONFIG_MESH_RETRY_TIMEOUT_DEF,
|
||||
|
||||
.prov_cfg.node_count = CONFIG_MESH_PROV_NODE_COUNT_DEF,
|
||||
.rf_cfg.rf_accessAddress = CONFIG_MESH_RF_ACCESSADDRESS,
|
||||
.rf_cfg.rf_channel_37 = CONFIG_MESH_RF_CHANNEL_37,
|
||||
.rf_cfg.rf_channel_38 = CONFIG_MESH_RF_CHANNEL_38,
|
||||
.rf_cfg.rf_channel_39 = CONFIG_MESH_RF_CHANNEL_39,
|
||||
};
|
||||
|
||||
/*********************************************************************
|
||||
* @fn read_flash
|
||||
*
|
||||
* @brief read flash
|
||||
*
|
||||
* @param offset - 地址偏移
|
||||
* @param data - 数据指针
|
||||
* @param len - 长度
|
||||
*
|
||||
* @return always success
|
||||
*/
|
||||
int read_flash(int offset, void *data, unsigned int len)
|
||||
{
|
||||
tmos_memcpy(data, (uint8_t*)offset, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn write_flash
|
||||
*
|
||||
* @brief write flash
|
||||
*
|
||||
* @param offset - 地址偏移
|
||||
* @param data - 数据指针
|
||||
* @param len - 长度
|
||||
*
|
||||
* @return state
|
||||
*/
|
||||
int write_flash(int offset, const void *data, unsigned int len)
|
||||
{
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
__attribute__((aligned(4))) uint8_t vec[64]={0};
|
||||
uint8_t i;
|
||||
|
||||
if(len > sizeof(vec))
|
||||
{
|
||||
return -E2BIG;
|
||||
}
|
||||
|
||||
memcpy(vec, data, len);
|
||||
|
||||
FLASH_Unlock();
|
||||
for( i=0; i<(len+1)/2; i++)
|
||||
{
|
||||
status = FLASH_ProgramHalfWord(offset+i*2,vec[i*2]|(vec[i*2+1]<<8));
|
||||
if( status != FLASH_COMPLETE )
|
||||
{
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
FLASH_Lock();
|
||||
|
||||
return NOERR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn erase_flash
|
||||
*
|
||||
* @brief erase flash
|
||||
*
|
||||
* @param offset - 地址偏移
|
||||
* @param len - 长度
|
||||
*
|
||||
* @return state
|
||||
*/
|
||||
int erase_flash(int offset, unsigned int len)
|
||||
{
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
if(len != 4096)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
FLASH_Unlock();
|
||||
status = FLASH_ErasePage(offset);
|
||||
FLASH_Lock();
|
||||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
return NOERR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn flash_write_protection
|
||||
*
|
||||
* @brief no used
|
||||
*
|
||||
* @param enable - no uesd
|
||||
*
|
||||
* @return always success
|
||||
*/
|
||||
int flash_write_protection(BOOL enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct device app_dev = {
|
||||
.api = {
|
||||
.read = read_flash,
|
||||
.write = write_flash,
|
||||
.erase = erase_flash,
|
||||
.write_protection = flash_write_protection,
|
||||
},
|
||||
.info = {
|
||||
.nvs_sector_cnt = CONFIG_MESH_SECTOR_COUNT_DEF,
|
||||
.nvs_write_size = sizeof(int),
|
||||
.nvs_sector_size = CONFIG_MESH_SECTOR_SIZE_DEF,
|
||||
.nvs_store_baddr = CONFIG_MESH_NVS_ADDR_DEF,
|
||||
},
|
||||
};
|
||||
|
||||
/******************************** endfile @ main ******************************/
|
||||
@@ -0,0 +1,74 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/06/16
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/*********************************************************************
|
||||
* INCLUDES
|
||||
*/
|
||||
#include "ch32v20x_it.h"
|
||||
#include "CONFIG.h"
|
||||
|
||||
/*********************************************************************
|
||||
* LOCAL FUNCTIONS
|
||||
*/
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void BB_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void LLE_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn BB_IRQHandler
|
||||
*
|
||||
* @brief BB Interrupt for BLE.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void BB_IRQHandler(void)
|
||||
{
|
||||
BB_IRQLibHandler();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LLE_IRQHandler
|
||||
*
|
||||
* @brief LLE Interrupt for BLE.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void LLE_IRQHandler(void)
|
||||
{
|
||||
LLE_IRQLibHandler();
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : app.h
|
||||
* Author : WCH
|
||||
* Version : V1.1
|
||||
* Date : 2021/11/18
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef app_H
|
||||
#define app_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define APP_USER_EVT (1 << 0)
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
void App_Init(void);
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : app_generic_onoff_model.h
|
||||
* Author : WCH
|
||||
* Version : V1.0
|
||||
* Date : 2018/11/12
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef app_generic_onoff_model_H
|
||||
#define app_generic_onoff_model_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "MESH_LIB.h"
|
||||
|
||||
#define MSG_PIN GPIO_Pin_14
|
||||
#define MSG_PCENR RCC_APB2Periph_GPIOB
|
||||
#define MSG_GPIO GPIOB
|
||||
|
||||
BOOL read_led_state(uint32_t led_pin);
|
||||
|
||||
extern const struct bt_mesh_model_op gen_onoff_op[];
|
||||
|
||||
void set_led_state(uint32_t led_pin, BOOL on);
|
||||
|
||||
void toggle_led_state(uint32_t led_pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,219 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : app_mesh_config.h
|
||||
* Author : WCH
|
||||
* Version : V1.1
|
||||
* Date : 2021/11/18
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef APP_MESH_CONFIG_H
|
||||
#define APP_MESH_CONFIG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**************************功能配置,建议直接参考不同例程*****************************/
|
||||
|
||||
// relay功能
|
||||
#define CONFIG_BLE_MESH_RELAY 1
|
||||
// 代理功能
|
||||
#define CONFIG_BLE_MESH_PROXY 1
|
||||
// GATT层配网功能
|
||||
#define CONFIG_BLE_MESH_PB_GATT 1
|
||||
// FLASH存储功能
|
||||
#define CONFIG_BLE_MESH_SETTINGS 1
|
||||
// 朋友节点功能
|
||||
#define CONFIG_BLE_MESH_FRIEND 0
|
||||
// 低功耗节点功能
|
||||
#define CONFIG_BLE_MESH_LOW_POWER 0
|
||||
// config模型客户端功能
|
||||
#define CONFIG_BLE_MESH_CFG_CLI 0
|
||||
// health模型客户端功能
|
||||
#define CONFIG_BLE_MESH_HLTH_CLI 0
|
||||
|
||||
/************************************参数配置******************************************/
|
||||
|
||||
// Net数据缓存个数
|
||||
#define CONFIG_MESH_ADV_BUF_COUNT_MIN (6)
|
||||
#define CONFIG_MESH_ADV_BUF_COUNT_DEF (10)
|
||||
#define CONFIG_MESH_ADV_BUF_COUNT_MAX (256)
|
||||
|
||||
// RPL数据缓存个数,需不小于配网发起者支持的配网设备节点个数
|
||||
#define CONFIG_MESH_RPL_COUNT_MIN (6)
|
||||
#define CONFIG_MESH_RPL_COUNT_DEF (20)
|
||||
#define CONFIG_MESH_RPL_COUNT_MAX (128)
|
||||
|
||||
// RPL缓存循环使用，开启后网络中节点数量不受RPL限制，但NVS将不存储RPL数据
|
||||
#define CONFIG_MESH_ALLOW_RPL_CYCLE (FALSE)
|
||||
|
||||
// IV Update State Timer 基于96H的分频系数
|
||||
#define CONFIG_MESH_IVU_DIVIDER_MIN (1)
|
||||
#define CONFIG_MESH_IVU_DIVIDER_DEF (96)
|
||||
#define CONFIG_MESH_IVU_DIVIDER_MAX (96)
|
||||
|
||||
// 代理黑白名单功能存储个数
|
||||
#define CONFIG_MESH_PROXY_FILTER_MIN (2)
|
||||
#define CONFIG_MESH_PROXY_FILTER_DEF (5)
|
||||
#define CONFIG_MESH_PROXY_FILTER_MAX (20)
|
||||
|
||||
// 消息贮存个数
|
||||
#define CONFIG_MESH_MSG_CACHE_MIN (3)
|
||||
#define CONFIG_MESH_MSG_CACHE_DEF (20)
|
||||
#define CONFIG_MESH_MSG_CACHE_MAX (20)
|
||||
|
||||
// 子网络个数
|
||||
#define CONFIG_MESH_SUBNET_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_SUBNET_COUNT_DEF (1)
|
||||
#define CONFIG_MESH_SUBNET_COUNT_MAX (4)
|
||||
|
||||
// APP key个数
|
||||
#define CONFIG_MESH_APPKEY_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_APPKEY_COUNT_DEF (3)
|
||||
#define CONFIG_MESH_APPKEY_COUNT_MAX (5)
|
||||
|
||||
// 可存储的模型密钥数量
|
||||
#define CONFIG_MESH_MOD_KEY_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_MOD_KEY_COUNT_DEF (1)
|
||||
#define CONFIG_MESH_MOD_KEY_COUNT_MAX (3)
|
||||
|
||||
// 可存储的订阅地址数量
|
||||
#define CONFIG_MESH_MOD_GROUP_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_MOD_GROUP_COUNT_DEF (6)
|
||||
#define CONFIG_MESH_MOD_GROUP_COUNT_MAX (64)
|
||||
|
||||
// 是否允许一个网络中存在同地址的节点（使能后分包功能不可用）
|
||||
#define CONFIG_MESH_ALLOW_SAME_ADDR (FALSE)
|
||||
|
||||
// 不分包消息支持的长度（超过此长度则需要分包，默认值为7，注意同网络里所有设备配置需统一）
|
||||
#define CONFIG_MESH_UNSEG_LENGTH_MIN (7)
|
||||
#define CONFIG_MESH_UNSEG_LENGTH_DEF (7)
|
||||
#define CONFIG_MESH_UNSEG_LENGTH_MAX (221)
|
||||
|
||||
// 每个消息的最大分包数
|
||||
#define CONFIG_MESH_TX_SEG_MIN (2)
|
||||
#define CONFIG_MESH_TX_SEG_DEF (8)
|
||||
#define CONFIG_MESH_TX_SEG_MAX (32)
|
||||
|
||||
// 允许同时存在的分包消息的最大发送个数
|
||||
#define CONFIG_MESH_TX_SEG_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_TX_SEG_COUNT_DEF (2)
|
||||
#define CONFIG_MESH_TX_SEG_COUNT_MAX (4)
|
||||
|
||||
// 允许同时存在的分包消息的最大接收个数
|
||||
#define CONFIG_MESH_RX_SEG_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_RX_SEG_COUNT_DEF (2)
|
||||
#define CONFIG_MESH_RX_SEG_COUNT_MAX (4)
|
||||
|
||||
// 每个接收的分包消息的最大字节数
|
||||
#define CONFIG_MESH_RX_SDU_MIN (12)
|
||||
#define CONFIG_MESH_RX_SDU_DEF (192)
|
||||
#define CONFIG_MESH_RX_SDU_MAX (384)
|
||||
|
||||
// 虚拟地址个数
|
||||
#define CONFIG_MESH_LABEL_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_LABEL_COUNT_DEF (2)
|
||||
#define CONFIG_MESH_LABEL_COUNT_MAX (4)
|
||||
|
||||
// NVS存储使用扇区个数
|
||||
#define CONFIG_MESH_SECTOR_COUNT_MIN (2)
|
||||
#define CONFIG_MESH_SECTOR_COUNT_DEF (3)
|
||||
|
||||
// NVS存储扇区大小
|
||||
#define CONFIG_MESH_SECTOR_SIZE_DEF (4096)
|
||||
|
||||
// NVS存储首地址
|
||||
#define CONFIG_MESH_NVS_ADDR_DEF (448*1024+0x08000000)
|
||||
|
||||
// RPL更新超过多少次后存储
|
||||
#define CONFIG_MESH_RPL_STORE_RATE_MIN (5)
|
||||
#define CONFIG_MESH_RPL_STORE_RATE_DEF (60)
|
||||
#define CONFIG_MESH_RPL_STORE_RATE_MAX (3600)
|
||||
|
||||
// SEQ更新超过多少次后存储
|
||||
#define CONFIG_MESH_SEQ_STORE_RATE_MIN (5)
|
||||
#define CONFIG_MESH_SEQ_STORE_RATE_DEF (60)
|
||||
#define CONFIG_MESH_SEQ_STORE_RATE_MAX (3600)
|
||||
|
||||
// 其他信息更新后存储的超时时长(s)
|
||||
#define CONFIG_MESH_STORE_RATE_MIN (2)
|
||||
#define CONFIG_MESH_STORE_RATE_DEF (2)
|
||||
#define CONFIG_MESH_STORE_RATE_MAX (5)
|
||||
|
||||
// 朋友节点支持的每个消息的分包个数
|
||||
#define CONFIG_MESH_FRIEND_SEG_RX_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_FRIEND_SEG_RX_COUNT_DEF (2)
|
||||
#define CONFIG_MESH_FRIEND_SEG_RX_COUNT_MAX (4)
|
||||
|
||||
// 朋友节点支持的订阅个数
|
||||
#define CONFIG_MESH_FRIEND_SUB_SIZE_MIN (1)
|
||||
#define CONFIG_MESH_FRIEND_SUB_SIZE_DEF (4)
|
||||
#define CONFIG_MESH_FRIEND_SUB_SIZE_MAX (8)
|
||||
|
||||
// 朋友节点支持的低功耗节点个数
|
||||
#define CONFIG_MESH_FRIEND_LPN_COUNT_MIN (1)
|
||||
#define CONFIG_MESH_FRIEND_LPN_COUNT_DEF (1)
|
||||
#define CONFIG_MESH_FRIEND_LPN_COUNT_MAX (4)
|
||||
|
||||
// 朋友节点存储的消息队列大小
|
||||
#define CONFIG_MESH_QUEUE_SIZE_MIN (2)
|
||||
#define CONFIG_MESH_QUEUE_SIZE_DEF (4)
|
||||
#define CONFIG_MESH_QUEUE_SIZE_MAX (30)
|
||||
|
||||
// 朋友节点接收窗口大小(ms)
|
||||
#define CONFIG_MESH_FRIEND_RECV_WIN_MIN (1)
|
||||
#define CONFIG_MESH_FRIEND_RECV_WIN_DEF (30)
|
||||
#define CONFIG_MESH_FRIEND_RECV_WIN_MAX (255)
|
||||
|
||||
// 低功耗节点的请求消息队列大小
|
||||
#define CONFIG_MESH_LPN_REQ_QUEUE_SIZE_MIN (2)
|
||||
#define CONFIG_MESH_LPN_REQ_QUEUE_SIZE_DEF (2)
|
||||
#define CONFIG_MESH_LPN_REQ_QUEUE_SIZE_MAX (20)
|
||||
|
||||
// 低功耗节点的请求消息间隔(100ms)
|
||||
#define CONFIG_MESH_LPN_POLLINTERVAL_MIN (1)
|
||||
#define CONFIG_MESH_LPN_POLLINTERVAL_DEF (80)
|
||||
#define CONFIG_MESH_LPN_POLLINTERVAL_MAX (3455999)
|
||||
|
||||
// 低功耗节点的请求消息超时时长(100ms)
|
||||
#define CONFIG_MESH_LPN_POLLTIMEOUT_MIN (10)
|
||||
#define CONFIG_MESH_LPN_POLLTIMEOUT_DEF (300)
|
||||
#define CONFIG_MESH_LPN_POLLTIMEOUT_MAX (3455999)
|
||||
|
||||
// 低功耗节点支持的接收延迟(ms)
|
||||
#define CONFIG_MESH_LPN_RECV_DELAY_MIN (10)
|
||||
#define CONFIG_MESH_LPN_RECV_DELAY_DEF (100)
|
||||
#define CONFIG_MESH_LPN_RECV_DELAY_MAX (255)
|
||||
|
||||
// 朋友关系重建等待时长(s)
|
||||
#define CONFIG_MESH_RETRY_TIMEOUT_MIN (3)
|
||||
#define CONFIG_MESH_RETRY_TIMEOUT_DEF (10)
|
||||
#define CONFIG_MESH_RETRY_TIMEOUT_MAX (60)
|
||||
|
||||
// 配网发起者支持的配网设备节点个数
|
||||
#define CONFIG_MESH_PROV_NODE_COUNT_DEF (0)
|
||||
|
||||
// ADV_RF配置
|
||||
#define CONFIG_MESH_RF_ACCESSADDRESS (0x8E89BED6)
|
||||
#define CONFIG_MESH_RF_CHANNEL_37 (37)
|
||||
#define CONFIG_MESH_RF_CHANNEL_38 (38)
|
||||
#define CONFIG_MESH_RF_CHANNEL_39 (39)
|
||||
|
||||
#define APP_DBG(X...) \
|
||||
if(1) \
|
||||
{ \
|
||||
PRINT("APP_DBG %s> ", __FUNCTION__); \
|
||||
PRINT(X); \
|
||||
PRINT("\n"); \
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,37 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/06/16
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/06/16
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/06/16
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
@@ -0,0 +1,989 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user