first submission
This commit is contained in:
qiyongshuang
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/********************************** (C) COPYRIGHT *******************************
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* File Name : IAP_Task.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2022/05/25
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* Description : IAP related functions.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include <stdlib.h>
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#include <string.h>
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#include "debug.h"
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#include "wchnet.h"
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#include "IAP_Task.h"
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__attribute__((__aligned__(4))) u8 dataDealBuf[RECE_BUF_LEN] = {0};
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ethDataDeal dataDeal = { //Ring buffer parameter initialization
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.readIndex = 0,
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.writeIndex = 0,
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.buffUsedLen = 0,
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.dataBuff = dataDealBuf,
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};
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u32 fileDataLen = 0; //IAP file data length
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u32 fileCheckSum = 0; //IAP file data checksum
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u32 flashProgramLen = 0; //length of data written to backup area
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iapFileHeader iapPara; //IAP file parameters
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extern u8 SocketId;
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/*********************************************************************
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* @fn IAP_EEPROM_ERASE
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*
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* @brief erase Data-Flash block, minimal block is 256B
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*
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* @param Page_Address - the address of the page being erased.
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* Length - Erased data length
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*
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* @return none
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*/
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void IAP_EEPROM_ERASE(uint32_t Page_Address, u32 Length)
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{
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u32 NbrOfPage, EraseCounter;
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FLASH_Unlock_Fast();
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NbrOfPage = Length / FLASH_PAGE_SIZE;
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for (EraseCounter = 0; EraseCounter < NbrOfPage; EraseCounter++) {
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FLASH_ErasePage_Fast( Page_Address + (FLASH_PAGE_SIZE * EraseCounter)); //Erase 256B
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}
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FLASH_Lock_Fast();
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}
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/*********************************************************************
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* @fn IAP_EEPROM_WRITE
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*
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* @brief write Data-Flash data block
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*
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* @param StartAddr - the address of the page being written.
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* Buffer - data buff
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* Length - written data length
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*
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* @return FLASH_Status
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*/
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void IAP_EEPROM_WRITE( u32 StartAddr, u8 *Buffer, u32 Length )
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{
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u32 address = StartAddr;
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u32 *p_buff = (u32 *)Buffer;
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u16 pageNum = Length / FLASH_PAGE_SIZE;
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u16 lastDataNum = Length % FLASH_PAGE_SIZE;
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u16 i;
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if(pageNum){ //write by page(256B)
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FLASH_Unlock_Fast();
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for(i = 0; i < pageNum; i++)
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FLASH_ProgramPage_Fast((address + FLASH_PAGE_SIZE * i),(p_buff + (FLASH_PAGE_SIZE / 4) * i));
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FLASH_Lock_Fast();
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}
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if(lastDataNum){ //write by a half word(2B)
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u8 *p_buff1 = Buffer + FLASH_PAGE_SIZE * pageNum;
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address = StartAddr + FLASH_PAGE_SIZE * pageNum;
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FLASH_Unlock();
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for(i = 0; i < lastDataNum; i += 2)
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FLASH_ProgramHalfWord((address + i), *(u16 *)(p_buff1 + i));
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FLASH_Lock();
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}
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}
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/*********************************************************************
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* @fn IAP_EEPROM_READ
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*
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* @brief read Data-Flash data block
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*
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* @param StartAddr - the address of the page being read.
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* Buffer - data buff
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* Length - read data length
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*
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* @return none
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*/
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void IAP_EEPROM_READ( u32 StartAddr, u8 *Buffer, u32 Length )
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{
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u32 address = StartAddr;
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u32 *p_buff = (u32 *)Buffer;
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while(address < (StartAddr + Length))
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{
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*p_buff = (*(u32 *)address);
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address += 4;
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p_buff++;
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}
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}
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/*********************************************************************
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* @fn IAP_EEPROM_ERASE_44k
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*
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* @brief erase Data-Flash block, minimal block is 4KB.
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* This function is used to erase USER and BACKUP area.
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*
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* @param Page_Address - the address of the page being erased.
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*
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* @return none
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*/
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void IAP_EEPROM_ERASE_44k(u32 StartAddr)
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{
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u8 i = 0;
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FLASH_Unlock();
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for(i = 0; i < USER_IMAGE_MAX_SIZE / FLASH_BLOCK_SIZE; i++)
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FLASH_ErasePage(StartAddr + i * FLASH_BLOCK_SIZE);
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FLASH_Lock();
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}
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/*********************************************************************
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* @fn IAPParaInit
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*
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* @brief IAP parameters initialize
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*
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* @return none
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*/
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void IAPParaInit(void)
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{
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iapPara.iapFileCheckSum = 0;
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memset(iapPara.iapFileFlag, 0,sizeof(iapPara.iapFileFlag));
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iapPara.iapFileLen = 0;
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dataDeal.buffUsedLen = 0;
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dataDeal.dataBuff = dataDealBuf;
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dataDeal.readIndex = 0;
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dataDeal.writeIndex = 0;
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fileDataLen = 0;
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fileCheckSum = 0;
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flashProgramLen = 0;
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}
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/*********************************************************************
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* @fn IAPFileParaCheck
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*
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* @brief Verify upgrade file parameters.
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*
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* @param id - socket id.
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*
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* @return none
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*/
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void IAPFileParaCheck(u8 id)
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{
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u32 len;
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u8 *pBuff = NULL;
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len = WCHNET_SocketRecvLen(id,NULL);
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if(BIN_INF_LEN <= len){ //The first 512 bytes are the bin file parameters
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u8 buffIndex;
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u32 recLen = BIN_INF_LEN;
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pBuff = malloc(recLen);
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WCHNET_SocketRecv(id,pBuff,&recLen);
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memcpy(iapPara.iapFileFlag, pBuff, 8);
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buffIndex = 8;
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iapPara.iapFileLen |= *(pBuff + buffIndex++);
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iapPara.iapFileLen |= *(pBuff + buffIndex++) << 8;
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iapPara.iapFileLen |= *(pBuff + buffIndex++) << 16;
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iapPara.iapFileLen |= *(pBuff + buffIndex++) << 24;
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iapPara.iapFileCheckSum |= *(pBuff + buffIndex++);
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iapPara.iapFileCheckSum |= *(pBuff + buffIndex++) << 8;
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iapPara.iapFileCheckSum |= *(pBuff + buffIndex++) << 16;
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iapPara.iapFileCheckSum |= *(pBuff + buffIndex++) << 24;
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fileDataLen += recLen;
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free(pBuff);
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if(memcmp(iapPara.iapFileFlag, FILE_FLAG, strlen(FILE_FLAG))){
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printf("The file's flag is wrong!\r\n");
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WCHNET_SocketClose(SocketId, TCP_CLOSE_NORMAL);
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}
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}
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}
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/*Ring buffer data distribution*/
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//first case
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/**start******************readIndex********************writeIndex***************end**
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******| writable area |*******| readable area |********| writable area |****/
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//second case
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/**start******************writeIndex********************readIndex***************end**
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******| readable area |********| writable area |*******| readable area |****/
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/*********************************************************************
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* @fn receUpdatedFile
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*
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* @brief ETH receive data and save it to ring buff.
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*
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* @param id - socket id.
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*
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* @return none
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*/
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void receUpdatedFile(u8 id)
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{
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u32 len, remainLen, recLen;
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int8_t receive_state = -1;
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len = WCHNET_SocketRecvLen(id,NULL); //query length
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if( dataDeal.buffUsedLen < RECE_BUF_LEN ) //Ring buffer has free space
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{
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if(dataDeal.readIndex <= dataDeal.writeIndex){
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remainLen = RECE_BUF_LEN - dataDeal.writeIndex;
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if(len <= remainLen){
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recLen = len;
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}
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else{
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recLen = remainLen;
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}
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receive_state = WCHNET_SocketRecv(id,&dataDeal.dataBuff[dataDeal.writeIndex],&recLen);
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if(receive_state == WCHNET_ERR_SUCCESS){
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dataDeal.writeIndex = (dataDeal.writeIndex + recLen)%RECE_BUF_LEN;
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dataDeal.buffUsedLen += recLen;
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fileDataLen += recLen;
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if(len > remainLen){
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remainLen = RECE_BUF_LEN - dataDeal.buffUsedLen;
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len -= recLen;
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if(len <= remainLen){
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remainLen = len;
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}
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receive_state = WCHNET_SocketRecv(id,&dataDeal.dataBuff[dataDeal.writeIndex],&remainLen);
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if(receive_state == WCHNET_ERR_SUCCESS){
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dataDeal.writeIndex = (dataDeal.writeIndex + remainLen)%RECE_BUF_LEN;
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dataDeal.buffUsedLen += remainLen;
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fileDataLen += remainLen;
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}
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}
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}
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}
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else{
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remainLen = dataDeal.readIndex - dataDeal.writeIndex;
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if(len <= remainLen){
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remainLen = len;
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}
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receive_state = WCHNET_SocketRecv(id,&dataDeal.dataBuff[dataDeal.writeIndex],&remainLen);
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if(receive_state == WCHNET_ERR_SUCCESS){
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dataDeal.writeIndex = (dataDeal.writeIndex + remainLen)%RECE_BUF_LEN;
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dataDeal.buffUsedLen += remainLen;
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fileDataLen += remainLen;
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}
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}
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}
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else
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{
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printf("ETH receive buff busy\n");
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}
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}
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/*********************************************************************
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* @fn saveUpdatedFile
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*
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* @brief Save the upgrade file to the backup area.
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*
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* @return none
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*/
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void saveUpdatedFile(void)
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{
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u8 *pBuff = NULL, pageCnt = 0;
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u16 writableDataLen = 0, tempLen = 0;
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u32 remainLen = 0;
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if(dataDeal.buffUsedLen){
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pageCnt = dataDeal.buffUsedLen / FLASH_PAGE_SIZE; // Calculate the number of data pages
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if(pageCnt){
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writableDataLen = pageCnt * FLASH_PAGE_SIZE; //at least one page
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}
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else if(iapPara.iapFileLen == fileDataLen){ //Extract data that is less than one page at the end of the file
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writableDataLen = dataDeal.buffUsedLen;
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}
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else return;
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pBuff = malloc(writableDataLen);
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if(dataDeal.writeIndex <= dataDeal.readIndex){
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remainLen = RECE_BUF_LEN - dataDeal.readIndex;
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if(writableDataLen <= remainLen){
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tempLen = writableDataLen;
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}
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else{
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tempLen = remainLen;
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}
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memcpy(pBuff, &dataDeal.dataBuff[dataDeal.readIndex], tempLen);
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dataDeal.readIndex = (dataDeal.readIndex + tempLen)%RECE_BUF_LEN;
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dataDeal.buffUsedLen -= tempLen;
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if(remainLen < writableDataLen){
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remainLen = writableDataLen - tempLen;
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memcpy((pBuff + tempLen), &dataDeal.dataBuff[dataDeal.readIndex], remainLen);
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dataDeal.readIndex = (dataDeal.readIndex + remainLen)%RECE_BUF_LEN;
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dataDeal.buffUsedLen -= remainLen;
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}
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IAP_EEPROM_WRITE((BACKUP_IMAGE_START_ADD + flashProgramLen), pBuff, writableDataLen );
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}
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else{
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memcpy(pBuff, &dataDeal.dataBuff[dataDeal.readIndex], writableDataLen);
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dataDeal.readIndex = (dataDeal.readIndex + writableDataLen)%RECE_BUF_LEN;
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dataDeal.buffUsedLen -= writableDataLen;
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IAP_EEPROM_WRITE((BACKUP_IMAGE_START_ADD + flashProgramLen), pBuff, writableDataLen );
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}
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flashProgramLen += writableDataLen;
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for(u16 i = 0; i < (writableDataLen / 4); i++) //Calculate checksum
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fileCheckSum += *((u32 *)pBuff + i);
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/*Calculate the checksum of data less than 4 bytes at the end of the file*/
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if((writableDataLen % 4) != 0){
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u8 lastDataLen = writableDataLen % 4;
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u8 temBuff[4] = {0};
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memcpy(temBuff, (pBuff + writableDataLen - lastDataLen), lastDataLen);
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fileCheckSum += *(u32 *)temBuff;
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}
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free(pBuff);
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/*After the data is saved, compare the checksum. If the checksum is correct,
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* update the upgrade flag. Disconnect if checksum error.*/
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if(iapPara.iapFileLen == (flashProgramLen + BIN_INF_LEN)){
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if(fileCheckSum == iapPara.iapFileCheckSum){
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printf("FileCheckSum is right!\r\n");
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u32 updateFlag = IMAGE_FLAG_UPDATE;
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IAP_EEPROM_ERASE(UPDATA_FLAG_STORAGE_ADD, FLASH_PAGE_SIZE);
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IAP_EEPROM_WRITE(UPDATA_FLAG_STORAGE_ADD, (u8 *)&updateFlag, 4);
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WCHNET_SocketClose(SocketId, TCP_CLOSE_RST);
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NVIC_SystemReset();
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}
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else{
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printf("FileCheckSum is wrong!\r\n");
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WCHNET_SocketClose(SocketId, TCP_CLOSE_NORMAL);
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}
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}
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}
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}
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/*********************************************************************
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* @fn IAPCopyFlashDeal
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*
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* @brief Move the BACKUP area code to the USER area.
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* Write in 2KB units.
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*
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* @return upgrade status
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*/
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u8 IAPCopyFlashDeal(void)
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{
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u16 i,j;
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u32 *pBuf;
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u32 flashAddr;
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u32 updataBuff[READ_DATA_LEN / 4];
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pBuf = updataBuff;
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IAP_EEPROM_ERASE_44k(USER_IMAGE_START_ADD);
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for(i = 0; i < (BACKUP_IMAGE_MAX_SIZE / READ_DATA_LEN); i++)
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{
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flashAddr = USER_IMAGE_START_ADD + i * READ_DATA_LEN;
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IAP_EEPROM_READ((flashAddr + USER_IMAGE_MAX_SIZE), (u8 *)pBuf, READ_DATA_LEN);
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IAP_EEPROM_WRITE(flashAddr, (u8 *)pBuf, READ_DATA_LEN);
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//Check data
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for(j = 0; j < (READ_DATA_LEN / 4); j++){
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if(pBuf[j] != *(u32 *)(flashAddr + 4 * j))
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return NoREADY;
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}
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}
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IAP_EEPROM_ERASE_44k(BACKUP_IMAGE_START_ADD);
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return READY;
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}
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@@ -0,0 +1,83 @@
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/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : IAP_Task.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/05/25
|
||||
* Description : This file contains the headers of the IAP task.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __IAP_TASK_H__
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#define __IAP_TASK_H__
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#include "debug.h"
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#include "ch32v20x_it.h"
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/*
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flash:128K
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BIM area（Image Boot Manager）：40K
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USER area（用户代码区）：44K
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BACKUP area（代码备份区）：44K
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address assignment：
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0x0 size:0xA000
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0xA000 size:0xB000
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0x15000 size:0xB000
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*/
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/*address assignment */
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#define BIM_IMAGE_START_ADD ((uint32_t) 0x08000000)
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#define BIM_IMAGE_MAX_SIZE 0xA000
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#define USER_IMAGE_START_ADD ((uint32_t) 0x0800A000)
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#define USER_IMAGE_MAX_SIZE 0xB000
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#define BACKUP_IMAGE_START_ADD ((uint32_t) 0x08015000)
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#define BACKUP_IMAGE_MAX_SIZE 0xB000
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#define UPDATA_FLAG_STORAGE_ADD ((uint32_t) 0x0801FF00)
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#define FLASH_BLOCK_SIZE 4096
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#define READ_DATA_LEN 2048
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#define FLASH_PAGE_SIZE 256
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||||
/*Flash operation information*/
|
||||
#define BIN_INF_LEN 512
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#define FILE_FLAG "WCHNET"
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||||
#define IMAGE_FLAG_UPDATE 0x57434820 //'W','C','H',' '
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typedef struct
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{
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u8 iapFileFlag[8]; //8-byte IAP flag, fixed as "WCHNET", the extra space is 0
|
||||
u32 iapFileLen; //4 bytes IAP file length, which is bin file length + 512 bytes
|
||||
u32 iapFileCheckSum; //4-byte checksum
|
||||
}iapFileHeader;
|
||||
|
||||
typedef struct{
|
||||
u16 readIndex;
|
||||
u16 writeIndex;
|
||||
u16 buffUsedLen;
|
||||
u8 *dataBuff;
|
||||
}ethDataDeal;
|
||||
|
||||
extern ethDataDeal dataDeal;
|
||||
extern iapFileHeader iapPara;
|
||||
extern u32 fileDataLen;
|
||||
extern u32 fileCheckSum;
|
||||
|
||||
extern u8 IAPCopyFlashDeal(void);
|
||||
extern void IAPParaInit(void);
|
||||
extern void saveUpdatedFile(void);
|
||||
extern void receUpdatedFile(u8 socketid);
|
||||
extern void IAPFileParaCheck(u8 socketid);
|
||||
extern void IAP_EEPROM_ERASE_44k(u32 StartAddr);
|
||||
extern void IAP_EEPROM_READ( u32 StartAddr, u8 *Buffer, u32 Length );
|
||||
extern void IAP_EEPROM_ERASE(uint32_t Page_Address, u32 Length);
|
||||
extern void IAP_EEPROM_WRITE( u32 StartAddr, u8 *Buffer, u32 Length );
|
||||
|
||||
#endif /* __IAP_TASK_H__ */
|
||||
@@ -0,0 +1,41 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_it.h"
|
||||
#include <wchnet.h>
|
||||
#include "eth_driver.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void SW_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
/**/
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
printf("HardFault_Handler\r\n");
|
||||
printf("mcause:%08x\r\n",__get_MCAUSE());
|
||||
printf("mtval:%08x\r\n",__get_MTVAL());
|
||||
printf("mepc:%08x\r\n",__get_MEPC());
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETH_IRQHandler
|
||||
*
|
||||
* @brief This function handles ETH exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETH_IRQHandler(void)
|
||||
{
|
||||
WCHNET_ETHIsr();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn TIM2_IRQHandler
|
||||
*
|
||||
* @brief This function handles TIM2 exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TIM2_IRQHandler(void)
|
||||
{
|
||||
WCHNET_TimeIsr(WCHNETTIMERPERIOD);
|
||||
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SW_Handler
|
||||
*
|
||||
* @brief This function handles Software exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SW_Handler(void) {
|
||||
__asm("li a6, 0xA000");
|
||||
__asm("jr a6");
|
||||
|
||||
while(1);
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,279 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/01/18
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "string.h"
|
||||
#include "debug.h"
|
||||
#include "eth_driver.h"
|
||||
#include "IAP_Task.h"
|
||||
/*
|
||||
*@Note
|
||||
ETH IAP example, demonstrating the transmission of data via TCP, perform IAP.
|
||||
This example uses the software as the 1_Tool_Doc folder under "VerifyBinTool_WCHNET",
|
||||
The user manual is "WCHNET IAP Upgrade Solution Tutorial".
|
||||
|
||||
For details on the selection of engineering chips,
|
||||
please refer to the "CH32V20x Evaluation Board Manual" under the CH32V20xEVT\EVT\PUB folder.
|
||||
*/
|
||||
|
||||
u8 MACAddr[6]; //MAC address
|
||||
u8 IPAddr[4] = {192,168,1,10}; //IP address
|
||||
u8 GWIPAddr[4] = {192,168,1,1}; //Gateway IP address
|
||||
u8 IPMask[4] = {255,255,255,0}; //subnet mask
|
||||
u8 DESIP[4] = {192,168,1,100}; //destination IP address
|
||||
u16 desport = 1000; //destination port
|
||||
u16 srcport = 1000; //source port
|
||||
|
||||
u8 SocketId;
|
||||
u8 SocketRecvBuf[WCHNET_MAX_SOCKET_NUM][RECE_BUF_LEN]; //socket receive buffer
|
||||
u8 connFlag = 0; /* 0 disconnect 1 connect */
|
||||
|
||||
/*********************************************************************
|
||||
* @fn mStopIfError
|
||||
*
|
||||
* @brief check if error.
|
||||
*
|
||||
* @param iError - error constants.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void mStopIfError(u8 iError)
|
||||
{
|
||||
if (iError == WCHNET_ERR_SUCCESS)
|
||||
return;
|
||||
printf("Error: %02X\r\n", (u16)iError);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn TIM2_Init
|
||||
*
|
||||
* @brief Initializes TIM2.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TIM2_Init( void )
|
||||
{
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure={0};
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
|
||||
|
||||
TIM_TimeBaseStructure.TIM_Period = SystemCoreClock / 1000000 - 1;
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = WCHNETTIMERPERIOD * 1000 - 1;
|
||||
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
|
||||
TIM_ITConfig(TIM2, TIM_IT_Update ,ENABLE);
|
||||
|
||||
TIM_Cmd(TIM2, ENABLE);
|
||||
TIM_ClearITPendingBit(TIM2, TIM_IT_Update );
|
||||
NVIC_EnableIRQ(TIM2_IRQn);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_CreateTcpSocket
|
||||
*
|
||||
* @brief Create TCP Socket
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_CreateTcpSocket(void)
|
||||
{
|
||||
u8 i;
|
||||
SOCK_INF TmpSocketInf;
|
||||
|
||||
memset((void *)&TmpSocketInf,0,sizeof(SOCK_INF));
|
||||
memcpy((void *)TmpSocketInf.IPAddr,DESIP,4);
|
||||
TmpSocketInf.DesPort = desport;
|
||||
TmpSocketInf.SourPort = srcport;
|
||||
TmpSocketInf.ProtoType = PROTO_TYPE_TCP;
|
||||
TmpSocketInf.RecvBufLen = RECE_BUF_LEN;
|
||||
i = WCHNET_SocketCreat(&SocketId,&TmpSocketInf);
|
||||
printf("WCHNET_SocketCreat %d\r\n",SocketId);
|
||||
mStopIfError(i);
|
||||
i = WCHNET_SocketConnect(SocketId);
|
||||
mStopIfError(i);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_HandleSockInt
|
||||
*
|
||||
* @brief Socket Interrupt Handle
|
||||
*
|
||||
* @param socketid - socket id.
|
||||
* intstat - interrupt status
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_HandleSockInt(u8 socketid,u8 intstat)
|
||||
{
|
||||
if(intstat & SINT_STAT_RECV) //receive data
|
||||
{
|
||||
if (fileDataLen < BIN_INF_LEN) {
|
||||
IAPFileParaCheck(socketid);
|
||||
}
|
||||
else{
|
||||
receUpdatedFile(socketid);
|
||||
}
|
||||
}
|
||||
if(intstat & SINT_STAT_CONNECT) //connect successfully
|
||||
{
|
||||
WCHNET_ModifyRecvBuf(socketid, (u32)SocketRecvBuf[socketid], RECE_BUF_LEN);
|
||||
connFlag = 1;
|
||||
IAP_EEPROM_ERASE_44k(BACKUP_IMAGE_START_ADD);
|
||||
printf("TCP Connect Success\r\n");
|
||||
}
|
||||
if(intstat & SINT_STAT_DISCONNECT) //disconnect
|
||||
{
|
||||
connFlag = 0;
|
||||
IAPParaInit();
|
||||
printf("TCP Disconnect\r\n");
|
||||
}
|
||||
if(intstat & SINT_STAT_TIM_OUT) //timeout disconnect
|
||||
{
|
||||
printf("TCP Timeout\r\n");
|
||||
connFlag = 0;
|
||||
IAPParaInit();
|
||||
WCHNET_CreateTcpSocket();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_HandleGlobalInt
|
||||
*
|
||||
* @brief Global Interrupt Handle
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_HandleGlobalInt(void)
|
||||
{
|
||||
u8 intstat;
|
||||
u16 i;
|
||||
u8 socketint;
|
||||
|
||||
intstat = WCHNET_GetGlobalInt(); //get global interrupt flag
|
||||
if(intstat & GINT_STAT_UNREACH) //Unreachable interrupt
|
||||
{
|
||||
printf("GINT_STAT_UNREACH\r\n");
|
||||
}
|
||||
if(intstat & GINT_STAT_IP_CONFLI) //IP conflict
|
||||
{
|
||||
printf("GINT_STAT_IP_CONFLI\r\n");
|
||||
}
|
||||
if(intstat & GINT_STAT_PHY_CHANGE) //PHY status change
|
||||
{
|
||||
i = WCHNET_GetPHYStatus();
|
||||
if(i&PHY_Linked_Status)
|
||||
printf("PHY Link Success\r\n");
|
||||
}
|
||||
if(intstat & GINT_STAT_SOCKET) //socket related interrupt
|
||||
{
|
||||
for(i = 0; i < WCHNET_MAX_SOCKET_NUM; i++)
|
||||
{
|
||||
socketint = WCHNET_GetSocketInt(i);
|
||||
if(socketint)WCHNET_HandleSockInt(i,socketint);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIOInit
|
||||
*
|
||||
* @brief GPIO configuration
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIOInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
u8 i;
|
||||
u32 updateFlag;
|
||||
|
||||
Delay_Init();
|
||||
USART_Printf_Init(115200); //USART initialize
|
||||
GPIOInit();
|
||||
/*Detect whether the button(PA0) is pressed, if pressed,
|
||||
*make a TCP connection to upgrade, otherwise jump
|
||||
*to the application.*/
|
||||
if(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == 0){
|
||||
Delay_Ms(50);
|
||||
if(GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == 0){
|
||||
printf("IAP test\r\n");
|
||||
printf("SystemClk:%d\r\n",SystemCoreClock);
|
||||
printf("net version:%x\n",WCHNET_GetVer());
|
||||
if( WCHNET_LIB_VER != WCHNET_GetVer() ){
|
||||
printf("version error.\n");
|
||||
}
|
||||
WCHNET_GetMacAddr(MACAddr); //get the chip MAC address
|
||||
printf("mac addr:");
|
||||
for(i = 0; i < 6; i++)
|
||||
printf("%x ",MACAddr[i]);
|
||||
printf("\n");
|
||||
TIM2_Init();
|
||||
i = ETH_LibInit(IPAddr,GWIPAddr,IPMask,MACAddr); //Ethernet library initialize
|
||||
mStopIfError(i);
|
||||
if(i == WCHNET_ERR_SUCCESS) printf("WCHNET_LibInit Success\r\n");
|
||||
WCHNET_CreateTcpSocket(); //Create TCP Socket
|
||||
|
||||
while(1)
|
||||
{
|
||||
/*Ethernet library main task function,
|
||||
* which needs to be called cyclically*/
|
||||
WCHNET_MainTask();
|
||||
/*Query the Ethernet global interrupt,
|
||||
* if there is an interrupt, call the global interrupt handler*/
|
||||
if(WCHNET_QueryGlobalInt())
|
||||
{
|
||||
WCHNET_HandleGlobalInt();
|
||||
}
|
||||
if(connFlag){
|
||||
saveUpdatedFile();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
IAP_EEPROM_READ(UPDATA_FLAG_STORAGE_ADD,(u8 *)&updateFlag,4);
|
||||
if(updateFlag == IMAGE_FLAG_UPDATE){
|
||||
printf("start IAP program!\r\n");
|
||||
if(IAPCopyFlashDeal() == READY){
|
||||
printf("update success!\r\n");
|
||||
printf("Run APP!\r\n");
|
||||
NVIC_EnableIRQ(Software_IRQn);
|
||||
NVIC_SetPendingIRQ(Software_IRQn);
|
||||
}
|
||||
else{
|
||||
printf("update error!\r\n");
|
||||
while(1);
|
||||
}
|
||||
}
|
||||
else{
|
||||
printf("Run APP!\r\n");
|
||||
NVIC_EnableIRQ(Software_IRQn);
|
||||
NVIC_SetPendingIRQ(Software_IRQn);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,144 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : net_config.h
|
||||
* Author : WCH
|
||||
* Version : V1.30
|
||||
* Date : 2022/06/02
|
||||
* Description : This file contains the configurations of
|
||||
* Ethernet protocol stack library
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __NET_CONFIG_H__
|
||||
#define __NET_CONFIG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* socket configuration, IPRAW + UDP + TCP + TCP_LISTEN = number of sockets
|
||||
*/
|
||||
#define WCHNET_NUM_IPRAW 0 /* Number of IPRAW connections */
|
||||
|
||||
#define WCHNET_NUM_UDP 0 /* The number of UDP connections */
|
||||
|
||||
#define WCHNET_NUM_TCP 1 /* Number of TCP connections */
|
||||
|
||||
#define WCHNET_NUM_TCP_LISTEN 0 /* Number of TCP listening */
|
||||
|
||||
/* The number of sockets, the maximum is 31 */
|
||||
#define WCHNET_MAX_SOCKET_NUM (WCHNET_NUM_IPRAW+WCHNET_NUM_UDP+WCHNET_NUM_TCP+WCHNET_NUM_TCP_LISTEN)
|
||||
|
||||
#define WCHNET_TCP_MSS 1460 /* Size of TCP MSS*/
|
||||
|
||||
/*********************************************************************
|
||||
* MAC queue configuration
|
||||
*/
|
||||
#define ETH_TXBUFNB 1 /* The number of descriptors sent by the MAC */
|
||||
|
||||
#define ETH_RXBUFNB 4 /* Number of MAC received descriptors */
|
||||
|
||||
#ifndef ETH_MAX_PACKET_SIZE
|
||||
#define ETH_RX_BUF_SZE 1520 /* MAC receive buffer length, an integer multiple of 4 */
|
||||
#define ETH_TX_BUF_SZE 1520 /* MAC send buffer length, an integer multiple of 4 */
|
||||
#else
|
||||
#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* Functional configuration
|
||||
*/
|
||||
#define WCHNET_PING_ENABLE 1 /* PING is enabled, PING is enabled by default */
|
||||
|
||||
#define TCP_RETRY_COUNT 20 /* The number of TCP retransmissions, the default value is 20 */
|
||||
|
||||
#define TCP_RETRY_PERIOD 10 /* TCP retransmission period, the default value is 10, the unit is 50ms */
|
||||
|
||||
#define SOCKET_SEND_RETRY 1 /* Send failed retry configuration, 1: enable, 0: disable */
|
||||
|
||||
#define CFG0_TCP_SEND_COPY 1 /* TCP send buffer copy, 1: copy, 0: not copy */
|
||||
|
||||
#define CFG0_TCP_RECV_COPY 1 /* TCP receive replication optimization, internal debugging use */
|
||||
|
||||
#define CFG0_TCP_OLD_DELETE 0 /* Delete oldest TCP connection, 1: enable, 0: disable */
|
||||
|
||||
/*********************************************************************
|
||||
* Memory related configuration
|
||||
*/
|
||||
/*If a single socket cannot reach full speed,
|
||||
* try to increase RECE_BUF_LEN to (WCHNET_TCP_MSS*4)
|
||||
* and increase WCHNET_NUM_TCP_SEG to (WCHNET_NUM_TCP*4)*/
|
||||
#define RECE_BUF_LEN (WCHNET_TCP_MSS*2) /* socket receive buffer size */
|
||||
|
||||
#define WCHNET_NUM_PBUF (WCHNET_MAX_SOCKET_NUM+WCHNET_NUM_TCP) /* Number of PBUF structures */
|
||||
|
||||
#define WCHNET_NUM_TCP_SEG (WCHNET_NUM_TCP*2) /* The number of TCP segments used to send */
|
||||
|
||||
#define WCHNET_MEM_HEAP_SIZE (((WCHNET_TCP_MSS+0x10+54)*WCHNET_NUM_TCP_SEG)+ETH_TX_BUF_SZE+64) /* memory heap size */
|
||||
|
||||
#define WCHNET_NUM_ARP_TABLE 50 /* Number of ARP lists */
|
||||
|
||||
#define WCHNET_NUM_IP_REASSDATA 4 /* Number of IP segments */
|
||||
|
||||
#define CFG0_IP_REASS_PBUFS 4 /* Number of reassembled IP PBUFs */
|
||||
|
||||
#define WCHNET_MEM_ALIGNMENT 4 /* 4 byte alignment */
|
||||
|
||||
#define WCHNET_NUM_POOL_BUF (WCHNET_NUM_TCP*2+2) /* The number of POOL BUFs, the number of receive queues */
|
||||
|
||||
/* Check the configuration of the SOCKET quantity */
|
||||
#if( WCHNET_NUM_TCP_LISTEN && !WCHNET_NUM_TCP )
|
||||
#error "WCHNET_NUM_TCP Error)"
|
||||
#endif
|
||||
/* Check byte alignment must be a multiple of 4 */
|
||||
#if((WCHNET_MEM_ALIGNMENT % 4) || (WCHNET_MEM_ALIGNMENT == 0))
|
||||
#error "WCHNET_MEM_ALIGNMENT Error,Please Config WCHNET_MEM_ALIGNMENT = 4 * N, N >=1"
|
||||
#endif
|
||||
/* TCP maximum segment length */
|
||||
#if((WCHNET_TCP_MSS > 1460) || (WCHNET_TCP_MSS < 60))
|
||||
#error "WCHNET_TCP_MSS Error,Please Config WCHNET_TCP_MSS >= 60 && WCHNET_TCP_MSS <= 1460"
|
||||
#endif
|
||||
/* Number of ARP cache tables */
|
||||
#if((WCHNET_NUM_ARP_TABLE > 0X7F) || (WCHNET_NUM_ARP_TABLE < 1))
|
||||
#error "WCHNET_NUM_ARP_TABLE Error,Please Config WCHNET_NUM_ARP_TABLE >= 1 && WCHNET_NUM_ARP_TABLE <= 0X7F"
|
||||
#endif
|
||||
/* Check POOL BUF configuration */
|
||||
#if(WCHNET_NUM_POOL_BUF < 1)
|
||||
#error "WCHNET_NUM_POOL_BUF Error,Please Config WCHNET_NUM_POOL_BUF >= 1"
|
||||
#endif
|
||||
/* Check PBUF structure configuration */
|
||||
#if(WCHNET_NUM_PBUF < 1)
|
||||
#error "WCHNET_NUM_PBUF Error,Please Config WCHNET_NUM_PBUF >= 1"
|
||||
#endif
|
||||
/* Check IP Assignment Configuration */
|
||||
#if((WCHNET_NUM_IP_REASSDATA > 10) || (WCHNET_NUM_IP_REASSDATA < 1))
|
||||
#error "WCHNET_NUM_IP_REASSDATA Error,Please Config WCHNET_NUM_IP_REASSDATA < 10 && WCHNET_NUM_IP_REASSDATA >= 1 "
|
||||
#endif
|
||||
/* Check the number of reassembled IP PBUFs */
|
||||
#if(WCHNET_IP_REASS_PBUFS > WCHNET_NUM_POOL_BUF)
|
||||
#error "WCHNET_IP_REASS_PBUFS Error,Please Config WCHNET_IP_REASS_PBUFS < WCHNET_NUM_POOL_BUF"
|
||||
#endif
|
||||
|
||||
#if(WCHNETTIMERPERIOD > 50)
|
||||
#error "WCHNETTIMERPERIOD Error,Please Config WCHNETTIMERPERIOD < 50"
|
||||
#endif
|
||||
|
||||
/* Configuration value 0 */
|
||||
#define WCHNET_MISC_CONFIG0 (((CFG0_TCP_SEND_COPY) << 0) |\
|
||||
((CFG0_TCP_RECV_COPY) << 1) |\
|
||||
((CFG0_TCP_OLD_DELETE) << 2) |\
|
||||
((CFG0_IP_REASS_PBUFS) << 3) )
|
||||
/* Configuration value 1 */
|
||||
#define WCHNET_MISC_CONFIG1 (((WCHNET_MAX_SOCKET_NUM)<<0)|\
|
||||
((WCHNET_PING_ENABLE) << 13) |\
|
||||
((TCP_RETRY_COUNT) << 14) |\
|
||||
((TCP_RETRY_PERIOD) << 19) |\
|
||||
((SOCKET_SEND_RETRY) << 25) )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,990 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user