first submission
This commit is contained in:
qiyongshuang
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/********************************** (C) COPYRIGHT *******************************
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* File Name : bsp_uart.c
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* Author : WCH
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* Version : V1.0
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* Date : 2022/05/10
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* Description : uart cfg.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "bsp_uart.h"
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/* Global Variable */
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struct uart_data uart_data_t;
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/* UART2 */
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u8 UART2_RX_DMA_DataBuf[UART_RX_DMA_SIZE]= {0};
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u8 UART2_TX_DMA_DataBuf[UART_TX_BUF_NUM][ETH_RECEIVE_SIZE] = {0};
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u16 UART2_TX_Buf_Length[UART_TX_BUF_NUM] = {0};
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/**********************************************************************
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* @fn UART_GPIO_Init
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*
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* @brief initialize uart2 GPIO
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*
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* @return none
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* */
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void UART_GPIO_Init(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure={0};
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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/* UART2 TX-->PA2 RX-->PA3 */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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}
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/**********************************************************************
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* @fn UART_DMA_Init
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*
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* @brief initialize uart2 DMA
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*
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* @return none
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* */
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void UART_DMA_Init(void)
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{
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DMA_InitTypeDef DMA_InitStructure = {0};
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
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/* UART2 TX-->DMA1_Channel7 RX-->DMA1_Channel6 */
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DMA_DeInit(DMA1_Channel7);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&USART2->DATAR);
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)uart_data_t.TX_buffer;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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//DMA_InitStructure.DMA_BufferSize = size(TX_DMA_dataBuf);
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel7, &DMA_InitStructure);
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DMA_DeInit(DMA1_Channel6);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&USART2->DATAR);
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DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)uart_data_t.RX_buffer;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = (uint32_t)UART_RX_DMA_SIZE;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_Init(DMA1_Channel6, &DMA_InitStructure);
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DMA_ClearFlag(DMA1_IT_TC7);
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DMA_Cmd(DMA1_Channel6, ENABLE);
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USART_DMACmd(USART2,USART_DMAReq_Rx|USART_DMAReq_Tx,ENABLE);
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}
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/**********************************************************************
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* @fn UART_Interrupt_Init
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*
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* @brief initialize uart2 interrupt
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*
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* @return none
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* */
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void UART_Interrupt_Init(void)
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{
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NVIC_InitTypeDef NVIC_InitStructure = {0};
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/* UART2 TX-->DMA1_Channel7 RX-->DMA1_Channel6 */
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DMA_ITConfig(DMA1_Channel7,DMA_IT_TC,ENABLE);
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NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel7_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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/**********************************************************************
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* @fn BSP_Uart_Init
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*
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* @brief initialize uart2
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*
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* @return none
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* */
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void BSP_Uart_Init(void)
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{
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USART_InitTypeDef USART_InitStructure = {0};
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UART_GPIO_Init();
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/* USART2 TX-->PA2 RX-->PA3 */
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uart_data_t.RX_buffer = UART2_RX_DMA_DataBuf;
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uart_data_t.TX_buffer = &UART2_TX_DMA_DataBuf[0];
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uart_data_t.TX_data_length = UART2_TX_Buf_Length;
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uart_data_t.rx_read = 0;
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uart_data_t.rx_write = 0;
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uart_data_t.last_RX_DMA_length = UART_RX_DMA_SIZE;
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uart_data_t.RX_data_length = 0;
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uart_data_t.tx_read = 0;
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uart_data_t.tx_write = 0;
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uart_data_t.tx_remainBuffNum = UART_TX_BUF_NUM;
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uart_data_t.uart_tx_dma_state = IDLE;
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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USART_InitStructure.USART_BaudRate = BAUD_RATE;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
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USART_Init(USART2, &USART_InitStructure);
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USART_Cmd(USART2, ENABLE);
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UART_DMA_Init();
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UART_Interrupt_Init();
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}
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@@ -0,0 +1,53 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : bsp_uart.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2022/05/10
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* Description : uart cfg.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef _BSP_UART_H_
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#define _BSP_UART_H_
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#include "ch32v20x.h"
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#include "net_config.h"
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/* Global define */
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#define BAUD_RATE 1000000
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#define size(a) (sizeof(a) / sizeof(*(a)))
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#define MIN(X,Y) ((X) < (Y) ? (X) : (Y))
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#define UART_RX_DMA_SIZE 2048 //Must be a power of 2 ( a%2^n = a&(2^n - 1) )
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#define ETH_RECEIVE_SIZE RECE_BUF_LEN
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#define UART_TX_BUF_NUM 3
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typedef enum { IDLE = 0, BUSY = !IDLE} Uart_TX_DMA_State;
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struct uart_data
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{
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uint8_t (*TX_buffer)[ETH_RECEIVE_SIZE]; /* receive from eth */
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uint8_t *RX_buffer; /* receive from uart */
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uint16_t *TX_data_length;
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uint16_t RX_data_length;
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uint16_t last_RX_DMA_length;
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uint32_t rx_read;
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uint32_t rx_write;
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uint8_t tx_read;
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uint8_t tx_write;
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uint8_t tx_remainBuffNum;
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Uart_TX_DMA_State uart_tx_dma_state; /* 0 -> idle, 1 -> busy */
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};
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extern struct uart_data uart_data_t;
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extern void BSP_Uart_Init(void);
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#endif /* end of bsp_uart.h */
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@@ -0,0 +1,41 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v20x_conf.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : Library configuration file.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef __CH32V20x_CONF_H
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#define __CH32V20x_CONF_H
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#include "ch32v20x_adc.h"
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#include "ch32v20x_bkp.h"
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#include "ch32v20x_can.h"
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#include "ch32v20x_crc.h"
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#include "ch32v20x_dbgmcu.h"
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#include "ch32v20x_dma.h"
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#include "ch32v20x_exti.h"
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#include "ch32v20x_flash.h"
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#include "ch32v20x_gpio.h"
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#include "ch32v20x_i2c.h"
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#include "ch32v20x_iwdg.h"
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#include "ch32v20x_pwr.h"
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#include "ch32v20x_rcc.h"
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#include "ch32v20x_rtc.h"
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#include "ch32v20x_spi.h"
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#include "ch32v20x_tim.h"
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#include "ch32v20x_usart.h"
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#include "ch32v20x_wwdg.h"
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#include "ch32v20x_it.h"
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#include "ch32v20x_misc.h"
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#endif /* __CH32V20x_CONF_H */
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@@ -0,0 +1,94 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v20x_it.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : Main Interrupt Service Routines.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v20x_it.h"
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#include <wchnet.h>
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#include "eth_driver.h"
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#include "bsp_uart.h"
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void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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/*********************************************************************
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* @fn NMI_Handler
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*
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* @brief This function handles NMI exception.
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*
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* @return none
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*/
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void NMI_Handler(void)
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{
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/**/
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}
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/*********************************************************************
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* @fn HardFault_Handler
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*
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* @brief This function handles Hard Fault exception.
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*
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* @return none
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*/
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void HardFault_Handler(void)
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{
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printf("HardFault_Handler\r\n");
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printf("mcause:%08x\r\n",__get_MCAUSE());
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printf("mtval:%08x\r\n",__get_MTVAL());
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printf("mepc:%08x\r\n",__get_MEPC());
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while (1);
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}
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/*********************************************************************
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* @fn ETH_IRQHandler
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*
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* @brief This function handles ETH exception.
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*
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* @return none
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*/
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void ETH_IRQHandler(void)
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{
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WCHNET_ETHIsr();
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}
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/*********************************************************************
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* @fn TIM2_IRQHandler
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*
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* @brief This function handles TIM2 exception.
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*
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* @return none
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*/
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void TIM2_IRQHandler(void)
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{
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WCHNET_TimeIsr(WCHNETTIMERPERIOD);
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TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
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}
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/*********************************************************************
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* @fn DMA1_Channel7_IRQHandler
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*
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* @brief uart2 DMA Tx completion interrupt.
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*
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* @return none
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*/
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void DMA1_Channel7_IRQHandler(void)
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{
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if(DMA_GetITStatus(DMA1_IT_TC7))
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{
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DMA_Cmd(DMA1_Channel7,DISABLE);
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uart_data_t.uart_tx_dma_state = IDLE;
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uart_data_t.tx_read++;
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uart_data_t.tx_remainBuffNum++;
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DMA_ClearITPendingBit(DMA1_IT_TC7);
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}
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}
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@@ -0,0 +1,19 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v20x_it.h
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* Author : WCH
|
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* Version : V1.0.0
|
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* Date : 2021/06/06
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* Description : This file contains the headers of the interrupt handlers.
|
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*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
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#ifndef __CH32V20x_IT_H
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#define __CH32V20x_IT_H
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#include "debug.h"
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#endif /* __CH32V20x_IT_H */
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@@ -0,0 +1,351 @@
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/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/05/10
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
/*
|
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*@Note
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||||
ETH_UART example demonstrates data transparency between Ethernet and UART.
|
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By default, 1000000 baud rate (can be changed in bsp_uart.h) is used for serial port data transmission.
|
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For details on the selection of engineering chips,
|
||||
please refer to the "CH32V20x Evaluation Board Manual" under the CH32V20xEVT\EVT\PUB folder.
|
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*/
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#include "string.h"
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#include "debug.h"
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#include "eth_driver.h"
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#include "bsp_uart.h"
|
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|
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u8 MACAddr[6]; //MAC address
|
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u8 IPAddr[4] = {192,168,1,10}; //IP address
|
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u8 GWIPAddr[4] = {192,168,1,1}; //Gateway IP address
|
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u8 IPMask[4] = {255,255,255,0}; //subnet mask
|
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u8 DESIP[4] = {192,168,1,100}; //destination IP address
|
||||
|
||||
u8 SocketId; //socket id
|
||||
u8 SocketRecvBuf[RECE_BUF_LEN]; //socket data buff
|
||||
u16 desport = 1000; //destination port
|
||||
u16 srcport = 1000; //source port
|
||||
|
||||
u8 TCPConnValid = 0; //0 disconnected 1 connect
|
||||
|
||||
/*********************************************************************
|
||||
* @fn mStopIfError
|
||||
*
|
||||
* @brief check if error.
|
||||
*
|
||||
* @param iError - error constants.
|
||||
*
|
||||
* @return none
|
||||
*/
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||||
void mStopIfError(u8 iError)
|
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{
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||||
if (iError == WCHNET_ERR_SUCCESS) return;
|
||||
printf("Error: %02X\r\n", (u16)iError);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn TIM2_Init
|
||||
*
|
||||
* @brief Initializes TIM2.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TIM2_Init( void )
|
||||
{
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure={0};
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
|
||||
|
||||
TIM_TimeBaseStructure.TIM_Period = SystemCoreClock / 1000000 - 1;
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = WCHNETTIMERPERIOD * 1000 - 1;
|
||||
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
|
||||
TIM_ITConfig(TIM2, TIM_IT_Update ,ENABLE);
|
||||
|
||||
TIM_Cmd(TIM2, ENABLE);
|
||||
TIM_ClearITPendingBit(TIM2, TIM_IT_Update );
|
||||
NVIC_EnableIRQ(TIM2_IRQn);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_CreateTcpSocket
|
||||
*
|
||||
* @brief Create TCP Socket
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_CreateTcpSocket(void)
|
||||
{
|
||||
u8 i;
|
||||
SOCK_INF TmpSocketInf;
|
||||
|
||||
memset((void *)&TmpSocketInf,0,sizeof(SOCK_INF));
|
||||
memcpy((void *)TmpSocketInf.IPAddr,DESIP,4);
|
||||
TmpSocketInf.DesPort = desport;
|
||||
TmpSocketInf.SourPort = srcport;
|
||||
TmpSocketInf.ProtoType = PROTO_TYPE_TCP;
|
||||
TmpSocketInf.RecvBufLen = RECE_BUF_LEN;
|
||||
i = WCHNET_SocketCreat(&SocketId,&TmpSocketInf);
|
||||
printf("WCHNET_SocketCreat %d\r\n",SocketId);
|
||||
mStopIfError(i);
|
||||
i = WCHNET_SocketConnect(SocketId);
|
||||
mStopIfError(i);
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn uartRxAndSendDataToETH
|
||||
*
|
||||
* @brief uart receive data, and send these data to eth
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void uartRxAndSendDataToETH(void)
|
||||
{
|
||||
int ret = -1;
|
||||
uint32_t temp = 0;
|
||||
uint32_t len = 0;
|
||||
uint32_t len_1 = 0;
|
||||
|
||||
temp = DMA1_Channel6->CNTR;
|
||||
|
||||
/* uart rx dma CNTR not equal to last, indicating that data is received*/
|
||||
if(temp != uart_data_t.last_RX_DMA_length)
|
||||
{
|
||||
/* calculate the length of the received data */
|
||||
uart_data_t.rx_write += (uart_data_t.last_RX_DMA_length - temp) & (UART_RX_DMA_SIZE - 1);
|
||||
|
||||
/* update last rx dma CNTR */
|
||||
uart_data_t.last_RX_DMA_length = temp;
|
||||
|
||||
/*calculate the length of the RX_buffer */
|
||||
len = uart_data_t.rx_write - uart_data_t.rx_read;
|
||||
|
||||
/* RX_buffer is full */
|
||||
if(len > UART_RX_DMA_SIZE)
|
||||
{
|
||||
printf("uart2 RX DMA Buff is full!\r\n");
|
||||
len = 0;
|
||||
uart_data_t.rx_read = 0;
|
||||
uart_data_t.rx_write = 0;
|
||||
uart_data_t.last_RX_DMA_length = 0;
|
||||
}
|
||||
|
||||
/* send data starting from rx_read to RX_buffer end */
|
||||
len_1 = MIN(len,UART_RX_DMA_SIZE-(uart_data_t.rx_read&(UART_RX_DMA_SIZE-1)));
|
||||
|
||||
if(len_1 != 0)
|
||||
{
|
||||
ret = WCHNET_SocketSend(SocketId, &uart_data_t.RX_buffer[uart_data_t.rx_read&(UART_RX_DMA_SIZE-1)], &len_1);
|
||||
if (ret == 0)
|
||||
{
|
||||
uart_data_t.rx_read += len_1;
|
||||
}
|
||||
}
|
||||
|
||||
/* send the rest of the data(if any) at beginning of RX_buffer */
|
||||
if( (len-len_1) != 0)
|
||||
{
|
||||
len_1 = len-len_1;
|
||||
ret = WCHNET_SocketSend(SocketId, &uart_data_t.RX_buffer[0], &len_1);
|
||||
if (ret == 0)
|
||||
{
|
||||
uart_data_t.rx_read += len_1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn uartTx
|
||||
*
|
||||
* @brief send data from TX_buffer by uart tx dma
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void uartTx(void)
|
||||
{
|
||||
uint16_t read_buf = 0;
|
||||
|
||||
if(uart_data_t.uart_tx_dma_state == IDLE)
|
||||
{
|
||||
/* eth has received data */
|
||||
if(uart_data_t.tx_remainBuffNum < UART_TX_BUF_NUM)
|
||||
{
|
||||
read_buf = (uart_data_t.tx_read)%UART_TX_BUF_NUM;
|
||||
DMA1_Channel7->MADDR = (uint32_t) &uart_data_t.TX_buffer[read_buf];
|
||||
DMA1_Channel7->CNTR = uart_data_t.TX_data_length[read_buf];
|
||||
uart_data_t.uart_tx_dma_state = BUSY;
|
||||
DMA_Cmd(DMA1_Channel7,ENABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ETHRx
|
||||
*
|
||||
* @brief ETH receive data and save it to buff.
|
||||
*
|
||||
* @param socketid - socket id.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ETHRx(u8 socketid)
|
||||
{
|
||||
u32 len;
|
||||
uint8_t write_buf = 0;
|
||||
int8_t receive_state = -1;
|
||||
|
||||
len = WCHNET_SocketRecvLen(socketid, NULL); /* query length */
|
||||
|
||||
if( uart_data_t.tx_remainBuffNum > 0)
|
||||
{
|
||||
write_buf = (uart_data_t.tx_write)%UART_TX_BUF_NUM;
|
||||
/* socket receive */
|
||||
receive_state = WCHNET_SocketRecv(socketid, uart_data_t.TX_buffer[write_buf], &len);
|
||||
if(receive_state == WCHNET_ERR_SUCCESS)
|
||||
{
|
||||
uart_data_t.TX_data_length[write_buf] = len;
|
||||
|
||||
uart_data_t.tx_write++;
|
||||
|
||||
uart_data_t.tx_remainBuffNum--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("eth receive buff busy\n");
|
||||
}
|
||||
uartTx();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_HandleSockInt
|
||||
*
|
||||
* @brief Socket Interrupt Handle
|
||||
*
|
||||
* @param socketid - socket id.
|
||||
* intstat - interrupt status
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_HandleSockInt(u8 socketid,u8 intstat)
|
||||
{
|
||||
if(intstat & SINT_STAT_RECV) //receive data
|
||||
{
|
||||
ETHRx(socketid);
|
||||
}
|
||||
if(intstat & SINT_STAT_CONNECT) //connect successfully
|
||||
{
|
||||
TCPConnValid = 1;
|
||||
WCHNET_ModifyRecvBuf(socketid, (u32)SocketRecvBuf, RECE_BUF_LEN);
|
||||
printf("TCP Connect Success\r\n");
|
||||
}
|
||||
if(intstat & SINT_STAT_DISCONNECT) //disconnect
|
||||
{
|
||||
TCPConnValid = 0;
|
||||
printf("TCP Disconnect\r\n");
|
||||
}
|
||||
if(intstat & SINT_STAT_TIM_OUT) //timeout disconnect
|
||||
{
|
||||
TCPConnValid = 0;
|
||||
printf("TCP Timeout\r\n");
|
||||
WCHNET_CreateTcpSocket();
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WCHNET_HandleGlobalInt
|
||||
*
|
||||
* @brief Global Interrupt Handle
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WCHNET_HandleGlobalInt(void)
|
||||
{
|
||||
u8 intstat;
|
||||
u8 socketint;
|
||||
u16 i;
|
||||
|
||||
intstat = WCHNET_GetGlobalInt(); //get global interrupt flag
|
||||
if(intstat & GINT_STAT_UNREACH) //Unreachable interrupt
|
||||
{
|
||||
printf("GINT_STAT_UNREACH\r\n");
|
||||
}
|
||||
if(intstat & GINT_STAT_IP_CONFLI) //IP conflict
|
||||
{
|
||||
printf("GINT_STAT_IP_CONFLI\r\n");
|
||||
}
|
||||
if(intstat & GINT_STAT_PHY_CHANGE) //PHY status change
|
||||
{
|
||||
i = WCHNET_GetPHYStatus(); //socket related interrupt
|
||||
if(i&PHY_Linked_Status)
|
||||
printf("PHY Link Success\r\n");
|
||||
}
|
||||
if(intstat & GINT_STAT_SOCKET)
|
||||
{
|
||||
for(i = 0; i < WCHNET_MAX_SOCKET_NUM; i ++)
|
||||
{
|
||||
socketint = WCHNET_GetSocketInt(i);
|
||||
if(socketint)WCHNET_HandleSockInt(i,socketint);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
u8 i;
|
||||
|
||||
Delay_Init();
|
||||
USART_Printf_Init(115200); //USART initialize
|
||||
printf("ETH_UART\r\n");
|
||||
printf("SystemClk:%d\r\n",SystemCoreClock);
|
||||
printf("net version:%x\n",WCHNET_GetVer());
|
||||
if( WCHNET_LIB_VER != WCHNET_GetVer() ){
|
||||
printf("version error.\n");
|
||||
}
|
||||
WCHNET_GetMacAddr(MACAddr); //get the chip MAC address
|
||||
printf("mac addr:");
|
||||
for(i = 0; i < 6; i++)
|
||||
printf("%x ",MACAddr[i]);
|
||||
printf("\n");
|
||||
TIM2_Init();
|
||||
BSP_Uart_Init(); //USART2 initialize
|
||||
i = ETH_LibInit(IPAddr,GWIPAddr,IPMask,MACAddr); //Ethernet library initialize
|
||||
mStopIfError(i);
|
||||
if(i == WCHNET_ERR_SUCCESS) printf("WCHNET_LibInit Success\r\n");
|
||||
|
||||
WCHNET_CreateTcpSocket(); //Create TCP Socket
|
||||
|
||||
while(1)
|
||||
{
|
||||
/*Ethernet library main task function,
|
||||
* which needs to be called cyclically*/
|
||||
WCHNET_MainTask();
|
||||
/*Query the Ethernet global interrupt,
|
||||
* if there is an interrupt, call the global interrupt handler*/
|
||||
if(WCHNET_QueryGlobalInt())
|
||||
{
|
||||
WCHNET_HandleGlobalInt();
|
||||
}
|
||||
if(TCPConnValid){
|
||||
uartTx();
|
||||
uartRxAndSendDataToETH();
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,144 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : net_config.h
|
||||
* Author : WCH
|
||||
* Version : V1.30
|
||||
* Date : 2022/06/02
|
||||
* Description : This file contains the configurations of
|
||||
* Ethernet protocol stack library
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __NET_CONFIG_H__
|
||||
#define __NET_CONFIG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* socket configuration, IPRAW + UDP + TCP + TCP_LISTEN = number of sockets
|
||||
*/
|
||||
#define WCHNET_NUM_IPRAW 0 /* Number of IPRAW connections */
|
||||
|
||||
#define WCHNET_NUM_UDP 0 /* The number of UDP connections */
|
||||
|
||||
#define WCHNET_NUM_TCP 1 /* Number of TCP connections */
|
||||
|
||||
#define WCHNET_NUM_TCP_LISTEN 0 /* Number of TCP listening */
|
||||
|
||||
/* The number of sockets, the maximum is 31 */
|
||||
#define WCHNET_MAX_SOCKET_NUM (WCHNET_NUM_IPRAW+WCHNET_NUM_UDP+WCHNET_NUM_TCP+WCHNET_NUM_TCP_LISTEN)
|
||||
|
||||
#define WCHNET_TCP_MSS 1460 /* Size of TCP MSS*/
|
||||
|
||||
/*********************************************************************
|
||||
* MAC queue configuration
|
||||
*/
|
||||
#define ETH_TXBUFNB 1 /* The number of descriptors sent by the MAC */
|
||||
|
||||
#define ETH_RXBUFNB 4 /* Number of MAC received descriptors */
|
||||
|
||||
#ifndef ETH_MAX_PACKET_SIZE
|
||||
#define ETH_RX_BUF_SZE 1520 /* MAC receive buffer length, an integer multiple of 4 */
|
||||
#define ETH_TX_BUF_SZE 1520 /* MAC send buffer length, an integer multiple of 4 */
|
||||
#else
|
||||
#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||
#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* Functional configuration
|
||||
*/
|
||||
#define WCHNET_PING_ENABLE 1 /* PING is enabled, PING is enabled by default */
|
||||
|
||||
#define TCP_RETRY_COUNT 20 /* The number of TCP retransmissions, the default value is 20 */
|
||||
|
||||
#define TCP_RETRY_PERIOD 10 /* TCP retransmission period, the default value is 10, the unit is 50ms */
|
||||
|
||||
#define SOCKET_SEND_RETRY 1 /* Send failed retry configuration, 1: enable, 0: disable */
|
||||
|
||||
#define CFG0_TCP_SEND_COPY 1 /* TCP send buffer copy, 1: copy, 0: not copy */
|
||||
|
||||
#define CFG0_TCP_RECV_COPY 1 /* TCP receive replication optimization, internal debugging use */
|
||||
|
||||
#define CFG0_TCP_OLD_DELETE 0 /* Delete oldest TCP connection, 1: enable, 0: disable */
|
||||
|
||||
/*********************************************************************
|
||||
* Memory related configuration
|
||||
*/
|
||||
/*If a single socket cannot reach full speed,
|
||||
* try to increase RECE_BUF_LEN to (WCHNET_TCP_MSS*4)
|
||||
* and increase WCHNET_NUM_TCP_SEG to (WCHNET_NUM_TCP*4)*/
|
||||
#define RECE_BUF_LEN (WCHNET_TCP_MSS*2) /* socket receive buffer size */
|
||||
|
||||
#define WCHNET_NUM_PBUF (WCHNET_MAX_SOCKET_NUM+WCHNET_NUM_TCP) /* Number of PBUF structures */
|
||||
|
||||
#define WCHNET_NUM_TCP_SEG (WCHNET_NUM_TCP*2) /* The number of TCP segments used to send */
|
||||
|
||||
#define WCHNET_MEM_HEAP_SIZE (((WCHNET_TCP_MSS+0x10+54)*WCHNET_NUM_TCP_SEG)+ETH_TX_BUF_SZE+64) /* memory heap size */
|
||||
|
||||
#define WCHNET_NUM_ARP_TABLE 50 /* Number of ARP lists */
|
||||
|
||||
#define WCHNET_NUM_IP_REASSDATA 4 /* Number of IP segments */
|
||||
|
||||
#define CFG0_IP_REASS_PBUFS 4 /* Number of reassembled IP PBUFs */
|
||||
|
||||
#define WCHNET_MEM_ALIGNMENT 4 /* 4 byte alignment */
|
||||
|
||||
#define WCHNET_NUM_POOL_BUF (WCHNET_NUM_TCP*2+2) /* The number of POOL BUFs, the number of receive queues */
|
||||
|
||||
/* Check the configuration of the SOCKET quantity */
|
||||
#if( WCHNET_NUM_TCP_LISTEN && !WCHNET_NUM_TCP )
|
||||
#error "WCHNET_NUM_TCP Error)"
|
||||
#endif
|
||||
/* Check byte alignment must be a multiple of 4 */
|
||||
#if((WCHNET_MEM_ALIGNMENT % 4) || (WCHNET_MEM_ALIGNMENT == 0))
|
||||
#error "WCHNET_MEM_ALIGNMENT Error,Please Config WCHNET_MEM_ALIGNMENT = 4 * N, N >=1"
|
||||
#endif
|
||||
/* TCP maximum segment length */
|
||||
#if((WCHNET_TCP_MSS > 1460) || (WCHNET_TCP_MSS < 60))
|
||||
#error "WCHNET_TCP_MSS Error,Please Config WCHNET_TCP_MSS >= 60 && WCHNET_TCP_MSS <= 1460"
|
||||
#endif
|
||||
/* Number of ARP cache tables */
|
||||
#if((WCHNET_NUM_ARP_TABLE > 0X7F) || (WCHNET_NUM_ARP_TABLE < 1))
|
||||
#error "WCHNET_NUM_ARP_TABLE Error,Please Config WCHNET_NUM_ARP_TABLE >= 1 && WCHNET_NUM_ARP_TABLE <= 0X7F"
|
||||
#endif
|
||||
/* Check POOL BUF configuration */
|
||||
#if(WCHNET_NUM_POOL_BUF < 1)
|
||||
#error "WCHNET_NUM_POOL_BUF Error,Please Config WCHNET_NUM_POOL_BUF >= 1"
|
||||
#endif
|
||||
/* Check PBUF structure configuration */
|
||||
#if(WCHNET_NUM_PBUF < 1)
|
||||
#error "WCHNET_NUM_PBUF Error,Please Config WCHNET_NUM_PBUF >= 1"
|
||||
#endif
|
||||
/* Check IP Assignment Configuration */
|
||||
#if((WCHNET_NUM_IP_REASSDATA > 10) || (WCHNET_NUM_IP_REASSDATA < 1))
|
||||
#error "WCHNET_NUM_IP_REASSDATA Error,Please Config WCHNET_NUM_IP_REASSDATA < 10 && WCHNET_NUM_IP_REASSDATA >= 1 "
|
||||
#endif
|
||||
/* Check the number of reassembled IP PBUFs */
|
||||
#if(WCHNET_IP_REASS_PBUFS > WCHNET_NUM_POOL_BUF)
|
||||
#error "WCHNET_IP_REASS_PBUFS Error,Please Config WCHNET_IP_REASS_PBUFS < WCHNET_NUM_POOL_BUF"
|
||||
#endif
|
||||
|
||||
#if(WCHNETTIMERPERIOD > 50)
|
||||
#error "WCHNETTIMERPERIOD Error,Please Config WCHNETTIMERPERIOD < 50"
|
||||
#endif
|
||||
|
||||
/* Configuration value 0 */
|
||||
#define WCHNET_MISC_CONFIG0 (((CFG0_TCP_SEND_COPY) << 0) |\
|
||||
((CFG0_TCP_RECV_COPY) << 1) |\
|
||||
((CFG0_TCP_OLD_DELETE) << 2) |\
|
||||
((CFG0_IP_REASS_PBUFS) << 3) )
|
||||
/* Configuration value 1 */
|
||||
#define WCHNET_MISC_CONFIG1 (((WCHNET_MAX_SOCKET_NUM)<<0)|\
|
||||
((WCHNET_PING_ENABLE) << 13) |\
|
||||
((TCP_RETRY_COUNT) << 14) |\
|
||||
((TCP_RETRY_PERIOD) << 19) |\
|
||||
((SOCKET_SEND_RETRY) << 25) )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,990 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user