first submission
This commit is contained in:
qiyongshuang
@@ -0,0 +1,399 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : RISC-V Core Peripheral Access Layer Source File
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
|
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include <stdint.h>
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/* define compiler specific symbols */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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/**
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* @brief Return the Floating-Point Accrued Exceptions
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*/
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uint32_t __get_FFLAGS(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Floating-Point Accrued Exceptions
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*/
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void __set_FFLAGS(uint32_t value)
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{
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__ASM volatile ("csrw fflags, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Floating-Point Dynamic Rounding Mode
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*/
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uint32_t __get_FRM(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "frm" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Floating-Point Dynamic Rounding Mode
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*/
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void __set_FRM(uint32_t value)
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{
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__ASM volatile ("csrw frm, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Floating-Point Control and Status Register
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*/
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uint32_t __get_FCSR(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Floating-Point Control and Status Register
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*/
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void __set_FCSR(uint32_t value)
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{
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__ASM volatile ("csrw fcsr, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Status Register
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*/
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uint32_t __get_MSTATUS(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Status Register
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*/
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void __set_MSTATUS(uint32_t value)
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{
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__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine ISA Register
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*/
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uint32_t __get_MISA(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine ISA Register
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*/
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void __set_MISA(uint32_t value)
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{
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__ASM volatile ("csrw misa, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Interrupt Enable Register
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*/
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uint32_t __get_MIE(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mie" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine ISA Register
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*/
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void __set_MIE(uint32_t value)
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{
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__ASM volatile ("csrw mie, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Trap-Vector Base-Address Register
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*/
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uint32_t __get_MTVEC(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Trap-Vector Base-Address Register
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*/
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void __set_MTVEC(uint32_t value)
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{
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__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Seratch Register
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*/
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uint32_t __get_MSCRATCH(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Seratch Register
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*/
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void __set_MSCRATCH(uint32_t value)
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{
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__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Exception Program Register
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*/
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uint32_t __get_MEPC(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Exception Program Register
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*/
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void __set_MEPC(uint32_t value)
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{
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__ASM volatile ("csrw mepc, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Cause Register
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*/
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uint32_t __get_MCAUSE(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Cause Register
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*/
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void __set_MCAUSE(uint32_t value)
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{
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__ASM volatile ("csrw mcause, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Trap Value Register
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*/
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uint32_t __get_MTVAL(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Trap Value Register
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*/
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void __set_MTVAL(uint32_t value)
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{
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__ASM volatile ("csrw mtval, %0" : : "r" (value) );
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}
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/**
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* @brief Return the Machine Interrupt Pending Register
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*/
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uint32_t __get_MIP(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mip" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set the Machine Interrupt Pending Register
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*/
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void __set_MIP(uint32_t value)
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{
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__ASM volatile ("csrw mip, %0" : : "r" (value) );
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}
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/**
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* @brief Return Lower 32 bits of Cycle counter
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*/
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uint32_t __get_MCYCLE(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set Lower 32 bits of Cycle counter
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*/
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void __set_MCYCLE(uint32_t value)
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{
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__ASM volatile ("csrw mcycle, %0" : : "r" (value) );
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}
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/**
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* @brief Return Upper 32 bits of Cycle counter
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*/
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uint32_t __get_MCYCLEH(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set Upper 32 bits of Cycle counter
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*/
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void __set_MCYCLEH(uint32_t value)
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{
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__ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
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}
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/**
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* @brief Return Lower 32 bits of Instructions-retired counter
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*/
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uint32_t __get_MINSTRET(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set Lower 32 bits of Instructions-retired counter
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*/
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void __set_MINSTRET(uint32_t value)
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{
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__ASM volatile ("csrw minstret, %0" : : "r" (value) );
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}
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/**
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* @brief Return Upper 32 bits of Instructions-retired counter
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*/
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uint32_t __get_MINSTRETH(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Set Upper 32 bits of Instructions-retired counter
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*/
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void __set_MINSTRETH(uint32_t value)
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{
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__ASM volatile ("csrw minstreth, %0" : : "r" (value) );
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}
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/**
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* @brief Return Vendor ID Register
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*/
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uint32_t __get_MVENDORID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Return Machine Architecture ID Register
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*/
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uint32_t __get_MARCHID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Return Machine Implementation ID Register
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*/
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uint32_t __get_MIMPID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Return Hart ID Register
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*/
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uint32_t __get_MHARTID(void)
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{
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uint32_t result;
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__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
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return (result);
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}
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/**
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* @brief Return SP Register
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*/
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uint32_t __get_SP(void)
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{
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uint32_t result;
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asm volatile (
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"mv %0," "sp"
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: "=r"(result)
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:
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);
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return (result);
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}
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||||
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@@ -0,0 +1,329 @@
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/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : RISC-V Core Peripheral Access Layer Header File for CH32V20x
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
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#define __CORE_RISCV_H__
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/* IO definitions */
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||||
#ifdef __cplusplus
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#define __I volatile /*!< defines 'read only' permissions */
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#else
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#define __I volatile const /*!< defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< defines 'write only' permissions */
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#define __IO volatile /*!< defines 'read / write' permissions */
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/* Standard Peripheral Library old types (maintained for legacy purpose) */
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typedef __I uint64_t vuc64; /* Read Only */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint64_t uc64; /* Read Only */
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int64_t vsc64; /* Read Only */
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int64_t sc64; /* Read Only */
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint64_t vu64;
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint64_t u64;
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int64_t vs64;
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int64_t s64;
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t RESERVED;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
uint8_t VTFIDR[4];
|
||||
uint8_t RESERVED0[12];
|
||||
__IO uint32_t VTFADDR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
}PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO u32 CTLR;
|
||||
__IO u32 SR;
|
||||
__IO u64 CNT;
|
||||
__IO u64 CMP;
|
||||
}SysTick_Type;
|
||||
|
||||
|
||||
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
|
||||
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||
|
||||
/* risc-v specific functions */
|
||||
RV_STATIC_INLINE void __enable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); }
|
||||
RV_STATIC_INLINE void __disable_irq() { __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); }
|
||||
RV_STATIC_INLINE void __NOP() { __asm volatile ("nop"); }
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_EnableIRQ
|
||||
* Description : Enable Interrupt
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_DisableIRQ
|
||||
* Description : Disable Interrupt
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_GetStatusIRQ
|
||||
* Description : Get Interrupt Enable State
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : 1: Interrupt Enable
|
||||
* 0: Interrupt Disable
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_GetPendingIRQ
|
||||
* Description : Get Interrupt Pending State
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : 1: Interrupt Pending Enable
|
||||
* 0: Interrupt Pending Disable
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_SetPendingIRQ
|
||||
* Description : Set Interrupt Pending
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_ClearPendingIRQ
|
||||
* Description : Clear Interrupt Pending
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_GetActive
|
||||
* Description : Get Interrupt Active State
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* Return : 1: Interrupt Active
|
||||
* 0: Interrupt No Active
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_SetPriority
|
||||
* Description : Set Interrupt Priority
|
||||
* Input : IRQn: Interrupt Numbers
|
||||
* priority: bit7:pre-emption priority
|
||||
* bit6-bit4: subpriority
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : __WFI
|
||||
* Description : Wait for Interrupt
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : __WFE
|
||||
* Description : Wait for Events
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->SCTLR;
|
||||
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
|
||||
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
|
||||
asm volatile ("wfi");
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SetVTFIRQ
|
||||
* Description : Set VTF Interrupt
|
||||
* Input : addr��VTF interrupt service function base address.
|
||||
* IRQn��Interrupt Numbers
|
||||
* num��VTF Interrupt Numbers
|
||||
* NewState: DISABLE or ENABLE
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
|
||||
if(num > 3) return ;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)|0x1);
|
||||
}
|
||||
else{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xF00FFFFE)&(~0x1));
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_SystemReset
|
||||
* Description : Initiate a system reset request
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_FFLAGS(void);
|
||||
extern void __set_FFLAGS(uint32_t value);
|
||||
extern uint32_t __get_FRM(void);
|
||||
extern void __set_FRM(uint32_t value);
|
||||
extern uint32_t __get_FCSR(void);
|
||||
extern void __set_FCSR(uint32_t value);
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MIE(void);
|
||||
extern void __set_MIE(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MIP(void);
|
||||
extern void __set_MIP(uint32_t value);
|
||||
extern uint32_t __get_MCYCLE(void);
|
||||
extern void __set_MCYCLE(uint32_t value);
|
||||
extern uint32_t __get_MCYCLEH(void);
|
||||
extern void __set_MCYCLEH(uint32_t value);
|
||||
extern uint32_t __get_MINSTRET(void);
|
||||
extern void __set_MINSTRET(uint32_t value);
|
||||
extern uint32_t __get_MINSTRETH(void);
|
||||
extern void __set_MINSTRETH(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user