first submission
This commit is contained in:
qiyongshuang
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="Udisk_Lib|Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
|
||||
<entry excluding="startup_ch32v20x_D8W.S|startup_ch32v20x_D8.S|startup_ch32v30x_D8C.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="obj">
|
||||
<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/000"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Release">
|
||||
<resource resourceType="PROJECT" workspacePath="/000"/>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
@@ -0,0 +1,59 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>APP</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>Core</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-4-PROJECT_LOC/SRC/Core</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Debug</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-4-PROJECT_LOC/SRC/Debug</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Peripheral</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-4-PROJECT_LOC/SRC/Peripheral</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>Startup</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-4-PROJECT_LOC/SRC/Startup</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>1595986042669</id>
|
||||
<name></name>
|
||||
<type>22</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
</filteredResources>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-998353469521742118" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@@ -0,0 +1,16 @@
|
||||
Mcu Type=CH32V20x
|
||||
Address=0x08000000
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=true
|
||||
Reset=true
|
||||
|
||||
Vendor=WCH
|
||||
Link=WCH-Link
|
||||
Toolchain=RISC-V
|
||||
Series=CH32V307
|
||||
Description=ROM(byte): 256K, SRAM(byte): 64K, CHIP PINS: 64, GPIO PORTS: 51.\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||
|
||||
PeripheralVersion=1.4
|
||||
MCU=CH32V307RVT6
|
||||
Target Path=obj/APP.hex
|
||||
@@ -0,0 +1,2 @@
|
||||
�i“CZ ?"Ç�¸rŸ�F<Fy8E9Y‡½„%P a³D¶La† %Ã'y€¡]Ç;’¶ ŸS)1†1+R4><‚.„ÇÅ¿º° ?/£XO©Ä¿ChQN$*¢”»EÅBk‹!2tŒ+buh†nUb]xl‹l|
|
||||
+"Ÿ<“¯AH42}z8p;m€u 1Ž-¦eh»Od¼Âwµª7x{5�CqEx©=;¦¢e¢º»2£Š ‚«* BP Mš"
|
||||
@@ -0,0 +1 @@
|
||||
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{ ␍/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */␍/*␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K␍*/ ␍␍/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */␍/**/␍/*␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍*/␍ FLASH (rx) : ORIGIN = 0x00005000, LENGTH = 44K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K␍ ␍/* CH32V20x_D8 - CH32V203RB␍ CH32V20x_D8W - CH32V208x␍ FLASH + RAM supports the following configuration␍ FLASH-128K + RAM-64K␍ FLASH-144K + RAM-48K␍ FLASH-160K + RAM-32K␍␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K␍*/␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.glue_7)␍ *(.glue_7t)␍ *(.gnu.linkonce.t.*)␍ . = ALIGN(4);␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . ); ␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
|
||||
@@ -0,0 +1,42 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_it.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,218 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/20
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/*
|
||||
*@Note
|
||||
With HOST_IAP, with as IAP's supporting APP use. The generated Hex file needs to be converted to a bin file.
|
||||
*/
|
||||
|
||||
#include "debug.h"
|
||||
#include "stdio.h"
|
||||
#include "string.h"
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Macro Definitions */
|
||||
#define DEF_FLASH_PAGE_SIZE 0x100
|
||||
|
||||
/* APP CODE ADDR Setting */
|
||||
#define DEF_APP_CODE_START_ADDR 0x08005000 /* IAP Flash Operation start address, user code start address */
|
||||
#ifdef CH32V20x_D6
|
||||
#define DEF_APP_CODE_END_ADDR 0x08010000 /* IAP Flash Operation end address, user code end address */
|
||||
/* Please refer to link.ld file for accuracy flash size, the size here is the smallest available size */
|
||||
/* CH32V203C8/G8/F8 - 0x08010000 (64K), CH32F203C6 - 0x08008000 (32K) */
|
||||
#else
|
||||
#define DEF_APP_CODE_END_ADDR 0x08020000 /* IAP Flash Operation end address, user code end address */
|
||||
/* Please refer to link.ld file for accuracy flash size, the size here is the smallest available size */
|
||||
/* CH32V203RB/208x - 0x08020000 (128K) */
|
||||
#endif
|
||||
#define DEF_APP_CODE_MAXLEN (DEF_APP_CODE_END_ADDR-DEF_APP_CODE_START_ADDR) /* IAP Flash Operation size, user code max size */
|
||||
|
||||
/* Verify CODE ADDR Setting */
|
||||
#define DEF_VERIFY_CODE_START_ADDR 0x08004F00 /* IAP Flash verify-code start address */
|
||||
#define DEF_VERIFY_CODE_END_ADDR 0x08005000 /* IAP Flash verify-code end address */
|
||||
#define DEF_VERIFY_CODE_MAXLEN (DEF_VERIFY_CODE_END_ADDR-DEF_VERIFY_CODE_START_ADDR) /* IAP Flash verify-code max size */
|
||||
#define DEF_VERIFY_CODE_LEN 0x10 /* IAP Flash verify-code actual length, be careful not to exceed the DEF_VERIFY_CODE_MAXLEN */
|
||||
|
||||
/* Flash Operation Key Setting */
|
||||
#define DEF_FLASH_OPERATION_KEY_CODE_0 0x1A86FF00 /* IAP Flash operation Key-code 0 */
|
||||
#define DEF_FLASH_OPERATION_KEY_CODE_1 0x55AA55AA /* IAP Flash operation Key-code 1 */
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Flash Operation Key */
|
||||
volatile uint32_t Flash_Operation_Key0;
|
||||
volatile uint32_t Flash_Operation_Key1;
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Function Statement */
|
||||
void GPIO_Cfg_init( void );
|
||||
uint8_t PA0_Check( void );
|
||||
uint8_t IAP_VerifyCode_Erase( void );
|
||||
uint8_t IAP_Flash_Erase( uint32_t address, uint32_t length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
uint8_t ret;
|
||||
Delay_Init( );
|
||||
Delay_Ms(500);
|
||||
USART_Printf_Init(115200);
|
||||
printf("SystemClk:%d\r\n",SystemCoreClock);
|
||||
printf("This is a APP code for a IAP application\n" );
|
||||
GPIO_Cfg_init( );
|
||||
|
||||
Flash_Operation_Key0 = DEF_FLASH_OPERATION_KEY_CODE_0;
|
||||
|
||||
while(1)
|
||||
{
|
||||
ret = PA0_Check( );
|
||||
if( ret )
|
||||
{
|
||||
printf( "Reset Chip, prepare to Jump To IAP\r\n" );
|
||||
printf( "Erase Verify-Code\r\n" );
|
||||
IAP_VerifyCode_Erase( );
|
||||
NVIC_SystemReset( );
|
||||
}
|
||||
Delay_Ms( 200 );
|
||||
printf( "USER Code\r\n" );
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Flash_Erase
|
||||
*
|
||||
* @brief Erase Flash In page(256 bytes),Specify length & address,
|
||||
* Based On Fast Flash Operation,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return 0: Operation Success
|
||||
* See notes for other errors
|
||||
*/
|
||||
uint8_t IAP_Flash_Erase( uint32_t address, uint32_t length )
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t erase_addr;
|
||||
uint32_t erase_len;
|
||||
volatile uint32_t page_cnts;
|
||||
volatile uint32_t page_addr;
|
||||
|
||||
/* Set initial value */
|
||||
erase_addr = address;
|
||||
page_addr = address;
|
||||
erase_len = length;
|
||||
if( (erase_len%256) == 0 )
|
||||
{
|
||||
page_cnts = erase_len/256;
|
||||
}
|
||||
else
|
||||
{
|
||||
page_cnts = (erase_len/256) + 1;
|
||||
}
|
||||
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if( (Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0) || (Flash_Operation_Key1 != DEF_FLASH_OPERATION_KEY_CODE_1) )
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
/* Verify Address, No flash operation if the address is out of range */
|
||||
if( ((erase_addr >= DEF_APP_CODE_START_ADDR) && (erase_addr <= DEF_APP_CODE_END_ADDR)) || ((erase_addr >= DEF_VERIFY_CODE_START_ADDR) && (erase_addr <= DEF_VERIFY_CODE_END_ADDR)) )
|
||||
{
|
||||
for( i=0; i<page_cnts; i++ )
|
||||
{
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if( Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0 )
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
FLASH_Unlock_Fast( );
|
||||
FLASH_ErasePage_Fast( page_addr );
|
||||
page_addr += DEF_FLASH_PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_VerifyCode_Erase
|
||||
*
|
||||
* @brief Erase IAP VerifyCode, Based On Fast Flash Operation.
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return ret : The meaning of 'ret' can be found in the notes of the
|
||||
* corresponding function.
|
||||
*/
|
||||
uint8_t IAP_VerifyCode_Erase( void )
|
||||
{
|
||||
uint8_t ret;
|
||||
|
||||
/* Verify Code Erase */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Erase( DEF_VERIFY_CODE_START_ADDR, DEF_VERIFY_CODE_MAXLEN );
|
||||
Flash_Operation_Key1 = 0;
|
||||
if( ret != 0 )
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Cfg_init
|
||||
*
|
||||
* @brief GPIO init
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Cfg_init( void )
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PA0_Check
|
||||
*
|
||||
* @brief Check PA0 state
|
||||
*
|
||||
* @return 0 - not Press Down
|
||||
* 1 - Press Down
|
||||
*/
|
||||
uint8_t PA0_Check( void )
|
||||
{
|
||||
u8 i;
|
||||
GPIO_Cfg_init();
|
||||
i = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0);
|
||||
if (i == 0)
|
||||
{
|
||||
Delay_Ms(200);
|
||||
i = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0);
|
||||
if (i == 0)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,986 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,166 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
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|
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|
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|
||||
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@@ -0,0 +1,66 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
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|
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<name>HOST_IAP</name>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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||||
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@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
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|
||||
<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1175690369799550824" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
@@ -0,0 +1,16 @@
|
||||
Mcu Type=CH32V20x
|
||||
Address=0x08000000
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=true
|
||||
Reset=true
|
||||
|
||||
Vendor=WCH
|
||||
Link=WCH-Link
|
||||
Toolchain=RISC-V
|
||||
Series=CH32V307
|
||||
Description=ROM(byte): 256K, SRAM(byte): 64K, CHIP PINS: 64, GPIO PORTS: 51.\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||
|
||||
PeripheralVersion=1.4
|
||||
Target Path=obj\HOST_IAP.hex
|
||||
MCU=CH32V307RVT6
|
||||
@@ -0,0 +1,2 @@
|
||||
�i“CZ ?"Ç�¸rŸ�F<Fy8E9Y‡½„%P a³D¶La† %Ã'y€¡]Ç;’¶ ŸS)1†1+R4><‚.„ÇÅ¿º° ?/£XO©Ä¿ChQN$*¢”»EÅBk‹!2tŒ+buh†nUb]xl‹l|
|
||||
+"Ÿ<“¯AH42}z8p;m€u 1Ž-¦eh»Od¼Âwµª7x{5�CqEx©=;¦¢e¢º»2£Š ‚«* BP Mš"
|
||||
@@ -0,0 +1,967 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : iap.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/20
|
||||
* Description : IAP
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "usb_host_iap.h"
|
||||
|
||||
/* Variable */
|
||||
__attribute__((aligned(4))) uint8_t IAPLoadBuffer[ DEF_MAX_IAP_BUFFER_LEN ];
|
||||
__attribute__((aligned(4))) uint8_t Com_Buffer[ DEF_COM_BUF_LEN ]; // even address , used for host enumcation and udisk operation
|
||||
__attribute__((aligned(4))) uint8_t DevDesc_Buf[ 18 ]; // Device Descriptor Buffer
|
||||
volatile uint32_t IAP_Load_Addr_Offset;
|
||||
volatile uint32_t IAP_WriteIn_Length;
|
||||
volatile uint32_t IAP_WriteIn_Count;
|
||||
struct _ROOT_HUB_DEVICE RootHubDev[ DEF_TOTAL_ROOT_HUB ];
|
||||
struct __HOST_CTL HostCtl[ DEF_TOTAL_ROOT_HUB * DEF_ONE_USB_SUP_DEV_TOTAL ];
|
||||
|
||||
/* Verify Code */
|
||||
const uint8_t Verify_Code[ DEF_VERIFY_CODE_LEN ] =
|
||||
{ '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
|
||||
|
||||
/* Flash Operation Key */
|
||||
volatile uint32_t Flash_Operation_Key0;
|
||||
volatile uint32_t Flash_Operation_Key1;
|
||||
|
||||
#if DEF_CORE_TYPE == DEF_CORE_CM3
|
||||
iapfun jump2app;
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ReadByte
|
||||
*
|
||||
* @brief Read Flash In byte(8 bits)
|
||||
*
|
||||
* @return 8bits data readout
|
||||
*/
|
||||
uint8_t FLASH_ReadByte(uint32_t address)
|
||||
{
|
||||
return *(__IO uint8_t*)address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ReadHalfWord
|
||||
*
|
||||
* @brief Read Flash In HalfWord(16 bits)
|
||||
*
|
||||
* @return 16bits data readout
|
||||
*/
|
||||
uint16_t FLASH_ReadHalfWord(uint32_t address)
|
||||
{
|
||||
return *(__IO uint16_t*)address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ReadWord
|
||||
*
|
||||
* @brief Read Flash In Word(32 bits).
|
||||
*
|
||||
* @return 32bits data readout
|
||||
*/
|
||||
uint32_t FLASH_ReadWord(uint32_t address)
|
||||
{
|
||||
return *(__IO uint32_t*)address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ReadWordAdd
|
||||
*
|
||||
* @brief Read Flash In Word(32 bits),Specify length & address
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void FLASH_ReadWordAdd(uint32_t address, u32* buff, uint16_t length)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
for(i = 0; i < length; i++)
|
||||
{
|
||||
buff[i] = *(__IO uint32_t*)address;//��ָ����ַ��һ���ֵ�����
|
||||
address += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Flash_Read
|
||||
*
|
||||
* @brief Read Flash In bytes(8 bits),Specify length & address,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return 0: Operation Success
|
||||
* See notes for other errors
|
||||
*/
|
||||
uint8_t IAP_Flash_Read(uint32_t address, uint8_t* buff, uint32_t length)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t read_addr;
|
||||
uint32_t read_len;
|
||||
read_addr = address;
|
||||
read_len = length;
|
||||
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if((Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0) || (Flash_Operation_Key1 != DEF_FLASH_OPERATION_KEY_CODE_1))
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
/* Verify Address, No flash operation if the address is out of range */
|
||||
if(((read_addr >= DEF_APP_CODE_START_ADDR) && (read_addr <= DEF_APP_CODE_END_ADDR)) || ((read_addr >= DEF_VERIFY_CODE_START_ADDR) && (read_addr <= DEF_VERIFY_CODE_END_ADDR)))
|
||||
{
|
||||
/* Available Data */
|
||||
for(i = 0; i < read_len; i++)
|
||||
{
|
||||
buff[i] = *(__IO uint8_t*)read_addr;//Read one word of data at the specified address
|
||||
read_addr++;
|
||||
}
|
||||
#if 0
|
||||
DUG_PRINTF("i %d\n", i);
|
||||
DUG_PRINTF("read_len %d\n", read_len);
|
||||
#endif
|
||||
if(i != read_len)
|
||||
{
|
||||
/* Incorrect read length */
|
||||
return 0xFD;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* address Out Of Range */
|
||||
return 0xFE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn mFLASH_ProgramPage_Fast
|
||||
*
|
||||
* @brief Fast programming, input variable addresses and data buffers,
|
||||
* no longer than one page at a time.
|
||||
* The content of the functions can be written according to the
|
||||
* chip flash fast programming process by yourself
|
||||
*
|
||||
* @return 0: Operation Success
|
||||
* See notes for other errors
|
||||
*/
|
||||
uint8_t mFLASH_ProgramPage_Fast(uint32_t addr, uint32_t* buffer)
|
||||
{
|
||||
/* ����оƬ��flash��������Ĵ˴����� */
|
||||
FLASH_ProgramPage_Fast( addr, buffer );
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Flash_Write
|
||||
*
|
||||
* @brief Write Flash In bytes(8 bits),Specify length & address,
|
||||
* Based On Fast Flash Operation,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return 0: Operation Success
|
||||
* See notes for other errors
|
||||
*/
|
||||
uint8_t IAP_Flash_Write(uint32_t address, uint8_t* buff, uint32_t length)
|
||||
{
|
||||
uint32_t i, j;
|
||||
uint32_t write_addr;
|
||||
uint32_t write_len;
|
||||
uint16_t write_len_once;
|
||||
uint32_t write_cnts;
|
||||
volatile uint32_t page_cnts;
|
||||
volatile uint32_t page_addr;
|
||||
uint8_t temp_buf[DEF_FLASH_PAGE_SIZE];
|
||||
|
||||
/* Set initial value */
|
||||
write_addr = address;
|
||||
page_addr = address;
|
||||
write_len = length;
|
||||
if((write_len % DEF_FLASH_PAGE_SIZE) == 0)
|
||||
{
|
||||
page_cnts = write_len / DEF_FLASH_PAGE_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
page_cnts = (write_len / DEF_FLASH_PAGE_SIZE) + 1;
|
||||
}
|
||||
write_cnts = 0;
|
||||
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if((Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0) || (Flash_Operation_Key1 != DEF_FLASH_OPERATION_KEY_CODE_1))
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
/* Verify Address, No flash operation if the address is out of range */
|
||||
if(((write_addr >= DEF_APP_CODE_START_ADDR) && (write_addr <= DEF_APP_CODE_END_ADDR)) || ((write_addr >= DEF_VERIFY_CODE_START_ADDR) && (write_addr <= DEF_VERIFY_CODE_END_ADDR)))
|
||||
{
|
||||
for(i = 0; i < page_cnts; i++)
|
||||
{
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if(Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0)
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
/* Determine if the length of the written packet is less than the page size */
|
||||
/* If it is less than, the original content of the memory needs to be read out first and modified before the operation can be performed */
|
||||
write_len_once = DEF_FLASH_PAGE_SIZE;
|
||||
FLASH_Unlock_Fast();
|
||||
FLASH_ErasePage_Fast(page_addr);
|
||||
if(write_len < DEF_FLASH_PAGE_SIZE)
|
||||
{
|
||||
FLASH_Unlock_Fast();
|
||||
IAP_Flash_Read(page_addr, temp_buf, DEF_FLASH_PAGE_SIZE);
|
||||
|
||||
for(j = 0; j < write_len; j++)
|
||||
{
|
||||
temp_buf[j] = buff[DEF_FLASH_PAGE_SIZE * i + j];
|
||||
}
|
||||
write_len_once = write_len;
|
||||
mFLASH_ProgramPage_Fast(page_addr, (u32*)&temp_buf[0]);
|
||||
}
|
||||
else
|
||||
{
|
||||
mFLASH_ProgramPage_Fast(page_addr, (u32*)&buff[DEF_FLASH_PAGE_SIZE * i]);
|
||||
}
|
||||
page_addr += DEF_FLASH_PAGE_SIZE;
|
||||
write_len -= write_len_once;
|
||||
write_cnts++;
|
||||
}
|
||||
if(i != write_cnts)
|
||||
{
|
||||
/* Incorrect read length */
|
||||
return 0xFD;
|
||||
}
|
||||
FLASH_Lock_Fast();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* address Out Of Range */
|
||||
return 0xFE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Flash_Erase
|
||||
*
|
||||
* @brief Erase Flash In page(256 bytes),Specify length & address,
|
||||
* Based On Fast Flash Operation,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return 0: Operation Success
|
||||
* See notes for other errors
|
||||
*/
|
||||
uint8_t IAP_Flash_Erase(uint32_t address, uint32_t length)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t erase_addr;
|
||||
uint32_t erase_len;
|
||||
volatile uint32_t page_cnts;
|
||||
volatile uint32_t page_addr;
|
||||
|
||||
/* Set initial value */
|
||||
erase_addr = address;
|
||||
page_addr = address;
|
||||
erase_len = length;
|
||||
if((erase_len % DEF_FLASH_PAGE_SIZE) == 0)
|
||||
{
|
||||
page_cnts = erase_len / DEF_FLASH_PAGE_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
page_cnts = (erase_len / DEF_FLASH_PAGE_SIZE) + 1;
|
||||
}
|
||||
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if((Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0) || (Flash_Operation_Key1 != DEF_FLASH_OPERATION_KEY_CODE_1))
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
/* Verify Address, No flash operation if the address is out of range */
|
||||
if(((erase_addr >= DEF_APP_CODE_START_ADDR) && (erase_addr <= DEF_APP_CODE_END_ADDR)) || ((erase_addr >= DEF_VERIFY_CODE_START_ADDR) && (erase_addr <= DEF_VERIFY_CODE_END_ADDR)))
|
||||
{
|
||||
for(i = 0; i < page_cnts; i++)
|
||||
{
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if(Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0)
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFF;
|
||||
}
|
||||
FLASH_Unlock_Fast();
|
||||
FLASH_ErasePage_Fast(page_addr);
|
||||
page_addr += DEF_FLASH_PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Flash_Verify
|
||||
*
|
||||
* @brief verify Flash In bytes(8 bits),Specify length & address,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return 0: Operation Success
|
||||
* See notes for other errors
|
||||
*/
|
||||
uint32_t IAP_Flash_Verify(uint32_t address, uint8_t* buff, uint32_t length)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t read_addr;
|
||||
uint32_t read_len;
|
||||
|
||||
/* Set initial value */
|
||||
read_addr = address;
|
||||
read_len = length;
|
||||
|
||||
/* Verify Keys, No flash operation if keys are not correct */
|
||||
if((Flash_Operation_Key0 != DEF_FLASH_OPERATION_KEY_CODE_0) || (Flash_Operation_Key1 != DEF_FLASH_OPERATION_KEY_CODE_1))
|
||||
{
|
||||
/* ERR: Risk of code running away */
|
||||
return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/* Verify Address, No flash operation if the address is out of range */
|
||||
if(((read_addr >= DEF_APP_CODE_START_ADDR) && (read_addr <= DEF_APP_CODE_END_ADDR)) || ((read_addr >= DEF_VERIFY_CODE_START_ADDR) && (read_addr <= DEF_VERIFY_CODE_END_ADDR)))
|
||||
{
|
||||
for(i = 0; i < read_len; i++)
|
||||
{
|
||||
if(FLASH_ReadByte(read_addr) != buff[i])
|
||||
{
|
||||
/* To prevent 0-length errors, the returned position +1 */
|
||||
return i + 1;
|
||||
}
|
||||
read_addr ++;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Flash_Program
|
||||
*
|
||||
* @brief IAP programming code, including write and verify,
|
||||
* Specify length & address, Based On Fast Flash Operation,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return ret : The meaning of 'ret' can be found in the notes of the
|
||||
* corresponding function.
|
||||
*/
|
||||
uint32_t IAP_Flash_Program(uint32_t address, uint8_t* buff, uint32_t length)
|
||||
{
|
||||
uint32_t ret;
|
||||
/* IAP Write */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Write(address, buff, length);
|
||||
Flash_Operation_Key1 = 0;
|
||||
if(ret != 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
/* IAP Verify */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Verify(address, buff, length);
|
||||
Flash_Operation_Key1 = 0;
|
||||
if(ret != 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_VerifyCode_Write
|
||||
*
|
||||
* @brief IAP VerifyCode Write in, including write and verify,
|
||||
* Based On Fast Flash Operation.
|
||||
* With address protection and program runaway protection.
|
||||
* If an operation is unsuccessful,the code will repeat the
|
||||
* operation up to 5 times and if it is still unsuccessful,
|
||||
* an error code will be returned.
|
||||
*
|
||||
* @return ret : The meaning of 'ret' can be found in the notes of the
|
||||
* corresponding function.
|
||||
*/
|
||||
uint32_t IAP_VerifyCode_Write(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
uint8_t rty_cnts;
|
||||
rty_cnts = 0;
|
||||
|
||||
IAP_VERIFYCODE_RTY:
|
||||
/* Verify Code Write-in */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Write(DEF_VERIFY_CODE_START_ADDR, (uint8_t*)Verify_Code, DEF_VERIFY_CODE_LEN);
|
||||
Flash_Operation_Key1 = 0;
|
||||
if(ret != 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Verify Code Check */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Verify(DEF_VERIFY_CODE_START_ADDR, (uint8_t*)Verify_Code, DEF_VERIFY_CODE_LEN);
|
||||
Flash_Operation_Key1 = 0;
|
||||
if(ret != 0)
|
||||
{
|
||||
rty_cnts++;
|
||||
if(rty_cnts >= 5)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
goto IAP_VERIFYCODE_RTY;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_VerifyCode_Check
|
||||
*
|
||||
* @brief Check IAP VerifyCode,
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return ret : The meaning of 'ret' can be found in the notes of the
|
||||
* corresponding function.
|
||||
*/
|
||||
uint32_t IAP_VerifyCode_Check(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
/* Verify Code Check */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Verify(DEF_VERIFY_CODE_START_ADDR, (uint8_t*)Verify_Code, DEF_VERIFY_CODE_LEN);
|
||||
Flash_Operation_Key1 = 0;
|
||||
if(ret != 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_VerifyCode_Erase
|
||||
*
|
||||
* @brief Erase IAP VerifyCode, Based On Fast Flash Operation.
|
||||
* With address protection and program runaway protection.
|
||||
*
|
||||
* @return ret : The meaning of 'ret' can be found in the notes of the
|
||||
* corresponding function.
|
||||
*/
|
||||
uint8_t IAP_VerifyCode_Erase(void)
|
||||
{
|
||||
uint8_t ret;
|
||||
|
||||
/* Verify Code Erase */
|
||||
Flash_Operation_Key1 = DEF_FLASH_OPERATION_KEY_CODE_1;
|
||||
ret = IAP_Flash_Erase(DEF_VERIFY_CODE_START_ADDR, DEF_VERIFY_CODE_MAXLEN);
|
||||
Flash_Operation_Key1 = 0;
|
||||
if(ret != 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if DEF_CORE_TYPE == DEF_CORE_CM3
|
||||
/*********************************************************************
|
||||
* @fn MSR_MSP
|
||||
*
|
||||
* @brief Set stack top address
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__asm void MSR_MSP(u32 addr)
|
||||
{
|
||||
MSR MSP, r0 //set Main Stack value
|
||||
BX r14
|
||||
}
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Jump_APP
|
||||
*
|
||||
* @brief Start the Operation of jumping to user application
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IAP_Jump_APP(void)
|
||||
{
|
||||
DUG_PRINTF("User Code!\r\n");
|
||||
/* Sys Deinit */
|
||||
/* .... */
|
||||
/* Jump Code */
|
||||
#if DEF_CORE_TYPE == DEF_CORE_CM3
|
||||
jump2app = (iapfun) * (vu32*)(DEF_APP_CODE_START_ADDR + 4); //�û��������ڶ�����Ϊ����ʼ��ַ(��λ��ַ)
|
||||
MSR_MSP(*(vu32*)DEF_APP_CODE_START_ADDR); //��ʼ���û���������ջָ��(�û��������ĵ�һ�������ڴ��ջ����ַ)
|
||||
jump2app(); //��ת��APP.
|
||||
#elif DEF_CORE_TYPE == DEF_CORE_RV
|
||||
/* Code for Jump, Enable Chip soft reset interrupt, jump to application code in soft reset interrupt */
|
||||
Delay_Ms(500);
|
||||
NVIC_EnableIRQ(Software_IRQn);
|
||||
NVIC_SetPendingIRQ(Software_IRQn);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn mStopIfError
|
||||
*
|
||||
* @brief Checking the operation status, displaying the error code and stopping if there is an error
|
||||
* input : iError - Error code input
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void mStopIfError( uint8_t iError )
|
||||
{
|
||||
if ( iError == ERR_SUCCESS )
|
||||
{
|
||||
/* operation success, return */
|
||||
return;
|
||||
}
|
||||
/* Display the errors */
|
||||
DUG_PRINTF( "Error:%02x\r\n", iError );
|
||||
/* After encountering an error, you should analyze the error code and CHRV3DiskStatus status, for example,
|
||||
* call CHRV3DiskReady to check whether the current USB disk is connected or not,
|
||||
* if the disk is disconnected then wait for the disk to be plugged in again and operate again,
|
||||
* Suggested steps to follow after an error:
|
||||
* 1, call CHRV3DiskReady once, if successful, then continue the operation, such as Open, Read/Write, etc.
|
||||
* 2?If CHRV3DiskReady is not successful, then the operation will be forced to start from the beginning.
|
||||
*/
|
||||
while(1)
|
||||
{ }
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Check_Verify_Code
|
||||
*
|
||||
* @brief Check IAP Verify-Code if exists, if exists then jump to APP Code,
|
||||
* else if stay in IAP code
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IAP_Check_Verify_Code(void)
|
||||
{
|
||||
uint8_t ret;
|
||||
DUG_PRINTF( "Check If Verify-Code Exists.\r\n" );
|
||||
ret = IAP_VerifyCode_Check( );
|
||||
if( ret == 0x00 )
|
||||
{
|
||||
DUG_PRINTF( "Verify-Code Exists.\r\n" );
|
||||
/* Jump User Application */
|
||||
IAP_Jump_APP( );
|
||||
}
|
||||
DUG_PRINTF( "Verify-Code Not Exists, Goto UDisk Operation.\r\n" );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Initialization
|
||||
*
|
||||
* @brief IAP process Initialization, include usb-host initialization
|
||||
* usb libs initialization, iap-related values Initialization
|
||||
* IAP verify-code inspection
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IAP_Initialization( void )
|
||||
{
|
||||
/* IAP verify-code inspection */
|
||||
Flash_Operation_Key0 = DEF_FLASH_OPERATION_KEY_CODE_0;
|
||||
IAP_Check_Verify_Code( );
|
||||
|
||||
/* USB Host Initialization */
|
||||
printf( "USB Host & UDisk Lib Initialization. \r\n" );
|
||||
/* Initialize USBFS host */
|
||||
DUG_PRINTF( "USBFS Host Init\r\n" );
|
||||
USBFS_RCC_Init( );
|
||||
USBFS_Host_Init( ENABLE );
|
||||
memset( &RootHubDev[ DEF_USB_PORT_FS ].bStatus, 0, sizeof( struct _ROOT_HUB_DEVICE ) );
|
||||
memset( &HostCtl[ DEF_USB_PORT_FS ].InterfaceNum, 0, sizeof( struct __HOST_CTL ) );
|
||||
|
||||
/* USB Libs Initialization */
|
||||
printf( "UDisk library Initialization. \r\n" );
|
||||
CHRV3LibInit( );
|
||||
|
||||
/* IAP-related variable initialization */
|
||||
IAP_Load_Addr_Offset = 0;
|
||||
IAP_WriteIn_Length = 0;
|
||||
IAP_WriteIn_Count = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBH_EnumRootDevice
|
||||
*
|
||||
* @brief Generally enumerate a device connected to host port.
|
||||
*
|
||||
* @para index: USB host port
|
||||
*
|
||||
* @return Enumeration result
|
||||
*/
|
||||
uint8_t USBH_EnumRootDevice( uint8_t usb_port )
|
||||
{
|
||||
uint8_t s;
|
||||
uint8_t enum_cnt;
|
||||
uint8_t cfg_val;
|
||||
uint16_t i;
|
||||
uint16_t len;
|
||||
|
||||
DUG_PRINTF( "Enum:\r\n" );
|
||||
|
||||
enum_cnt = 0;
|
||||
ENUM_START:
|
||||
/* Delay and wait for the device to stabilize */
|
||||
Delay_Ms( 100 );
|
||||
enum_cnt++;
|
||||
Delay_Ms( 8 << enum_cnt );
|
||||
|
||||
/* Reset the USB device and wait for the USB device to reconnect */
|
||||
USBFSH_ResetRootHubPort( 0 );
|
||||
for( i = 0, s = 0; i < DEF_RE_ATTACH_TIMEOUT; i++ )
|
||||
{
|
||||
if( USBFSH_EnableRootHubPort( &RootHubDev[ usb_port ].bSpeed ) == ERR_SUCCESS )
|
||||
{
|
||||
i = 0;
|
||||
s++;
|
||||
if( s > 6 )
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
Delay_Ms( 1 );
|
||||
}
|
||||
if( i )
|
||||
{
|
||||
/* Determine whether the maximum number of retries has been reached, and retry if not reached */
|
||||
if( enum_cnt <= 5 )
|
||||
{
|
||||
goto ENUM_START;
|
||||
}
|
||||
return ERR_USB_DISCON;
|
||||
}
|
||||
|
||||
/* Select USB speed */
|
||||
USBFSH_SetSelfSpeed( RootHubDev[ usb_port].bSpeed );
|
||||
|
||||
/* Get USB device device descriptor */
|
||||
DUG_PRINTF("Get DevDesc: ");
|
||||
s = USBFSH_GetDeviceDescr( &RootHubDev[ usb_port ].bEp0MaxPks, DevDesc_Buf );
|
||||
if( s == ERR_SUCCESS )
|
||||
{
|
||||
/* Print USB device device descriptor */
|
||||
#if DEF_DEBUG_PRINTF
|
||||
for( i = 0; i < 18; i++ )
|
||||
{
|
||||
DUG_PRINTF( "%02x ", DevDesc_Buf[ i ] );
|
||||
}
|
||||
DUG_PRINTF("\n");
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Determine whether the maximum number of retries has been reached, and retry if not reached */
|
||||
DUG_PRINTF( "Err(%02x)\n", s );
|
||||
if( enum_cnt <= 5 )
|
||||
{
|
||||
goto ENUM_START;
|
||||
}
|
||||
return DEF_DEV_DESCR_GETFAIL;
|
||||
}
|
||||
|
||||
/* Set the USB device address */
|
||||
DUG_PRINTF("Set DevAddr: ");
|
||||
RootHubDev[ usb_port ].bAddress = (uint8_t)( DEF_USB_PORT_FS + USB_DEVICE_ADDR );
|
||||
s = USBFSH_SetUsbAddress( RootHubDev[ usb_port ].bEp0MaxPks, RootHubDev[ usb_port ].bAddress );
|
||||
if( s == ERR_SUCCESS )
|
||||
{
|
||||
DUG_PRINTF( "OK\n" );
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Determine whether the maximum number of retries has been reached, and retry if not reached */
|
||||
DUG_PRINTF( "Err(%02x)\n", s );
|
||||
if( enum_cnt <= 5 )
|
||||
{
|
||||
goto ENUM_START;
|
||||
}
|
||||
return DEF_DEV_ADDR_SETFAIL;
|
||||
}
|
||||
Delay_Ms( 5 );
|
||||
|
||||
/* Get the USB device configuration descriptor */
|
||||
DUG_PRINTF("Get CfgDesc: ");
|
||||
s = USBFSH_GetConfigDescr( RootHubDev[ usb_port ].bEp0MaxPks, Com_Buffer, DEF_COM_BUF_LEN, &len );
|
||||
if( s == ERR_SUCCESS )
|
||||
{
|
||||
cfg_val = ( (PUSB_CFG_DESCR)Com_Buffer )->bConfigurationValue;
|
||||
|
||||
/* Print USB device configuration descriptor */
|
||||
#if DEF_DEBUG_PRINTF
|
||||
for( i = 0; i < len; i++ )
|
||||
{
|
||||
DUG_PRINTF( "%02x ", Com_Buffer[ i ] );
|
||||
}
|
||||
DUG_PRINTF("\n");
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Determine whether the maximum number of retries has been reached, and retry if not reached */
|
||||
DUG_PRINTF( "Err(%02x)\n", s );
|
||||
if( enum_cnt <= 5 )
|
||||
{
|
||||
goto ENUM_START;
|
||||
}
|
||||
return DEF_CFG_DESCR_GETFAIL;
|
||||
}
|
||||
|
||||
/* Set USB device configuration value */
|
||||
DUG_PRINTF("Set Cfg: ");
|
||||
s = USBFSH_SetUsbConfig( RootHubDev[ usb_port ].bEp0MaxPks, cfg_val );
|
||||
if( s == ERR_SUCCESS )
|
||||
{
|
||||
DUG_PRINTF( "OK\n" );
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Determine whether the maximum number of retries has been reached, and retry if not reached */
|
||||
DUG_PRINTF( "Err(%02x)\n", s );
|
||||
if( enum_cnt <= 5 )
|
||||
{
|
||||
goto ENUM_START;
|
||||
}
|
||||
return ERR_USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_USBH_PreDeal
|
||||
*
|
||||
* @brief usb host preemption operations,
|
||||
* including detecting device insertion and enumerating device information
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t IAP_USBH_PreDeal( void )
|
||||
{
|
||||
uint8_t usb_port;
|
||||
uint8_t index;
|
||||
uint8_t ret;
|
||||
usb_port = DEF_USB_PORT_FS;
|
||||
ret = USBFSH_CheckRootHubPortStatus( RootHubDev[ usb_port ].bStatus );
|
||||
if( ret == ROOT_DEV_CONNECTED )
|
||||
{
|
||||
DUG_PRINTF("USB Dev In.\n");
|
||||
USBFSH_CheckRootHubPortStatus( RootHubDev[ usb_port ].bStatus );
|
||||
RootHubDev[ usb_port ].bStatus = ROOT_DEV_CONNECTED; // Set connection status_
|
||||
RootHubDev[ usb_port ].DeviceIndex = usb_port * DEF_ONE_USB_SUP_DEV_TOTAL;
|
||||
|
||||
/* Enumerate root device */
|
||||
ret = USBH_EnumRootDevice( usb_port );
|
||||
if( ret == ERR_SUCCESS )
|
||||
{
|
||||
DUG_PRINTF( "USB Port %02x Device Enumeration Succeed\r\n", usb_port );
|
||||
RootHubDev[ usb_port ].bStatus = ROOT_DEV_SUCCESS;
|
||||
return DEF_IAP_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
DUG_PRINTF( "USB Port %02x Device Enumeration ERR %02x.\r\n", usb_port, ret );
|
||||
RootHubDev[ usb_port ].bStatus = ROOT_DEV_FAILED;
|
||||
return DEF_IAP_ERR_ENUM;
|
||||
}
|
||||
}
|
||||
else if( ret == ROOT_DEV_DISCONNECT )
|
||||
{
|
||||
DUG_PRINTF("USB Port %02x Device Out.\r\n", usb_port );
|
||||
/* Clear parameters */
|
||||
index = RootHubDev[ usb_port ].DeviceIndex;
|
||||
memset( &RootHubDev[ usb_port ].bStatus, 0, sizeof( struct _ROOT_HUB_DEVICE ) );
|
||||
memset( &HostCtl[ index ].InterfaceNum, 0, sizeof( struct __HOST_CTL ) );
|
||||
return DEF_IAP_ERR_DETECT;
|
||||
}
|
||||
return DEF_IAP_DEFAULT;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IAP_Main_Deal
|
||||
*
|
||||
* @brief IAP Transaction Processing
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IAP_Main_Deal( void )
|
||||
{
|
||||
uint32_t totalcount, t;
|
||||
uint16_t i, ret;
|
||||
uint8_t *pCodeStr;
|
||||
static uint8_t op_flag = 0;
|
||||
|
||||
/* Detect USB Device & Enumeration processing */
|
||||
ret = IAP_USBH_PreDeal( );
|
||||
if( ret == DEF_IAP_SUCCESS )
|
||||
{
|
||||
/* Wait for uDisk Ready */
|
||||
CHRV3DiskStatus = DISK_USB_ADDR;
|
||||
for ( i = 0; i != 10; i ++ )
|
||||
{
|
||||
DUG_PRINTF( "Wait Disk Ready...\r\n" );
|
||||
ret = CHRV3DiskReady( );
|
||||
if ( ret == ERR_SUCCESS )
|
||||
{
|
||||
/* Disk Ready */
|
||||
DUG_PRINTF( "Disk Ready Code:%02x.\r\n", ret );
|
||||
DUG_PRINTF( "CHRV3DiskStatus:%02x\n", CHRV3DiskStatus);
|
||||
op_flag = 1;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
DUG_PRINTF("Not Ready Code :%02x.\r\n", ret);
|
||||
DUG_PRINTF("CHRV3DiskStatus:%02x.\n", CHRV3DiskStatus);
|
||||
}
|
||||
Delay_Ms( 50 );
|
||||
}
|
||||
}
|
||||
|
||||
if( (CHRV3DiskStatus >= DISK_MOUNTED) && op_flag )
|
||||
{
|
||||
op_flag = 0;
|
||||
/* Make sure the flash operation is correct */
|
||||
Flash_Operation_Key0 = DEF_FLASH_OPERATION_KEY_CODE_0;
|
||||
/* Set the name of the file to be manipulated to "/APP.BIN" */
|
||||
strcpy( (char *)mCmdParam.Open.mPathName, DEF_IAP_FILE_NAME );
|
||||
/* open file */
|
||||
ret = CHRV3FileOpen( );
|
||||
/* file or directory not found */
|
||||
if ( ret == ERR_MISS_DIR || ret == ERR_MISS_FILE )
|
||||
{
|
||||
/* list all file and stay in IAP code */
|
||||
DUG_PRINTF( "APP file not Found, Stay In IAP.\r\n" );
|
||||
pCodeStr = "/*";
|
||||
DUG_PRINTF( "List all files %s\r\n", pCodeStr );
|
||||
for ( i = 0; i < 10000; i ++ ) //Search up to the first 10,000 files, practically no limit
|
||||
{
|
||||
strcpy( (char *)mCmdParam.Open.mPathName, (char *)pCodeStr ); //Search for filenames, * is a wildcard, for all files or subdirectories
|
||||
ret = strlen( (char *)mCmdParam.Open.mPathName );
|
||||
mCmdParam.Open.mPathName[ ret ] = 0xFF; //Replace the terminator with the search number according to the length of the string, from 0 to 254,if it is 0xFF that is 255, then the search number is in the CHRV3vFileSize variable
|
||||
CHRV3vFileSize = i; //Specify the serial number of the search/enumeration
|
||||
ret = CHRV3FileOpen( ); //Open a file, if the file name contains a wildcard *, the file is searched for and not opened
|
||||
if ( ret == ERR_MISS_FILE ) //The only difference between CHRV3FileEnum and CHRV3FileOpen is that when the latter returns ERR_FOUND_NAME, then the former returns ERR_SUCCESS.
|
||||
{
|
||||
break; //No more matching files, no more matching file names
|
||||
}
|
||||
if ( ret == ERR_FOUND_NAME ) //Search for a file name matching the wildcard, the file name and its full path are in the command buffer
|
||||
{
|
||||
DUG_PRINTF( " match file %04d#: %s\r\n", (unsigned int)i, mCmdParam.Open.mPathName );//Display the serial number and the name of the matching file or subdirectory searched
|
||||
continue; //Continue searching for the next matching file name, the next search will add 1 to the serial number
|
||||
}
|
||||
else
|
||||
{
|
||||
mStopIfError( ret );
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Found file, start IAP processing */
|
||||
else
|
||||
{
|
||||
DUG_PRINTF( "File Found, Start IAP Process\r\n" );
|
||||
/* Read File Size */
|
||||
totalcount = CHRV3vFileSize;
|
||||
DUG_PRINTF( "File size in bytes: %d.\r\n", totalcount );
|
||||
/* Make sure the flash operation is correct */
|
||||
Flash_Operation_Key0 = DEF_FLASH_OPERATION_KEY_CODE_0;
|
||||
IAP_Load_Addr_Offset = 0;
|
||||
IAP_WriteIn_Length = 0;
|
||||
IAP_WriteIn_Count = 0;
|
||||
/* Binary file read & iap write in */
|
||||
while ( totalcount )
|
||||
{
|
||||
/* If the file is large and cannot be read at once, you can call CH103ByteRead again to continue reading, and the file pointer will move backward automatically.*/
|
||||
/* MAX_PATH_LEN: the maximum path length, including all slash separators and decimal point separators and path terminator 00H */
|
||||
if ( totalcount > (MAX_PATH_LEN-1) )
|
||||
{
|
||||
t = MAX_PATH_LEN-1; //The length of a single read/write cannot exceed sizeof( mCmdParam.Other.mBuffer ) if the remaining data is large.
|
||||
}
|
||||
else
|
||||
{
|
||||
t = totalcount; //Last remaining bytes
|
||||
}
|
||||
mCmdParam.ByteRead.mByteCount = t; //Request to read out tens of bytes of data
|
||||
mCmdParam.ByteRead.mByteBuffer= &Com_Buffer[0];
|
||||
ret = CHRV3ByteRead( ); //Read the data block in bytes, the length of a single read/write cannot exceed MAX_BYTE_IO, and the second call is followed by a backward read.
|
||||
mStopIfError( ret );
|
||||
totalcount -= mCmdParam.ByteRead.mByteCount; //Counting, subtracting the number of characters that have actually been read out
|
||||
for(i=0;i<mCmdParam.ByteRead.mByteCount;i++)
|
||||
{
|
||||
IAPLoadBuffer[IAP_WriteIn_Length]=mCmdParam.ByteRead.mByteBuffer[i];
|
||||
IAP_WriteIn_Length++;
|
||||
/* The whole package part of the IAP user file */
|
||||
if( IAP_WriteIn_Length == DEF_MAX_IAP_BUFFER_LEN )
|
||||
{
|
||||
/* Write Data In Flash */
|
||||
ret = IAP_Flash_Program( DEF_APP_CODE_START_ADDR+IAP_Load_Addr_Offset, IAPLoadBuffer, IAP_WriteIn_Length );
|
||||
mStopIfError( ret );
|
||||
IAP_Load_Addr_Offset += DEF_MAX_IAP_BUFFER_LEN;
|
||||
IAP_WriteIn_Count += IAP_WriteIn_Length;
|
||||
IAP_WriteIn_Length = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ( mCmdParam.ByteRead.mByteCount < t ) //The actual number of characters read is less than the number of characters requested, which means that the end of the file has been reached.
|
||||
{
|
||||
DUG_PRINTF( "\r\nFile End.\r\n" );
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Close the file be operated now */
|
||||
CHRV3FileClose( );
|
||||
/* Disposal of remaining package length */
|
||||
ret = IAP_Flash_Program( DEF_APP_CODE_START_ADDR+IAP_Load_Addr_Offset, IAPLoadBuffer, IAP_WriteIn_Length );
|
||||
mStopIfError( ret );
|
||||
IAP_WriteIn_Count += IAP_WriteIn_Length;
|
||||
/* Check actual write length and file length */
|
||||
DUG_PRINTF( "\r\nFileSze : %d,%d.\r\n", (int)CHRV3vFileSize, IAP_WriteIn_Count );
|
||||
if( CHRV3vFileSize == IAP_WriteIn_Count )
|
||||
{
|
||||
ret = IAP_VerifyCode_Write( );
|
||||
if( ret != ERR_SUCCESS )
|
||||
{
|
||||
/* IAP Verify code error, stay in IAP */
|
||||
DUG_PRINTF( "Verify-Code ERR %02x\r\n", ret );
|
||||
}
|
||||
DUG_PRINTF( "\r\nIAP End.\r\n" );
|
||||
/* Jump User Application */
|
||||
IAP_Jump_APP( );
|
||||
}
|
||||
else
|
||||
{
|
||||
/* IAP length checksum error */
|
||||
DUG_PRINTF( "IAP length checksum ERR. \r\n" );
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : iap.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/12/16
|
||||
* Description : IAP
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __USB_HOST_IAP_H
|
||||
#define __USB_HOST_IAP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "debug.h"
|
||||
#include "stdio.h"
|
||||
#include "string.h"
|
||||
#include "ch32v20x.h"
|
||||
#include "ch32v20x_usbfs_host.h"
|
||||
#include "usb_host_config.h"
|
||||
#include "CHRV3UFI.h"
|
||||
|
||||
/*******************************************************************************/
|
||||
/* File Descripton */
|
||||
/*
|
||||
*@Note
|
||||
������CH32ϵ�еĵ�Ƭ��������risc-v�ں˵�CH32Vϵ�к�cortex-m3�ں˵�CH32Fϵ��
|
||||
iap_flash.c/iap_flash.h�ļ�����iap��app��Ҫ��iap���������ֹ���壬app���������ֹ���壬
|
||||
оƬflash�IJ���������
|
||||
***2022��6��13��***
|
||||
1���汾0.1��
|
||||
�����Ĵ������flash�֣����֣��ֽڶ���iap�ػ���flash������д�룬��̣���ȡ��У�顣
|
||||
�����漰flash��д�������IJ�����ʹ��DEF_FLASH_OPERATION_KEY_CODE������DEF_FLASH_OPERATION_KEY_CODE_0
|
||||
����������ʼʱд�룬DEF_FLASH_OPERATION_KEY_CODE_1��ÿ�β���flashǰд�롣
|
||||
ʹ�ú궨������iap�����app���룬��iap��app��flash�����Ĵ���ͳһ��һ���ļ���
|
||||
iap���뿪�����к������ã�app���������IAP_VerifyCode_Erase(); ������
|
||||
*/
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Macro Definitions */
|
||||
#define DEF_CORE_RV 0x01
|
||||
#define DEF_CORE_CM3 0x10
|
||||
#define DEF_CORE_TYPE DEF_CORE_RV
|
||||
|
||||
/* IAP binary File */
|
||||
#define DEF_IAP_FILE_NAME "/APP.BIN"
|
||||
|
||||
/* IAP Status Definitions */
|
||||
#define DEF_IAP_SUCCESS 0x00 /* IAP Operation Success */
|
||||
#define DEF_IAP_DEFAULT 0xFF /* IAP Operation Default Status */
|
||||
#define DEF_IAP_ERR_DETECT 0xF1 /* IAP Operation, USB device not detected */
|
||||
#define DEF_IAP_ERR_ENUM 0xF2 /* IAP Operation, Host enumeration failure */
|
||||
#define DEF_IAP_ERR_FILE 0xF3 /* IAP Operation, File name incorrect or no such file */
|
||||
#define DEF_IAP_ERR_FLASH 0xF4 /* IAP Operation, Flash operation failure */
|
||||
#define DEF_IAP_ERR_VERIFY 0xF5 /* IAP Operation, Flash data verify error */
|
||||
#define DEF_IAP_ERR_LENGTH 0xF6 /* IAP Operation, Flash data length verify error */
|
||||
|
||||
/* IAP Load buffer Definitions */
|
||||
#define DEF_MAX_IAP_BUFFER_LEN 1024 /* IAP Load buffer size */
|
||||
|
||||
/* Flash page size */
|
||||
#define DEF_FLASH_PAGE_SIZE 0x100 /* Flash Page size, refer to the data-sheet (ch32vf2x_3xRM.pdf) for details */
|
||||
|
||||
/* APP CODE ADDR Setting */
|
||||
#define DEF_APP_CODE_START_ADDR 0x08005000 /* IAP Flash Operation start address, user code start address */
|
||||
#ifdef CH32V20x_D6
|
||||
#define DEF_APP_CODE_END_ADDR 0x08010000 /* IAP Flash Operation end address, user code end address */
|
||||
/* Please refer to link.ld file for accuracy flash size, the size here is the smallest available size */
|
||||
/* CH32V203C8/G8/F8 - 0x08010000 (64K), CH32F203C6 - 0x08008000 (32K) */
|
||||
#else
|
||||
#define DEF_APP_CODE_END_ADDR 0x08020000 /* IAP Flash Operation end address, user code end address */
|
||||
/* Please refer to link.ld file for accuracy flash size, the size here is the smallest available size */
|
||||
/* CH32V203RB/208x - 0x08020000 (128K) */
|
||||
#endif
|
||||
#define DEF_APP_CODE_MAXLEN (DEF_APP_CODE_END_ADDR-DEF_APP_CODE_START_ADDR) /* IAP Flash Operation size, user code max size */
|
||||
|
||||
/* Verify CODE ADDR Setting */
|
||||
#define DEF_VERIFY_CODE_START_ADDR 0x08004F00 /* IAP Flash verify-code start address */
|
||||
#define DEF_VERIFY_CODE_END_ADDR 0x08005000 /* IAP Flash verify-code end address */
|
||||
#define DEF_VERIFY_CODE_MAXLEN (DEF_VERIFY_CODE_END_ADDR-DEF_VERIFY_CODE_START_ADDR) /* IAP Flash verify-code max size */
|
||||
#define DEF_VERIFY_CODE_LEN 0x10 /* IAP Flash verify-code actual length, be careful not to exceed the DEF_VERIFY_CODE_MAXLEN */
|
||||
|
||||
/* Flash Operation Key Setting */
|
||||
#define DEF_FLASH_OPERATION_KEY_CODE_0 0x1A86FF00 /* IAP Flash operation Key-code 0 */
|
||||
#define DEF_FLASH_OPERATION_KEY_CODE_1 0x55AA55AA /* IAP Flash operation Key-code 1 */
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Variable Extrapolation */
|
||||
/* Flash Operation Key Variables, Operation with DEF_FLASH_OPERATION_KEY_CODE_x to ensure the correctness of flash operation*/
|
||||
extern volatile uint32_t Flash_Operation_Key0; /* IAP Flash operation Key-code Variables 0 */
|
||||
extern volatile uint32_t Flash_Operation_Key1; /* IAP Flash operation Key-code Variables 1 */
|
||||
extern __attribute__((aligned(4))) uint8_t USBHD_TX_Buf[ MAX_PACKET_SIZE ] ; // IN, must even address
|
||||
extern __attribute__((aligned(4))) uint8_t USBHD_RX_Buf[ MAX_PACKET_SIZE ] ; // OUT, must even address
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Data Structures */
|
||||
#if DEF_CORE_TYPE == DEF_CORE_CM3
|
||||
typedef void (*iapfun)(void); //Define a function type parameter.
|
||||
#endif
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Function Extrapolation */
|
||||
/* Lower operation */
|
||||
extern uint8_t FLASH_ReadByte( uint32_t address );
|
||||
extern uint16_t FLASH_ReadHalfWord( uint32_t address );
|
||||
extern uint32_t FLASH_ReadWord( uint32_t address );
|
||||
extern uint8_t IAP_Flash_Erase( uint32_t address, uint32_t length );
|
||||
extern uint8_t IAP_Flash_Read( uint32_t address, uint8_t *buff, uint32_t length );
|
||||
extern uint8_t IAP_Flash_Write( uint32_t address, uint8_t *buff, uint32_t length );
|
||||
extern uint32_t IAP_Flash_Verify( uint32_t address, uint8_t *buff, uint32_t length );
|
||||
extern uint32_t IAP_Flash_Program( uint32_t address, uint8_t *buff, uint32_t length );
|
||||
extern uint8_t IAP_VerifyCode_Erase( void );
|
||||
extern uint32_t IAP_VerifyCode_Write( void );
|
||||
extern uint32_t IAP_VerifyCode_Check( void );
|
||||
extern void IAP_Jump_APP( void );
|
||||
extern void FLASH_ReadWordAdd(uint32_t address, u32 *buff, uint16_t length);
|
||||
|
||||
/* upper operation */
|
||||
extern void IAP_Main_Deal( void );
|
||||
extern void IAP_Initialization( void );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,655 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32f20x_usbfs_host.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/09/01
|
||||
* Description : USB full-speed port host operation functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Header File */
|
||||
#include "usb_host_config.h"
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Variable Definition */
|
||||
__attribute__((aligned(4))) uint8_t RxBuffer[ MAX_PACKET_SIZE ]; // IN, must even address
|
||||
__attribute__((aligned(4))) uint8_t TxBuffer[ MAX_PACKET_SIZE ]; // OUT, must even address
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFS_RCC_Init
|
||||
*
|
||||
* @brief Set USB port clock.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USBFS_RCC_Init( void )
|
||||
{
|
||||
if( SystemCoreClock == 144000000 )
|
||||
{
|
||||
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
|
||||
}
|
||||
else if( SystemCoreClock == 96000000 )
|
||||
{
|
||||
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
|
||||
}
|
||||
else if( SystemCoreClock == 48000000 )
|
||||
{
|
||||
RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
|
||||
}
|
||||
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE );
|
||||
}
|
||||
/*********************************************************************
|
||||
* @fn USBFS_Host_Init
|
||||
*
|
||||
* @brief Initialize USB port host configuration.
|
||||
*
|
||||
* @param sta - ENABLE or DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USBFS_Host_Init( FunctionalState sta )
|
||||
{
|
||||
if( sta == ENABLE )
|
||||
{
|
||||
USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE;
|
||||
USBOTG_H_FS->HOST_CTRL = 0;
|
||||
USBOTG_H_FS->DEV_ADDR = 0;
|
||||
USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN;
|
||||
|
||||
USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf;
|
||||
USBOTG_H_FS->HOST_TX_DMA = (uint32_t)USBFS_TX_Buf;
|
||||
|
||||
USBOTG_H_FS->HOST_RX_CTRL = 0;
|
||||
USBOTG_H_FS->HOST_TX_CTRL = 0;
|
||||
USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
|
||||
|
||||
USBOTG_H_FS->INT_FG = 0xFF;
|
||||
|
||||
USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT;
|
||||
}
|
||||
else
|
||||
{
|
||||
USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_CheckRootHubPortStatus
|
||||
*
|
||||
* @brief Check status of USB port.
|
||||
*
|
||||
* @para dev_sta: The status of the root device connected to this port.
|
||||
*
|
||||
* @return The current status of the port.
|
||||
*/
|
||||
uint8_t USBFSH_CheckRootHubPortStatus( uint8_t dev_sta )
|
||||
{
|
||||
/* Check USB device connection or disconnection */
|
||||
if( ( USBOTG_H_FS->INT_FG ) & USBFS_UIF_DETECT )
|
||||
{
|
||||
USBOTG_H_FS->INT_FG = USBFS_UIF_DETECT; // Clear flag
|
||||
if( USBOTG_H_FS->MIS_ST & USBFS_UMS_DEV_ATTACH ) // Check that the USB device has been connected to the port
|
||||
{
|
||||
if( ( dev_sta == ROOT_DEV_DISCONNECT ) || ( ( dev_sta != ROOT_DEV_FAILED ) && ( USBFSH_CheckRootHubPortEnable( ) == 0x00 ) ) )
|
||||
{
|
||||
return ROOT_DEV_CONNECTED;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ROOT_DEV_FAILED;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return ROOT_DEV_DISCONNECT;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return ROOT_DEV_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_CheckRootHubPortEnable
|
||||
*
|
||||
* @brief Check the enable status of the USB port.
|
||||
*
|
||||
* @return The current enable status of the port.
|
||||
*/
|
||||
uint8_t USBFSH_CheckRootHubPortEnable( void )
|
||||
{
|
||||
return ( USBOTG_H_FS->HOST_CTRL & USBFS_UH_PORT_EN );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_CheckRootHubPortSpeed
|
||||
*
|
||||
* @brief Check the speed of the USB port.
|
||||
*
|
||||
* @return The current speed of the port.
|
||||
*/
|
||||
uint8_t USBFSH_CheckRootHubPortSpeed( void )
|
||||
{
|
||||
return ( USBOTG_H_FS->MIS_ST & USBFS_UMS_DM_LEVEL? USB_LOW_SPEED: USB_FULL_SPEED );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_SetSelfAddr
|
||||
*
|
||||
* @brief Set the USB device address.
|
||||
*
|
||||
* @para addr: USB device address.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USBFSH_SetSelfAddr( uint8_t addr )
|
||||
{
|
||||
USBOTG_H_FS->DEV_ADDR = ( USBOTG_H_FS->DEV_ADDR & USBFS_UDA_GP_BIT ) | ( addr & USBFS_USB_ADDR_MASK );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_SetSelfSpeed
|
||||
*
|
||||
* @brief Set USB speed.
|
||||
*
|
||||
* @para speed: USB speed.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USBFSH_SetSelfSpeed( uint8_t speed )
|
||||
{
|
||||
if( speed )
|
||||
{
|
||||
USBOTG_H_FS->BASE_CTRL &= ~USBFS_UC_LOW_SPEED;
|
||||
USBOTG_H_FS->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
USBOTG_H_FS->BASE_CTRL |= USBFS_UC_LOW_SPEED;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_ResetRootHubPort
|
||||
*
|
||||
* @brief Reset USB port.
|
||||
*
|
||||
* @para mod: Reset host port operating mode.
|
||||
* 0 -> reset and wait end
|
||||
* 1 -> begin reset
|
||||
* 2 -> end reset
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USBFSH_ResetRootHubPort( uint8_t mode )
|
||||
{
|
||||
USBFSH_SetSelfAddr( 0x00 );
|
||||
USBFSH_SetSelfSpeed( 1 );
|
||||
if( mode <= 1 )
|
||||
{
|
||||
USBOTG_H_FS->HOST_CTRL = ( USBOTG_H_FS->HOST_CTRL & ~USBFS_UH_LOW_SPEED ) | USBFS_UH_BUS_RESET;
|
||||
}
|
||||
if( mode == 0 )
|
||||
{
|
||||
Delay_Ms( DEF_BUS_RESET_TIME ); // Reset time from 10mS to 20mS
|
||||
}
|
||||
if( mode != 1 )
|
||||
{
|
||||
USBOTG_H_FS->HOST_CTRL = USBOTG_H_FS->HOST_CTRL & ~USBFS_UH_BUS_RESET; // End Reset
|
||||
}
|
||||
Delay_Ms( 2 );
|
||||
USBOTG_H_FS->INT_FG = USBFS_UIF_DETECT;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_EnableRootHubPort
|
||||
*
|
||||
* @brief Enable USB host port.
|
||||
*
|
||||
* @para *pspeed: USB speed.
|
||||
*
|
||||
* @return Operation result of the enabled port.
|
||||
*/
|
||||
uint8_t USBFSH_EnableRootHubPort( uint8_t *pspeed )
|
||||
{
|
||||
if( USBOTG_H_FS->MIS_ST & USBFS_UMS_DEV_ATTACH )
|
||||
{
|
||||
if( USBFSH_CheckRootHubPortEnable( ) == 0x00 )
|
||||
{
|
||||
*pspeed = USBFSH_CheckRootHubPortSpeed( );
|
||||
if( *pspeed == 0 )
|
||||
{
|
||||
USBOTG_H_FS->HOST_CTRL |= USBFS_UH_LOW_SPEED;
|
||||
}
|
||||
}
|
||||
USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN;
|
||||
USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN;
|
||||
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
return ERR_USB_DISCON;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_Transact
|
||||
*
|
||||
* @brief Perform USB transaction.
|
||||
*
|
||||
* @para endp_pid: Token PID.
|
||||
* endp_tog: Toggle
|
||||
* timeout: Timeout time.
|
||||
*
|
||||
* @return USB transfer result.
|
||||
*/
|
||||
uint8_t USBFSH_Transact( uint8_t endp_pid, uint8_t endp_tog, uint16_t timeout )
|
||||
{
|
||||
uint8_t r, trans_rerty;
|
||||
uint16_t i;
|
||||
|
||||
USBOTG_H_FS->HOST_TX_CTRL = USBOTG_H_FS->HOST_RX_CTRL = endp_tog;
|
||||
trans_rerty = 0;
|
||||
do
|
||||
{
|
||||
USBOTG_H_FS->HOST_EP_PID = endp_pid; // Specify token PID and endpoint number
|
||||
USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; // Allow transmission
|
||||
for( i = DEF_WAIT_USB_TOUT_200US; ( i != 0 ) && ( ( USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER ) == 0 ); i-- )
|
||||
{
|
||||
Delay_Us( 1 );
|
||||
}
|
||||
USBOTG_H_FS->HOST_EP_PID = 0x00; // Stop USB transfer
|
||||
if( ( USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER ) == 0 )
|
||||
{
|
||||
return ERR_USB_UNKNOWN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Complete transfer */
|
||||
if( USBOTG_H_FS->INT_ST & USBFS_UIS_TOG_OK )
|
||||
{
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
r = USBOTG_H_FS->INT_ST & USBFS_UIS_H_RES_MASK; // USB device answer status
|
||||
if( r == USB_PID_STALL )
|
||||
{
|
||||
return ( r | ERR_USB_TRANSFER );
|
||||
}
|
||||
if( r == USB_PID_NAK )
|
||||
{
|
||||
if( timeout == 0 )
|
||||
{
|
||||
return ( r | ERR_USB_TRANSFER );
|
||||
}
|
||||
if( timeout < 0xFFFF )
|
||||
{
|
||||
timeout--;
|
||||
}
|
||||
--trans_rerty;
|
||||
}
|
||||
else switch ( endp_pid >> 4 )
|
||||
{
|
||||
case USB_PID_SETUP:
|
||||
case USB_PID_OUT:
|
||||
if( r )
|
||||
{
|
||||
return ( r | ERR_USB_TRANSFER );
|
||||
}
|
||||
break;
|
||||
case USB_PID_IN:
|
||||
if( ( r == USB_PID_DATA0 ) && ( r == USB_PID_DATA1 ) )
|
||||
{
|
||||
;
|
||||
}
|
||||
else if( r )
|
||||
{
|
||||
return ( r | ERR_USB_TRANSFER );
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return ERR_USB_UNKNOWN;
|
||||
}
|
||||
}
|
||||
Delay_Us( 15 );
|
||||
if( USBOTG_H_FS->INT_FG & USBFS_UIF_DETECT )
|
||||
{
|
||||
Delay_Us( 200 );
|
||||
if( USBFSH_CheckRootHubPortEnable( ) == 0 )
|
||||
{
|
||||
return ERR_USB_DISCON; // USB device disconnect event
|
||||
}
|
||||
}
|
||||
}while( ++trans_rerty < 10 );
|
||||
|
||||
return ERR_USB_TRANSFER; // Reply timeout
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_CtrlTransfer
|
||||
*
|
||||
* @brief USB host control transfer.
|
||||
*
|
||||
* @para ep0_size: Device endpoint 0 size
|
||||
* pbuf: Data buffer
|
||||
* plen: Data length
|
||||
*
|
||||
* @return USB control transfer result.
|
||||
*/
|
||||
uint8_t USBFSH_CtrlTransfer( uint8_t ep0_size, uint8_t *pbuf, uint16_t *plen )
|
||||
{
|
||||
uint8_t s;
|
||||
uint16_t rem_len, rx_len, rx_cnt, tx_cnt;
|
||||
|
||||
if( plen )
|
||||
{
|
||||
*plen = 0;
|
||||
}
|
||||
USBOTG_H_FS->HOST_TX_LEN = sizeof( USB_SETUP_REQ );
|
||||
s = USBFSH_Transact( USB_PID_SETUP << 4 | 0x00, 0x00, DEF_CTRL_TRANS_TIMEOVER_CNT ); // SETUP stage, 200mS timeout
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
USBOTG_H_FS->HOST_TX_CTRL = USBOTG_H_FS->HOST_RX_CTRL = USBFS_UH_T_TOG | USBFS_UH_R_TOG | USBFS_UH_T_AUTO_TOG | USBFS_UH_R_AUTO_TOG; // Default DATA1
|
||||
USBOTG_H_FS->HOST_TX_LEN = 0x01; // The default no-data state stage is IN
|
||||
rem_len = pUSBFS_SetupRequest->wLength;
|
||||
if( rem_len && pbuf )
|
||||
{
|
||||
if( pUSBFS_SetupRequest->bRequestType & USB_REQ_TYP_IN )
|
||||
{
|
||||
/* Receive data */
|
||||
while( rem_len )
|
||||
{
|
||||
Delay_Us( 100 );
|
||||
s = USBFSH_Transact( USB_PID_IN << 4 | 0x00, USBOTG_H_FS->HOST_RX_CTRL, DEF_CTRL_TRANS_TIMEOVER_CNT ); // IN
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
rx_len = ( USBOTG_H_FS->RX_LEN < rem_len )? USBOTG_H_FS->RX_LEN : rem_len;
|
||||
rem_len -= rx_len;
|
||||
if( plen )
|
||||
{
|
||||
*plen += rx_len; // The total length of the actual successful transmission and reception
|
||||
}
|
||||
for( rx_cnt = 0; rx_cnt != rx_len; rx_cnt++ )
|
||||
{
|
||||
*pbuf = USBFS_RX_Buf[ rx_cnt ];
|
||||
pbuf++;
|
||||
}
|
||||
|
||||
if( ( USBOTG_H_FS->RX_LEN == 0 ) || ( USBOTG_H_FS->RX_LEN & ( ep0_size - 1 ) ) )
|
||||
{
|
||||
break; // Short package
|
||||
}
|
||||
}
|
||||
USBOTG_H_FS->HOST_TX_LEN = 0x00; // Status stage is OUT
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Send data */
|
||||
while( rem_len )
|
||||
{
|
||||
Delay_Us( 100 );
|
||||
USBOTG_H_FS->HOST_TX_LEN = ( rem_len >= ep0_size )? ep0_size : rem_len;
|
||||
for( tx_cnt = 0; tx_cnt != USBOTG_H_FS->HOST_TX_LEN; tx_cnt++ )
|
||||
{
|
||||
USBFS_TX_Buf[ tx_cnt ] = *pbuf;
|
||||
pbuf++;
|
||||
}
|
||||
s = USBFSH_Transact( USB_PID_OUT << 4 | 0x00, USBOTG_H_FS->HOST_TX_CTRL, DEF_CTRL_TRANS_TIMEOVER_CNT ); // OUT
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
rem_len -= USBOTG_H_FS->HOST_TX_LEN;
|
||||
if( plen )
|
||||
{
|
||||
*plen += USBOTG_H_FS->HOST_TX_LEN; // The total length of the actual successful transmission and reception
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Delay_Us( 100 );
|
||||
s = USBFSH_Transact( ( USBOTG_H_FS->HOST_TX_LEN )? ( USB_PID_IN << 4 | 0x00 ) : ( USB_PID_OUT << 4 | 0x00 ), USBFS_UH_R_TOG | USBFS_UH_T_TOG, DEF_CTRL_TRANS_TIMEOVER_CNT ); /* STATUS½×¶Î */
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
if( USBOTG_H_FS->HOST_TX_LEN == 0 )
|
||||
{
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
if( USBOTG_H_FS->RX_LEN == 0 )
|
||||
{
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
return ERR_USB_BUF_OVER;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_GetDeviceDescr
|
||||
*
|
||||
* @brief Get the device descriptor of the USB device.
|
||||
*
|
||||
* @para pep0_size: Device endpoint 0 size
|
||||
* pbuf: Data buffer
|
||||
*
|
||||
* @return The result of getting the device descriptor.
|
||||
*/
|
||||
uint8_t USBFSH_GetDeviceDescr( uint8_t *pep0_size, uint8_t *pbuf )
|
||||
{
|
||||
uint8_t s;
|
||||
uint16_t len;
|
||||
|
||||
*pep0_size = DEFAULT_ENDP0_SIZE;
|
||||
memcpy( pUSBFS_SetupRequest, SetupGetDevDesc, sizeof( USB_SETUP_REQ ) );
|
||||
s = USBFSH_CtrlTransfer( *pep0_size, pbuf, &len );
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
|
||||
*pep0_size = ( (PUSB_DEV_DESCR)pbuf )->bMaxPacketSize0;
|
||||
if( len < ( (PUSB_SETUP_REQ)SetupGetDevDesc )->wLength )
|
||||
{
|
||||
return ERR_USB_BUF_OVER;
|
||||
}
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_GetConfigDescr
|
||||
*
|
||||
* @brief Get the configuration descriptor of the USB device.
|
||||
*
|
||||
* @para ep0_size: Device endpoint 0 size
|
||||
* pbuf: Data buffer
|
||||
* buf_len: Data buffer length
|
||||
* pcfg_len: The length of the device configuration descriptor
|
||||
*
|
||||
* @return The result of getting the configuration descriptor.
|
||||
*/
|
||||
uint8_t USBFSH_GetConfigDescr( uint8_t ep0_size, uint8_t *pbuf, uint16_t buf_len, uint16_t *pcfg_len )
|
||||
{
|
||||
uint8_t s;
|
||||
|
||||
memcpy( pUSBFS_SetupRequest, SetupGetCfgDesc, sizeof( USB_SETUP_REQ ) );
|
||||
s = USBFSH_CtrlTransfer( ep0_size, pbuf, pcfg_len );
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
if( *pcfg_len < ( (PUSB_SETUP_REQ)SetupGetCfgDesc )->wLength )
|
||||
{
|
||||
return ERR_USB_BUF_OVER;
|
||||
}
|
||||
|
||||
*pcfg_len = ( (PUSB_CFG_DESCR)pbuf )->wTotalLength;
|
||||
if( *pcfg_len > buf_len )
|
||||
{
|
||||
*pcfg_len = buf_len;
|
||||
}
|
||||
memcpy( pUSBFS_SetupRequest, SetupGetCfgDesc, sizeof( USB_SETUP_REQ ) );
|
||||
pUSBFS_SetupRequest->wLength = *pcfg_len;
|
||||
s = USBFSH_CtrlTransfer( ep0_size, pbuf, pcfg_len );
|
||||
return s;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_GetStrDescr
|
||||
*
|
||||
* @brief Get the string descriptor of the USB device.
|
||||
*
|
||||
* @para ep0_size: Device endpoint 0 size
|
||||
* str_num: Index of string descriptor
|
||||
* pbuf: Data buffer
|
||||
*
|
||||
* @return The result of getting the string descriptor.
|
||||
*/
|
||||
uint8_t USBFSH_GetStrDescr( uint8_t ep0_size, uint8_t str_num, uint8_t *pbuf )
|
||||
{
|
||||
uint8_t s;
|
||||
uint16_t len;
|
||||
|
||||
/* Get the string descriptor of the first 4 bytes */
|
||||
memcpy( pUSBFS_SetupRequest, SetupGetStrDesc, sizeof( USB_SETUP_REQ ) );
|
||||
pUSBFS_SetupRequest->wValue = ( (uint16_t)USB_DESCR_TYP_STRING << 8 ) | str_num;
|
||||
s = USBFSH_CtrlTransfer( ep0_size, pbuf, &len );
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
|
||||
/* Get the complete string descriptor */
|
||||
len = pbuf[ 0 ];
|
||||
memcpy( pUSBFS_SetupRequest, SetupGetStrDesc, sizeof( USB_SETUP_REQ ) );
|
||||
pUSBFS_SetupRequest->wValue = ( (uint16_t)USB_DESCR_TYP_STRING << 8 ) | str_num;
|
||||
pUSBFS_SetupRequest->wLength = len;
|
||||
s = USBFSH_CtrlTransfer( ep0_size, pbuf, &len );
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_SetUsbAddress
|
||||
*
|
||||
* @brief Set USB device address.
|
||||
*
|
||||
* @para ep0_size: Device endpoint 0 size
|
||||
* addr: Device address
|
||||
*
|
||||
* @return The result of setting device address.
|
||||
*/
|
||||
uint8_t USBFSH_SetUsbAddress( uint8_t ep0_size, uint8_t addr )
|
||||
{
|
||||
uint8_t s;
|
||||
|
||||
memcpy( pUSBFS_SetupRequest, SetupSetAddr, sizeof( USB_SETUP_REQ ) );
|
||||
pUSBFS_SetupRequest->wValue = (uint16_t)addr;
|
||||
s = USBFSH_CtrlTransfer( ep0_size, NULL, NULL );
|
||||
if( s != ERR_SUCCESS )
|
||||
{
|
||||
return s;
|
||||
}
|
||||
USBFSH_SetSelfAddr( addr );
|
||||
Delay_Ms( DEF_BUS_RESET_TIME >> 1 ); // Wait for the USB device to complete its operation.
|
||||
return ERR_SUCCESS;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_SetUsbConfig
|
||||
*
|
||||
* @brief Set USB configuration.
|
||||
*
|
||||
* @para ep0_size: Device endpoint 0 size
|
||||
* cfg: Device configuration value
|
||||
*
|
||||
* @return The result of setting device configuration.
|
||||
*/
|
||||
uint8_t USBFSH_SetUsbConfig( uint8_t ep0_size, uint8_t cfg_val )
|
||||
{
|
||||
memcpy( pUSBFS_SetupRequest, SetupSetConfig, sizeof( USB_SETUP_REQ ) );
|
||||
pUSBFS_SetupRequest->wValue = (uint16_t)cfg_val;
|
||||
return USBFSH_CtrlTransfer( ep0_size, NULL, NULL );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_ClearEndpStall
|
||||
*
|
||||
* @brief Clear endpoint stall.
|
||||
*
|
||||
* @para ep0_size: Device endpoint 0 size
|
||||
* endp_num: Endpoint number.
|
||||
*
|
||||
* @return The result of clearing endpoint stall.
|
||||
*/
|
||||
uint8_t USBFSH_ClearEndpStall( uint8_t ep0_size, uint8_t endp_num )
|
||||
{
|
||||
memcpy( pUSBFS_SetupRequest, SetupClearEndpStall, sizeof( USB_SETUP_REQ ) );
|
||||
pUSBFS_SetupRequest->wIndex = (uint16_t)endp_num;
|
||||
return USBFSH_CtrlTransfer( ep0_size, NULL, NULL );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_GetEndpData
|
||||
*
|
||||
* @brief Get data from USB device input endpoint.
|
||||
*
|
||||
* @para endp_num: Endpoint number
|
||||
* pendp_tog: Endpoint toggle
|
||||
* pbuf: Data Buffer
|
||||
* plen: Data length
|
||||
*
|
||||
* @return The result of getting data.
|
||||
*/
|
||||
uint8_t USBFSH_GetEndpData( uint8_t endp_num, uint8_t *pendp_tog, uint8_t *pbuf, uint16_t *plen )
|
||||
{
|
||||
uint8_t s;
|
||||
|
||||
s = USBFSH_Transact( ( USB_PID_IN << 4 ) | endp_num, *pendp_tog, 0 );
|
||||
if( s == ERR_SUCCESS )
|
||||
{
|
||||
*pendp_tog ^= USBFS_UH_T_TOG | USBFS_UH_R_TOG;
|
||||
*plen = USBOTG_H_FS->RX_LEN;
|
||||
memcpy( pbuf, USBFS_RX_Buf, *plen );
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USBFSH_SendEndpData
|
||||
*
|
||||
* @brief Send data to the USB device output endpoint.
|
||||
*
|
||||
* @para endp_num: Endpoint number
|
||||
* pendp_tog: Endpoint toggle
|
||||
* pbuf: Data Buffer
|
||||
* plen: Data length
|
||||
*
|
||||
* @return The result of sending data.
|
||||
*/
|
||||
uint8_t USBFSH_SendEndpData( uint8_t endp_num, uint8_t *pendp_tog, uint8_t *pbuf, uint16_t len )
|
||||
{
|
||||
uint8_t s;
|
||||
|
||||
memcpy( USBFS_TX_Buf, pbuf, len );
|
||||
USBOTG_H_FS->HOST_TX_LEN = len;
|
||||
|
||||
s = USBFSH_Transact( ( USB_PID_OUT << 4 ) | endp_num, *pendp_tog, 0 );
|
||||
if( s == ERR_SUCCESS )
|
||||
{
|
||||
*pendp_tog ^= USBFS_UH_T_TOG | USBFS_UH_R_TOG;
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
@@ -0,0 +1,103 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_usbfs_host.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : USBOTG full speed host header file
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __CH32V20x_USBFS_HOST_H__
|
||||
#define __CH32V20x_USBFS_HOST_H__
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Header File */
|
||||
#include "ch32v20x.h"
|
||||
#include "ch32v20x_usb.h"
|
||||
|
||||
/*******************************************************************************/
|
||||
/* USB Setup Request Macro Definition */
|
||||
#define pUSBFS_SetupRequest ( (PUSB_SETUP_REQ)USBFS_TX_Buf )
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Constant Definition */
|
||||
#ifndef DEF_GET_USB_DEV_DESC
|
||||
#define DEF_GET_USB_DEV_DESC
|
||||
/* Get Device Descriptor Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupGetDevDesc[ ] =
|
||||
{
|
||||
USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof( USB_DEV_DESCR ), 0x00
|
||||
};
|
||||
|
||||
/* Get Configuration Descriptor Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupGetCfgDesc[ ] =
|
||||
{
|
||||
USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00
|
||||
};
|
||||
|
||||
/* Get String Descriptor Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupGetStrDesc[ ] =
|
||||
{
|
||||
USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_STRING, 0x09, 0x04, 0x04, 0x00
|
||||
};
|
||||
|
||||
/* Set USB Address Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupSetAddr[ ] =
|
||||
{
|
||||
USB_REQ_TYP_OUT, USB_SET_ADDRESS, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Set USB Configuration Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupSetConfig[ ] =
|
||||
{
|
||||
USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Clear Endpoint STALL Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupClearEndpStall[ ] =
|
||||
{
|
||||
USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Set Device Interface Command Packet */
|
||||
__attribute__((aligned(4))) static const uint8_t SetupSetInterface[ ] =
|
||||
{
|
||||
USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
#endif
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Variable Declaration */
|
||||
extern __attribute__((aligned(4))) uint8_t RxBuffer[ ]; // IN, must even address
|
||||
extern __attribute__((aligned(4))) uint8_t TxBuffer[ ]; // OUT, must even address
|
||||
#define USBFS_RX_Buf RxBuffer
|
||||
#define USBFS_TX_Buf TxBuffer
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Function Declaration */
|
||||
extern void USBFS_RCC_Init( void );
|
||||
extern void USBFS_Host_Init( FunctionalState sta );
|
||||
extern uint8_t USBFSH_CheckRootHubPortStatus( uint8_t dev_sta );
|
||||
extern uint8_t USBFSH_CheckRootHubPortEnable( void );
|
||||
extern uint8_t USBFSH_CheckRootHubPortSpeed( void );
|
||||
extern void USBFSH_SetSelfAddr( uint8_t addr );
|
||||
extern void USBFSH_SetSelfSpeed( uint8_t speed );
|
||||
extern void USBFSH_ResetRootHubPort( uint8_t mode );
|
||||
extern uint8_t USBFSH_EnableRootHubPort( uint8_t *pspeed );
|
||||
extern uint8_t USBFSH_Transact( uint8_t endp_pid, uint8_t endp_tog, uint16_t timeout );
|
||||
extern uint8_t USBFSH_CtrlTransfer( uint8_t ep0_size, uint8_t *pbuf, uint16_t *plen );
|
||||
extern uint8_t USBFSH_GetDeviceDescr( uint8_t *pep0_size, uint8_t *pbuf );
|
||||
extern uint8_t USBFSH_GetConfigDescr( uint8_t ep0_size, uint8_t *pbuf, uint16_t buf_len, uint16_t *pcfg_len );
|
||||
extern uint8_t USBFSH_GetStrDescr( uint8_t ep0_size, uint8_t str_num, uint8_t *pbuf );
|
||||
extern uint8_t USBFSH_SetUsbAddress( uint8_t ep0_size, uint8_t addr );
|
||||
extern uint8_t USBFSH_SetUsbConfig( uint8_t ep0_size, uint8_t cfg_val );
|
||||
extern uint8_t USBFSH_ClearEndpStall( uint8_t ep0_size, uint8_t endp_num );
|
||||
extern uint8_t USBFSH_GetEndpData( uint8_t endp_num, uint8_t *pendp_tog, uint8_t *pbuf, uint16_t *plen );
|
||||
extern uint8_t USBFSH_SendEndpData( uint8_t endp_num, uint8_t *pendp_tog, uint8_t *pbuf, uint16_t len );
|
||||
extern uint8_t USBFSH_PortDetect( uint8_t status );
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,169 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : usb_host_config.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/29
|
||||
* Description :
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __USB_HOST_CONFIG_H
|
||||
#define __USB_HOST_CONFIG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* Header File */
|
||||
#include "string.h"
|
||||
#include "debug.h"
|
||||
#include "ch32v20x_usb.h"
|
||||
#include "ch32v20x_usbfs_host.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/* USB Host Communication Related Macro Definition */
|
||||
|
||||
/* USB Host Port General Control */
|
||||
#define DEF_TOTAL_ROOT_HUB 1
|
||||
#define DEF_USB_PORT_FS_EN 1
|
||||
#define DEF_USB_PORT_FS 0x00
|
||||
|
||||
/* USB Root Device Status */
|
||||
#define ROOT_DEV_DISCONNECT 0
|
||||
#define ROOT_DEV_CONNECTED 1
|
||||
#define ROOT_DEV_FAILED 2
|
||||
#define ROOT_DEV_SUCCESS 3
|
||||
|
||||
/* USB Device Address */
|
||||
#define USB_DEVICE_ADDR 0x02
|
||||
|
||||
/* USB Speed */
|
||||
#define USB_LOW_SPEED 0x00
|
||||
#define USB_FULL_SPEED 0x01
|
||||
#define USB_HIGH_SPEED 0x02
|
||||
#define USB_SPEED_CHECK_ERR 0xFF
|
||||
|
||||
/* Configuration Descriptor Type */
|
||||
#define DEF_DECR_CONFIG 0x02
|
||||
#define DEF_DECR_INTERFACE 0x04
|
||||
#define DEF_DECR_ENDPOINT 0x05
|
||||
#define DEF_DECR_HID 0x21
|
||||
|
||||
/* USB Communication Status Code */
|
||||
#define ERR_SUCCESS 0x00
|
||||
#define ERR_USB_CONNECT 0x15
|
||||
#define ERR_USB_DISCON 0x16
|
||||
#define ERR_USB_BUF_OVER 0x17
|
||||
#define ERR_USB_DISK_ERR 0x1F
|
||||
#define ERR_USB_TRANSFER 0x20
|
||||
#define ERR_USB_UNSUPPORT 0xFB
|
||||
#define ERR_USB_UNAVAILABLE 0xFC
|
||||
#define ERR_USB_UNKNOWN 0xFE
|
||||
|
||||
/* USB Device Enumeration Status Code */
|
||||
#define DEF_DEV_DESCR_GETFAIL 0x45
|
||||
#define DEF_DEV_ADDR_SETFAIL 0x46
|
||||
#define DEF_CFG_DESCR_GETFAIL 0x47
|
||||
#define DEF_REP_DESCR_GETFAIL 0x48
|
||||
#define DEF_DEV_TYPE_UNKNOWN 0xFF
|
||||
|
||||
/* USB Communication Time */
|
||||
#define DEF_BUS_RESET_TIME 11 // USB bus reset time
|
||||
#define DEF_RE_ATTACH_TIMEOUT 100 // Wait for the USB device to reconnect after reset, 100mS timeout
|
||||
#define DEF_WAIT_USB_TOUT_200US 1000
|
||||
#define DEF_CTRL_TRANS_TIMEOVER_CNT 60000 // Control transmission delay timing
|
||||
|
||||
/* General */
|
||||
#define DEF_ONE_USB_SUP_DEV_TOTAL 1
|
||||
#define DEF_NEXT_HUB_PORT_NUM_MAX 4
|
||||
#define DEF_INTERFACE_NUM_MAX 4
|
||||
#define DEF_COM_BUF_LEN 255
|
||||
|
||||
/* Debug */
|
||||
#define DEF_DEBUG_PRINTF 1
|
||||
#if ( DEF_DEBUG_PRINTF == 1 )
|
||||
#define DUG_PRINTF( format, arg... ) printf( format, ##arg )
|
||||
#else
|
||||
#define DUG_PRINTF( format, arg... ) do{ if( 0 )printf( format, ##arg ); }while( 0 );
|
||||
#endif
|
||||
|
||||
/* HUB Port Device */
|
||||
typedef struct _HUB_DEVICE
|
||||
{
|
||||
uint8_t bStatus;
|
||||
uint8_t bType;
|
||||
uint8_t bAddress;
|
||||
uint8_t bSpeed;
|
||||
uint8_t bEp0MaxPks;
|
||||
uint8_t DeviceIndex;
|
||||
}HUB_DEVICE, *PHUB_DEVICE;
|
||||
|
||||
/* Root HUB Device Structure, Physical Interface */
|
||||
typedef struct _ROOT_HUB_DEVICE
|
||||
{
|
||||
uint8_t bStatus;
|
||||
uint8_t bType;
|
||||
uint8_t bAddress;
|
||||
uint8_t bSpeed;
|
||||
uint8_t bEp0MaxPks;
|
||||
uint8_t DeviceIndex;
|
||||
uint8_t bPortNum;
|
||||
HUB_DEVICE Device[ DEF_NEXT_HUB_PORT_NUM_MAX ];
|
||||
} ROOT_HUB_DEVICE, *PROOT_HUB_DEVICE;
|
||||
|
||||
/* USB Host Control Structure */
|
||||
struct __HOST_CTL
|
||||
{
|
||||
uint8_t InterfaceNum;
|
||||
uint8_t ErrorCount;
|
||||
|
||||
struct interface
|
||||
{
|
||||
uint8_t Type;
|
||||
uint16_t HidDescLen;
|
||||
uint8_t HidReportID;
|
||||
uint8_t Full_KB_Flag;
|
||||
|
||||
uint8_t InEndpNum;
|
||||
uint8_t InEndpAddr[ 4 ];
|
||||
uint8_t InEndpType[ 4 ];
|
||||
uint16_t InEndpSize[ 4 ];
|
||||
uint8_t InEndpTog[ 4 ];
|
||||
uint8_t InEndpInterval[ 4 ];
|
||||
uint8_t InEndpTimeCount[ 4 ];
|
||||
|
||||
uint8_t OutEndpNum;
|
||||
uint8_t OutEndpAddr[ 4 ];
|
||||
uint8_t OutEndpType[ 4 ];
|
||||
uint16_t OutEndpSize[ 4 ];
|
||||
uint8_t OutEndpTog[ 4 ];
|
||||
|
||||
uint8_t IDFlag;
|
||||
uint8_t ReportID;
|
||||
|
||||
uint8_t LED_Usage_Min;
|
||||
uint8_t LED_Usage_Max;
|
||||
|
||||
uint8_t SetReport_Swi;
|
||||
uint8_t SetReport_Value;
|
||||
uint8_t SetReport_Flag;
|
||||
|
||||
}Interface[ DEF_INTERFACE_NUM_MAX ];
|
||||
};
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Variable Declaration */
|
||||
extern uint8_t DevDesc_Buf[ ];
|
||||
extern uint8_t Com_Buf[ ];
|
||||
extern struct _ROOT_HUB_DEVICE RootHubDev[ ];
|
||||
extern struct __HOST_CTL HostCtl[ ];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,42 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_it.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void SW_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SW_Handler
|
||||
*
|
||||
* @brief This function handles Software exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SW_Handler(void)
|
||||
{
|
||||
|
||||
__asm("li a0, 0x5000");
|
||||
__asm("jr a0");
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,539 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_usb.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __CH32V20x_USB_H
|
||||
#define __CH32V20x_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Header Files */
|
||||
#include "stdint.h"
|
||||
|
||||
/*******************************************************************************/
|
||||
/* USB Communication Related Macro Definition */
|
||||
|
||||
/* USB Endpoint0 Size */
|
||||
#ifndef DEFAULT_ENDP0_SIZE
|
||||
#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0
|
||||
#endif
|
||||
#ifndef MAX_PACKET_SIZE
|
||||
#define MAX_PACKET_SIZE 64 // maximum packet size
|
||||
#endif
|
||||
|
||||
/* USB PID */
|
||||
#ifndef USB_PID_SETUP
|
||||
#define USB_PID_NULL 0x00
|
||||
#define USB_PID_SOF 0x05
|
||||
#define USB_PID_SETUP 0x0D
|
||||
#define USB_PID_IN 0x09
|
||||
#define USB_PID_OUT 0x01
|
||||
#define USB_PID_NYET 0x06
|
||||
#define USB_PID_ACK 0x02
|
||||
#define USB_PID_NAK 0x0A
|
||||
#define USB_PID_STALL 0x0E
|
||||
#define USB_PID_DATA0 0x03
|
||||
#define USB_PID_DATA1 0x0B
|
||||
#define USB_PID_PRE 0x0C
|
||||
#endif
|
||||
|
||||
/* USB standard device request code */
|
||||
#ifndef USB_GET_DESCRIPTOR
|
||||
#define USB_GET_STATUS 0x00
|
||||
#define USB_CLEAR_FEATURE 0x01
|
||||
#define USB_SET_FEATURE 0x03
|
||||
#define USB_SET_ADDRESS 0x05
|
||||
#define USB_GET_DESCRIPTOR 0x06
|
||||
#define USB_SET_DESCRIPTOR 0x07
|
||||
#define USB_GET_CONFIGURATION 0x08
|
||||
#define USB_SET_CONFIGURATION 0x09
|
||||
#define USB_GET_INTERFACE 0x0A
|
||||
#define USB_SET_INTERFACE 0x0B
|
||||
#define USB_SYNCH_FRAME 0x0C
|
||||
#endif
|
||||
|
||||
#define DEF_STRING_DESC_LANG 0x00
|
||||
#define DEF_STRING_DESC_MANU 0x01
|
||||
#define DEF_STRING_DESC_PROD 0x02
|
||||
#define DEF_STRING_DESC_SERN 0x03
|
||||
|
||||
/* USB hub class request code */
|
||||
#ifndef HUB_GET_DESCRIPTOR
|
||||
#define HUB_GET_STATUS 0x00
|
||||
#define HUB_CLEAR_FEATURE 0x01
|
||||
#define HUB_GET_STATE 0x02
|
||||
#define HUB_SET_FEATURE 0x03
|
||||
#define HUB_GET_DESCRIPTOR 0x06
|
||||
#define HUB_SET_DESCRIPTOR 0x07
|
||||
#endif
|
||||
|
||||
/* USB HID class request code */
|
||||
#ifndef HID_GET_REPORT
|
||||
#define HID_GET_REPORT 0x01
|
||||
#define HID_GET_IDLE 0x02
|
||||
#define HID_GET_PROTOCOL 0x03
|
||||
#define HID_SET_REPORT 0x09
|
||||
#define HID_SET_IDLE 0x0A
|
||||
#define HID_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* Bit Define for USB Request Type */
|
||||
#ifndef USB_REQ_TYP_MASK
|
||||
#define USB_REQ_TYP_IN 0x80
|
||||
#define USB_REQ_TYP_OUT 0x00
|
||||
#define USB_REQ_TYP_READ 0x80
|
||||
#define USB_REQ_TYP_WRITE 0x00
|
||||
#define USB_REQ_TYP_MASK 0x60
|
||||
#define USB_REQ_TYP_STANDARD 0x00
|
||||
#define USB_REQ_TYP_CLASS 0x20
|
||||
#define USB_REQ_TYP_VENDOR 0x40
|
||||
#define USB_REQ_TYP_RESERVED 0x60
|
||||
#define USB_REQ_RECIP_MASK 0x1F
|
||||
#define USB_REQ_RECIP_DEVICE 0x00
|
||||
#define USB_REQ_RECIP_INTERF 0x01
|
||||
#define USB_REQ_RECIP_ENDP 0x02
|
||||
#define USB_REQ_RECIP_OTHER 0x03
|
||||
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
|
||||
#define USB_REQ_FEAT_ENDP_HALT 0x00
|
||||
#endif
|
||||
|
||||
/* USB Descriptor Type */
|
||||
#ifndef USB_DESCR_TYP_DEVICE
|
||||
#define USB_DESCR_TYP_DEVICE 0x01
|
||||
#define USB_DESCR_TYP_CONFIG 0x02
|
||||
#define USB_DESCR_TYP_STRING 0x03
|
||||
#define USB_DESCR_TYP_INTERF 0x04
|
||||
#define USB_DESCR_TYP_ENDP 0x05
|
||||
#define USB_DESCR_TYP_QUALIF 0x06
|
||||
#define USB_DESCR_TYP_SPEED 0x07
|
||||
#define USB_DESCR_TYP_OTG 0x09
|
||||
#define USB_DESCR_TYP_BOS 0X0F
|
||||
#define USB_DESCR_TYP_HID 0x21
|
||||
#define USB_DESCR_TYP_REPORT 0x22
|
||||
#define USB_DESCR_TYP_PHYSIC 0x23
|
||||
#define USB_DESCR_TYP_CS_INTF 0x24
|
||||
#define USB_DESCR_TYP_CS_ENDP 0x25
|
||||
#define USB_DESCR_TYP_HUB 0x29
|
||||
#endif
|
||||
|
||||
/* USB Device Class */
|
||||
#ifndef USB_DEV_CLASS_HUB
|
||||
#define USB_DEV_CLASS_RESERVED 0x00
|
||||
#define USB_DEV_CLASS_AUDIO 0x01
|
||||
#define USB_DEV_CLASS_COMMUNIC 0x02
|
||||
#define USB_DEV_CLASS_HID 0x03
|
||||
#define USB_DEV_CLASS_MONITOR 0x04
|
||||
#define USB_DEV_CLASS_PHYSIC_IF 0x05
|
||||
#define USB_DEV_CLASS_POWER 0x06
|
||||
#define USB_DEV_CLASS_PRINTER 0x07
|
||||
#define USB_DEV_CLASS_STORAGE 0x08
|
||||
#define USB_DEV_CLASS_HUB 0x09
|
||||
#define USB_DEV_CLASS_VEN_SPEC 0xFF
|
||||
#endif
|
||||
|
||||
/* USB Hub Class Request */
|
||||
#ifndef HUB_GET_HUB_DESCRIPTOR
|
||||
#define HUB_CLEAR_HUB_FEATURE 0x20
|
||||
#define HUB_CLEAR_PORT_FEATURE 0x23
|
||||
#define HUB_GET_BUS_STATE 0xA3
|
||||
#define HUB_GET_HUB_DESCRIPTOR 0xA0
|
||||
#define HUB_GET_HUB_STATUS 0xA0
|
||||
#define HUB_GET_PORT_STATUS 0xA3
|
||||
#define HUB_SET_HUB_DESCRIPTOR 0x20
|
||||
#define HUB_SET_HUB_FEATURE 0x20
|
||||
#define HUB_SET_PORT_FEATURE 0x23
|
||||
#endif
|
||||
|
||||
/* Hub Class Feature Selectors */
|
||||
#ifndef HUB_PORT_RESET
|
||||
#define HUB_C_HUB_LOCAL_POWER 0
|
||||
#define HUB_C_HUB_OVER_CURRENT 1
|
||||
#define HUB_PORT_CONNECTION 0
|
||||
#define HUB_PORT_ENABLE 1
|
||||
#define HUB_PORT_SUSPEND 2
|
||||
#define HUB_PORT_OVER_CURRENT 3
|
||||
#define HUB_PORT_RESET 4
|
||||
#define HUB_PORT_POWER 8
|
||||
#define HUB_PORT_LOW_SPEED 9
|
||||
#define HUB_C_PORT_CONNECTION 16
|
||||
#define HUB_C_PORT_ENABLE 17
|
||||
#define HUB_C_PORT_SUSPEND 18
|
||||
#define HUB_C_PORT_OVER_CURRENT 19
|
||||
#define HUB_C_PORT_RESET 20
|
||||
#endif
|
||||
|
||||
/* USB HID Class Request Code */
|
||||
#ifndef HID_GET_REPORT
|
||||
#define HID_GET_REPORT 0x01
|
||||
#define HID_GET_IDLE 0x02
|
||||
#define HID_GET_PROTOCOL 0x03
|
||||
#define HID_SET_REPORT 0x09
|
||||
#define HID_SET_IDLE 0x0A
|
||||
#define HID_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* USB UDisk */
|
||||
#ifndef USB_BO_CBW_SIZE
|
||||
#define USB_BO_CBW_SIZE 0x1F
|
||||
#define USB_BO_CSW_SIZE 0x0D
|
||||
#endif
|
||||
#ifndef USB_BO_CBW_SIG0
|
||||
#define USB_BO_CBW_SIG0 0x55
|
||||
#define USB_BO_CBW_SIG1 0x53
|
||||
#define USB_BO_CBW_SIG2 0x42
|
||||
#define USB_BO_CBW_SIG3 0x43
|
||||
#define USB_BO_CSW_SIG0 0x55
|
||||
#define USB_BO_CSW_SIG1 0x53
|
||||
#define USB_BO_CSW_SIG2 0x42
|
||||
#define USB_BO_CSW_SIG3 0x53
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************/
|
||||
/* USBFS Related Register Macro Definition */
|
||||
|
||||
/* R8_USB_CTRL */
|
||||
#define USBFS_UC_HOST_MODE 0x80
|
||||
#define USBFS_UC_LOW_SPEED 0x40
|
||||
#define USBFS_UC_DEV_PU_EN 0x20
|
||||
#define USBFS_UC_SYS_CTRL_MASK 0x30
|
||||
#define USBFS_UC_SYS_CTRL0 0x00
|
||||
#define USBFS_UC_SYS_CTRL1 0x10
|
||||
#define USBFS_UC_SYS_CTRL2 0x20
|
||||
#define USBFS_UC_SYS_CTRL3 0x30
|
||||
#define USBFS_UC_INT_BUSY 0x08
|
||||
#define USBFS_UC_RESET_SIE 0x04
|
||||
#define USBFS_UC_CLR_ALL 0x02
|
||||
#define USBFS_UC_DMA_EN 0x01
|
||||
|
||||
/* R8_USB_INT_EN */
|
||||
#define USBFS_UIE_DEV_SOF 0x80
|
||||
#define USBFS_UIE_DEV_NAK 0x40
|
||||
#define USBFS_UIE_FIFO_OV 0x10
|
||||
#define USBFS_UIE_HST_SOF 0x08
|
||||
#define USBFS_UIE_SUSPEND 0x04
|
||||
#define USBFS_UIE_TRANSFER 0x02
|
||||
#define USBFS_UIE_DETECT 0x01
|
||||
#define USBFS_UIE_BUS_RST 0x01
|
||||
|
||||
/* R8_USB_DEV_AD */
|
||||
#define USBFS_UDA_GP_BIT 0x80
|
||||
#define USBFS_USB_ADDR_MASK 0x7F
|
||||
|
||||
/* R8_USB_MIS_ST */
|
||||
#define USBFS_UMS_SOF_PRES 0x80
|
||||
#define USBFS_UMS_SOF_ACT 0x40
|
||||
#define USBFS_UMS_SIE_FREE 0x20
|
||||
#define USBFS_UMS_R_FIFO_RDY 0x10
|
||||
#define USBFS_UMS_BUS_RESET 0x08
|
||||
#define USBFS_UMS_SUSPEND 0x04
|
||||
#define USBFS_UMS_DM_LEVEL 0x02
|
||||
#define USBFS_UMS_DEV_ATTACH 0x01
|
||||
|
||||
/* R8_USB_INT_FG */
|
||||
#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
|
||||
#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||
#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
|
||||
#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
|
||||
|
||||
/* R8_USB_INT_ST */
|
||||
#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
|
||||
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
|
||||
#define USBFS_UIS_TOKEN_OUT 0x00
|
||||
#define USBFS_UIS_TOKEN_SOF 0x10
|
||||
#define USBFS_UIS_TOKEN_IN 0x20
|
||||
#define USBFS_UIS_TOKEN_SETUP 0x30
|
||||
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
|
||||
// 00: OUT token PID received
|
||||
// 01: SOF token PID received
|
||||
// 10: IN token PID received
|
||||
// 11: SETUP token PID received
|
||||
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
|
||||
#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
|
||||
|
||||
/* R32_USB_OTG_CR */
|
||||
#define USBFS_CR_SESS_VTH 0x20
|
||||
#define USBFS_CR_VBUS_VTH 0x10
|
||||
#define USBFS_CR_OTG_EN 0x08
|
||||
#define USBFS_CR_IDPU 0x04
|
||||
#define USBFS_CR_CHARGE_VBUS 0x02
|
||||
#define USBFS_CR_DISCHAR_VBUS 0x01
|
||||
|
||||
/* R32_USB_OTG_SR */
|
||||
#define USBFS_SR_ID_DIG 0x08
|
||||
#define USBFS_SR_SESS_END 0x04
|
||||
#define USBFS_SR_SESS_VLD 0x02
|
||||
#define USBFS_SR_VBUS_VLD 0x01
|
||||
|
||||
/* R8_UDEV_CTRL */
|
||||
#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||
#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||
#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||
#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
|
||||
#define USBFS_UD_GP_BIT 0x02 // general purpose bit
|
||||
#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
|
||||
|
||||
/* R8_UEP4_1_MOD */
|
||||
#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
|
||||
#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
|
||||
#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
|
||||
// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
|
||||
// 0 0 x: disable endpoint and disable buffer
|
||||
// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
|
||||
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
|
||||
// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
|
||||
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
|
||||
// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
|
||||
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
|
||||
#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
|
||||
#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
|
||||
// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
|
||||
// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
||||
// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
|
||||
// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
|
||||
// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
||||
// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
|
||||
#define USBFS_UEP4_BUF_MOD 0x01
|
||||
|
||||
/* R8_UEP2_3_MOD */
|
||||
#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
|
||||
#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
|
||||
#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
|
||||
#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
|
||||
#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
|
||||
#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
|
||||
|
||||
/* R8_UEP5_6_MOD */
|
||||
#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT)
|
||||
#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN)
|
||||
#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6
|
||||
#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT)
|
||||
#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN)
|
||||
#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5
|
||||
|
||||
/* R8_UEP7_MOD */
|
||||
#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT)
|
||||
#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN)
|
||||
#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7
|
||||
|
||||
/* R8_UEPn_TX_CTRL */
|
||||
#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
|
||||
#define USBFS_UEP_T_RES_ACK 0x00
|
||||
#define USBFS_UEP_T_RES_NONE 0x01
|
||||
#define USBFS_UEP_T_RES_NAK 0x02
|
||||
#define USBFS_UEP_T_RES_STALL 0x03
|
||||
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
|
||||
// 00: DATA0 or DATA1 then expecting ACK (ready)
|
||||
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
|
||||
// 10: NAK (busy)
|
||||
// 11: STALL (error)
|
||||
// host aux setup
|
||||
|
||||
/* R8_UEPn_RX_CTRL, n=0-7 */
|
||||
#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT)
|
||||
#define USBFS_UEP_R_RES_ACK 0x00
|
||||
#define USBFS_UEP_R_RES_NONE 0x01
|
||||
#define USBFS_UEP_R_RES_NAK 0x02
|
||||
#define USBFS_UEP_R_RES_STALL 0x03
|
||||
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
|
||||
// 00: ACK (ready)
|
||||
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
|
||||
// 10: NAK (busy)
|
||||
// 11: STALL (error)
|
||||
|
||||
/* R8_UHOST_CTRL */
|
||||
#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||
#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||
#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||
#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
|
||||
#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
|
||||
#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
|
||||
|
||||
/* R32_UH_EP_MOD */
|
||||
#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
|
||||
#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
|
||||
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
|
||||
// 0 x: disable endpoint and disable buffer
|
||||
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
|
||||
#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
|
||||
#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
|
||||
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
|
||||
// 0 x: disable endpoint and disable buffer
|
||||
// 1 0: 64 bytes buffer for receiving (IN endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
|
||||
|
||||
/* R16_UH_SETUP */
|
||||
#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub
|
||||
#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable
|
||||
|
||||
/* R8_UH_EP_PID */
|
||||
#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
|
||||
#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
|
||||
|
||||
/* R8_UH_RX_CTRL */
|
||||
#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
||||
|
||||
/* R8_UH_TX_CTRL */
|
||||
#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
||||
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Struct Definition */
|
||||
|
||||
/* USB Setup Request */
|
||||
typedef struct __attribute__((packed)) _USB_SETUP_REQ
|
||||
{
|
||||
uint8_t bRequestType;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
|
||||
|
||||
/* USB Device Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdUSB;
|
||||
uint8_t bDeviceClass;
|
||||
uint8_t bDeviceSubClass;
|
||||
uint8_t bDeviceProtocol;
|
||||
uint8_t bMaxPacketSize0;
|
||||
uint16_t idVendor;
|
||||
uint16_t idProduct;
|
||||
uint16_t bcdDevice;
|
||||
uint8_t iManufacturer;
|
||||
uint8_t iProduct;
|
||||
uint8_t iSerialNumber;
|
||||
uint8_t bNumConfigurations;
|
||||
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
|
||||
|
||||
/* USB Configuration Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wTotalLength;
|
||||
uint8_t bNumInterfaces;
|
||||
uint8_t bConfigurationValue;
|
||||
uint8_t iConfiguration;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t MaxPower;
|
||||
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
|
||||
|
||||
/* USB Interface Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bInterfaceNumber;
|
||||
uint8_t bAlternateSetting;
|
||||
uint8_t bNumEndpoints;
|
||||
uint8_t bInterfaceClass;
|
||||
uint8_t bInterfaceSubClass;
|
||||
uint8_t bInterfaceProtocol;
|
||||
uint8_t iInterface;
|
||||
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
|
||||
|
||||
/* USB Endpoint Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t wMaxPacketSizeL;
|
||||
uint8_t wMaxPacketSizeH;
|
||||
uint8_t bInterval;
|
||||
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
|
||||
|
||||
/* USB Configuration Descriptor Set */
|
||||
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
|
||||
{
|
||||
USB_CFG_DESCR cfg_descr;
|
||||
USB_ITF_DESCR itf_descr;
|
||||
USB_ENDP_DESCR endp_descr[ 1 ];
|
||||
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
|
||||
|
||||
/* USB HUB Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_HUB_DESCR
|
||||
{
|
||||
uint8_t bDescLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bNbrPorts;
|
||||
uint8_t wHubCharacteristicsL;
|
||||
uint8_t wHubCharacteristicsH;
|
||||
uint8_t bPwrOn2PwrGood;
|
||||
uint8_t bHubContrCurrent;
|
||||
uint8_t DeviceRemovable;
|
||||
uint8_t PortPwrCtrlMask;
|
||||
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
|
||||
|
||||
/* USB HID Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_HID_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdHID;
|
||||
uint8_t bCountryCode;
|
||||
uint8_t bNumDescriptors;
|
||||
uint8_t bDescriptorTypeX;
|
||||
uint8_t wDescriptorLengthL;
|
||||
uint8_t wDescriptorLengthH;
|
||||
} USB_HID_DESCR, *PUSB_HID_DESCR;
|
||||
|
||||
/* USB UDisk */
|
||||
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
|
||||
{
|
||||
uint32_t mCBW_Sig;
|
||||
uint32_t mCBW_Tag;
|
||||
uint32_t mCBW_DataLen;
|
||||
uint8_t mCBW_Flag;
|
||||
uint8_t mCBW_LUN;
|
||||
uint8_t mCBW_CB_Len;
|
||||
uint8_t mCBW_CB_Buf[ 16 ];
|
||||
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
|
||||
|
||||
/* USB UDisk */
|
||||
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
|
||||
{
|
||||
uint32_t mCBW_Sig;
|
||||
uint32_t mCBW_Tag;
|
||||
uint32_t mCSW_Residue;
|
||||
uint8_t mCSW_Status;
|
||||
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V20x_USB_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2022/08/20
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/*
|
||||
*@Note
|
||||
USB host IAP demo code.
|
||||
USBFS HOST USB drive enumeration and operation, read the APP.BIN file in the root directory inside the USB drive, write to location 0x08005000, after a successful check
|
||||
Write the flag data, then jump to the user code. The code will run IAP first to check the flag data, if the preparation data is normal, it will jump to the user code, otherwise
|
||||
If the compiled data is OK, it will jump to the user code, if not, it will stay in IAP again.
|
||||
Support: FAT12/FAT16/FAT32
|
||||
*/
|
||||
|
||||
#include "usb_host_iap.h"
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
USART_Printf_Init(115200);
|
||||
Delay_Init( );
|
||||
printf("SystemClk:%d\r\n",SystemCoreClock);
|
||||
printf("USBFS-OTG HOST,UDisk IAP.\r\n");
|
||||
|
||||
IAP_Initialization( );
|
||||
|
||||
while( 1 )
|
||||
{
|
||||
IAP_Main_Deal( );
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,986 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user