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qiyongshuang
2026-01-07 10:43:29 +08:00
parent 6209b6e7f9
commit d161f84c90
551 changed files with 23169 additions and 1518 deletions
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EVT/EXAM/ETH/DHCP/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/DHCP.hex
EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/DNS/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/DNS.hex
EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/ETH_CFG/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/ETH_CFG.hex
EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/ETH_IAP/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/ETH_IAP.hex
EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/ETH_UART/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/ETH_UART.hex
EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/IPRaw_PING/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/IPRaw_PING.hex
EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/MAC_RAW/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/MAC_RAW.hex
EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
+6 -3
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@@ -488,10 +488,13 @@ void ETH_Configuration( uint8_t *macAddr )
uint32_t MACRAW_Tx(uint8_t *buff, uint16_t len)
{
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if( DMATxDescToSet->Status & ETH_DMATxDesc_OWN )
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN))
{
/* Return ERROR: OWN bit set */
return ETH_ERROR;
if((R8_ETH_ECON1 & RB_ETH_ECON1_TXRTS) == 0)
{
DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
}
else return ETH_ERROR;
}
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
R16_ETH_ETXLN = len;
EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/MQTT/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/MQTT.hex
EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/Mail/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/Mail.hex
EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/NetLib/eth_driver.c
+6 -3
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@@ -535,10 +535,13 @@ void ETH_Configuration( uint8_t *macAddr )
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
{
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if( DMATxDescToSet->Status & ETH_DMATxDesc_OWN )
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN))
{
/* Return ERROR: OWN bit set */
return ETH_ERROR;
if((R8_ETH_ECON1 & RB_ETH_ECON1_TXRTS) == 0)
{
DMATxDescToSet->Status &= ~ETH_DMATxDesc_OWN;
}
else return ETH_ERROR;
}
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
R16_ETH_ETXLN = len;
EVT/EXAM/ETH/NetLib/libwchnet.a
BIN
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EVT/EXAM/ETH/NetLib/wchnet.h
+26 -1
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@@ -21,7 +21,7 @@
extern "C" {
#endif
#define WCHNET_LIB_VER 0x1A //the library version number
#define WCHNET_LIB_VER 0x1B //the library version number
#define WCHNET_CFG_VALID 0x12345678 //Configuration value valid flag
/* LED state @LED_STAT */
@@ -167,6 +167,8 @@ typedef uint8_t (*dhcp_callback)( uint8_t status, void * );
struct _SOCK_INF;
typedef void (*pSockRecv)( struct _SOCK_INF *, uint32_t, uint16_t, uint8_t *, uint32_t);
typedef uint8_t (*pTcpVerifyConnection)(uint32_t src_ip, uint16_t src_port, uint16_t dest_port);
/* Socket information struct */
typedef struct _SOCK_INF
{
@@ -579,6 +581,20 @@ uint8_t WCHNET_HostNameGetIp( const char *hostname, uint8_t *addr, dns_callback
*/
void WCHNET_ConfigKeepLive( struct _KEEP_CFG *cfg );
/**
* @brief Configure ARP retransmission parameters.
*
* @param retry_period - ARP retransmission period, the default value is 10, the unit is 100ms
* retry_cnt - The number of ARP retransmissions, the default value is 3.
* When the value of the retry_cnt is 0xff, it will be retried
* until the MAC address of the device is obtained.
* Arp_Entry_timeout_s - the time an ARP entry stays valid after its last update.
* the default value is 300, the unit is 1s
*
* @return None
*/
void WCHNET_ARPRetryCfg(uint8_t retry_period, uint8_t retry_cnt, uint16_t Arp_Entry_timeout_s);
/**
* @brief Configure socket KEEP LIVE enable.
*
@@ -598,6 +614,15 @@ uint8_t WCHNET_SocketSetKeepLive( uint8_t socketid, uint8_t enable );
*/
void WCHNET_PhyStatus( uint32_t phy_stat );
/**
* @brief Configure socket Nagle Func.
*
* @param socketid - socket id value
* @param enable - 1: Enabled. 0: Disabled.
*
* @return @ERR_T
*/
uint8_t WCHNET_SocketSetNagle( uint8_t socketid, uint8_t enable );
#ifdef __cplusplus
}
EVT/EXAM/ETH/TcpClient/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/TCPClient.hex
EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/TcpServer/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/TCPServer.hex
EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/UdpClient/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/UDPClient.hex
EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/UdpServer/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/UDPServer.hex
EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
EVT/EXAM/ETH/WebServer/.template
+1 -1
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@@ -12,5 +12,5 @@ Series=CH32V203
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
PeripheralVersion=1.0
MCU=CH32V203RBT6
MCU=CH32V203RBT
Target Path=obj/WebServer.hex
EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
+1 -1
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@@ -4,7 +4,7 @@
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.