V2.31
This commit is contained in:
qiyongshuang
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|
||||
CalibrateCommand=
|
||||
MCU=CH32V203RBT6
|
||||
Link=WCH-Link
|
||||
PeripheralVersion=1.0
|
||||
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||
ArtifactType=executable
|
||||
Mcu Type=CH32V20x
|
||||
Address=0x08000000
|
||||
Target Path=obj/Stop_Mode_RtcWakeUp.hex
|
||||
Exe Path=
|
||||
Exe Arguments=
|
||||
CLKSpeed=1
|
||||
DebugInterfaceMode=0
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=true
|
||||
Reset=true
|
||||
SDIPrintf=false
|
||||
Disable Power Output=false
|
||||
Clear CodeFlash=false
|
||||
Disable Code-Protect=false
|
||||
@@ -0,0 +1,202 @@
|
||||
ENTRY( _start )
|
||||
|
||||
__stack_size = 2048;
|
||||
|
||||
PROVIDE( _stack_size = __stack_size );
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */
|
||||
/*
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
|
||||
*/
|
||||
|
||||
/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
|
||||
/**/
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
|
||||
|
||||
/* CH32V20x_D8 - CH32V203RB
|
||||
CH32V20x_D8W - CH32V208x
|
||||
FLASH + RAM supports the following configuration
|
||||
FLASH-128K + RAM-64K
|
||||
FLASH-144K + RAM-48K
|
||||
FLASH-160K + RAM-32K
|
||||
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.init :
|
||||
{
|
||||
_sinit = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(SORT_NONE(.init)))
|
||||
. = ALIGN(4);
|
||||
_einit = .;
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.vector :
|
||||
{
|
||||
*(.vector);
|
||||
. = ALIGN(64);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.highcodelalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_highcode_lma = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.highcode :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_highcode_vma_start = .);
|
||||
*(.highcode);
|
||||
*(.highcode.*);
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_highcode_vma_end = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(SORT_NONE(.fini)))
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
PROVIDE( _etext = . );
|
||||
PROVIDE( _eitcm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_vma = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.dlalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_lma = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _sbss = .);
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ebss = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
PROVIDE( _end = _ebss);
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_susrstack = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _eusrstack = .);
|
||||
} >RAM
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,266 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_ch32v20x_D6.s
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.2
|
||||
;* Date : 2025/10/21
|
||||
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
|
||||
;* Startup File.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
.global _start
|
||||
.align 1
|
||||
_start:
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 1
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler /* NMI */
|
||||
.word HardFault_Handler /* Hard Fault */
|
||||
.word 0
|
||||
.word Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.word Break_Point_Handler /* Break Point */
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler /* SysTick */
|
||||
.word 0
|
||||
.word SW_Handler /* SW */
|
||||
.word 0
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.word TAMPER_IRQHandler /* TAMPER */
|
||||
.word RTC_IRQHandler /* RTC */
|
||||
.word FLASH_IRQHandler /* Flash */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.word ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
|
||||
.word USBFS_IRQHandler /* USBFS Break */
|
||||
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler /* NMI */
|
||||
.weak HardFault_Handler /* Hard Fault */
|
||||
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.weak Break_Point_Handler /* Break Point */
|
||||
.weak SysTick_Handler /* SysTick */
|
||||
.weak SW_Handler /* SW */
|
||||
.weak WWDG_IRQHandler /* Window Watchdog */
|
||||
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.weak TAMPER_IRQHandler /* TAMPER */
|
||||
.weak RTC_IRQHandler /* RTC */
|
||||
.weak FLASH_IRQHandler /* Flash */
|
||||
.weak RCC_IRQHandler /* RCC */
|
||||
.weak EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
.weak EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
.weak EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
.weak EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
.weak EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.weak ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.weak TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.weak TIM2_IRQHandler /* TIM2 */
|
||||
.weak TIM3_IRQHandler /* TIM3 */
|
||||
.weak TIM4_IRQHandler /* TIM4 */
|
||||
.weak I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.weak I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.weak I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.weak I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.weak SPI1_IRQHandler /* SPI1 */
|
||||
.weak SPI2_IRQHandler /* SPI2 */
|
||||
.weak USART1_IRQHandler /* USART1 */
|
||||
.weak USART2_IRQHandler /* USART2 */
|
||||
.weak USART3_IRQHandler /* USART3 */
|
||||
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||
.weak USBFS_IRQHandler /* USBFS */
|
||||
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
|
||||
.weak UART4_IRQHandler /* UART4 */
|
||||
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Mode_Handler:
|
||||
Ecall_U_Mode_Handler:
|
||||
Break_Point_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
WWDG_IRQHandler:
|
||||
PVD_IRQHandler:
|
||||
TAMPER_IRQHandler:
|
||||
RTC_IRQHandler:
|
||||
FLASH_IRQHandler:
|
||||
RCC_IRQHandler:
|
||||
EXTI0_IRQHandler:
|
||||
EXTI1_IRQHandler:
|
||||
EXTI2_IRQHandler:
|
||||
EXTI3_IRQHandler:
|
||||
EXTI4_IRQHandler:
|
||||
DMA1_Channel1_IRQHandler:
|
||||
DMA1_Channel2_IRQHandler:
|
||||
DMA1_Channel3_IRQHandler:
|
||||
DMA1_Channel4_IRQHandler:
|
||||
DMA1_Channel5_IRQHandler:
|
||||
DMA1_Channel6_IRQHandler:
|
||||
DMA1_Channel7_IRQHandler:
|
||||
ADC1_2_IRQHandler:
|
||||
USB_HP_CAN1_TX_IRQHandler:
|
||||
USB_LP_CAN1_RX0_IRQHandler:
|
||||
CAN1_RX1_IRQHandler:
|
||||
CAN1_SCE_IRQHandler:
|
||||
EXTI9_5_IRQHandler:
|
||||
TIM1_BRK_IRQHandler:
|
||||
TIM1_UP_IRQHandler:
|
||||
TIM1_TRG_COM_IRQHandler:
|
||||
TIM1_CC_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
TIM4_IRQHandler:
|
||||
I2C1_EV_IRQHandler:
|
||||
I2C1_ER_IRQHandler:
|
||||
I2C2_EV_IRQHandler:
|
||||
I2C2_ER_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
SPI2_IRQHandler:
|
||||
USART1_IRQHandler:
|
||||
USART2_IRQHandler:
|
||||
USART3_IRQHandler:
|
||||
EXTI15_10_IRQHandler:
|
||||
RTCAlarm_IRQHandler:
|
||||
USBWakeUp_IRQHandler:
|
||||
USBFS_IRQHandler:
|
||||
USBFSWakeUp_IRQHandler:
|
||||
UART4_IRQHandler:
|
||||
DMA1_Channel8_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
|
||||
la sp, _eusrstack
|
||||
|
||||
/* Load highcode code section from flash to RAM */
|
||||
la a0, _highcode_lma
|
||||
la a1, _highcode_vma_start
|
||||
la a2, _highcode_vma_end
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x88
|
||||
csrw mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
|
||||
jal SystemInit
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
|
||||
|
||||
@@ -0,0 +1,281 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_ch32v20x_D8.s
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.2
|
||||
;* Date : 2025/10/21
|
||||
;* Description : CH32V203RB
|
||||
;* Startup File.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
.global _start
|
||||
.align 1
|
||||
_start:
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 1
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler /* NMI */
|
||||
.word HardFault_Handler /* Hard Fault */
|
||||
.word 0
|
||||
.word Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.word Break_Point_Handler /* Break Point */
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler /* SysTick */
|
||||
.word 0
|
||||
.word SW_Handler /* SW */
|
||||
.word 0
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.word TAMPER_IRQHandler /* TAMPER */
|
||||
.word RTC_IRQHandler /* RTC */
|
||||
.word FLASH_IRQHandler /* Flash */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.word ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
|
||||
.word USBFS_IRQHandler /* USBFS Break */
|
||||
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
|
||||
.word ETH_IRQHandler /* ETH global */
|
||||
.word ETHWakeUp_IRQHandler /* ETH Wake up */
|
||||
.word 0 /* BLE BB */
|
||||
.word 0 /* BLE LLE */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
.word OSC32KCal_IRQHandler /* OSC32KCal */
|
||||
.word OSCWakeUp_IRQHandler /* OSC Wake Up */
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler /* NMI */
|
||||
.weak HardFault_Handler /* Hard Fault */
|
||||
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.weak Break_Point_Handler /* Break Point */
|
||||
.weak SysTick_Handler /* SysTick */
|
||||
.weak SW_Handler /* SW */
|
||||
.weak WWDG_IRQHandler /* Window Watchdog */
|
||||
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.weak TAMPER_IRQHandler /* TAMPER */
|
||||
.weak RTC_IRQHandler /* RTC */
|
||||
.weak FLASH_IRQHandler /* Flash */
|
||||
.weak RCC_IRQHandler /* RCC */
|
||||
.weak EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
.weak EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
.weak EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
.weak EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
.weak EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.weak ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.weak TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.weak TIM2_IRQHandler /* TIM2 */
|
||||
.weak TIM3_IRQHandler /* TIM3 */
|
||||
.weak TIM4_IRQHandler /* TIM4 */
|
||||
.weak I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.weak I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.weak I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.weak I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.weak SPI1_IRQHandler /* SPI1 */
|
||||
.weak SPI2_IRQHandler /* SPI2 */
|
||||
.weak USART1_IRQHandler /* USART1 */
|
||||
.weak USART2_IRQHandler /* USART2 */
|
||||
.weak USART3_IRQHandler /* USART3 */
|
||||
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||
.weak USBFS_IRQHandler /* USBFS */
|
||||
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
|
||||
.weak ETH_IRQHandler /* ETH global */
|
||||
.weak ETHWakeUp_IRQHandler /* ETHWakeUp */
|
||||
.weak TIM5_IRQHandler /* TIM5 */
|
||||
.weak UART4_IRQHandler /* UART4 */
|
||||
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
.weak OSC32KCal_IRQHandler /* OSC32 KCal */
|
||||
.weak OSCWakeUp_IRQHandler /* OSC Wake Up */
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Mode_Handler:
|
||||
Ecall_U_Mode_Handler:
|
||||
Break_Point_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
WWDG_IRQHandler:
|
||||
PVD_IRQHandler:
|
||||
TAMPER_IRQHandler:
|
||||
RTC_IRQHandler:
|
||||
FLASH_IRQHandler:
|
||||
RCC_IRQHandler:
|
||||
EXTI0_IRQHandler:
|
||||
EXTI1_IRQHandler:
|
||||
EXTI2_IRQHandler:
|
||||
EXTI3_IRQHandler:
|
||||
EXTI4_IRQHandler:
|
||||
DMA1_Channel1_IRQHandler:
|
||||
DMA1_Channel2_IRQHandler:
|
||||
DMA1_Channel3_IRQHandler:
|
||||
DMA1_Channel4_IRQHandler:
|
||||
DMA1_Channel5_IRQHandler:
|
||||
DMA1_Channel6_IRQHandler:
|
||||
DMA1_Channel7_IRQHandler:
|
||||
ADC1_2_IRQHandler:
|
||||
USB_HP_CAN1_TX_IRQHandler:
|
||||
USB_LP_CAN1_RX0_IRQHandler:
|
||||
CAN1_RX1_IRQHandler:
|
||||
CAN1_SCE_IRQHandler:
|
||||
EXTI9_5_IRQHandler:
|
||||
TIM1_BRK_IRQHandler:
|
||||
TIM1_UP_IRQHandler:
|
||||
TIM1_TRG_COM_IRQHandler:
|
||||
TIM1_CC_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
TIM4_IRQHandler:
|
||||
I2C1_EV_IRQHandler:
|
||||
I2C1_ER_IRQHandler:
|
||||
I2C2_EV_IRQHandler:
|
||||
I2C2_ER_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
SPI2_IRQHandler:
|
||||
USART1_IRQHandler:
|
||||
USART2_IRQHandler:
|
||||
USART3_IRQHandler:
|
||||
EXTI15_10_IRQHandler:
|
||||
RTCAlarm_IRQHandler:
|
||||
USBWakeUp_IRQHandler:
|
||||
USBFS_IRQHandler:
|
||||
USBFSWakeUp_IRQHandler:
|
||||
ETH_IRQHandler:
|
||||
ETHWakeUp_IRQHandler:
|
||||
TIM5_IRQHandler:
|
||||
OSC32KCal_IRQHandler:
|
||||
OSCWakeUp_IRQHandler:
|
||||
UART4_IRQHandler:
|
||||
DMA1_Channel8_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
|
||||
la sp, _eusrstack
|
||||
|
||||
/* Load highcode code section from flash to RAM */
|
||||
la a0, _highcode_lma
|
||||
la a1, _highcode_vma_start
|
||||
la a2, _highcode_vma_end
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x88
|
||||
csrw mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
|
||||
jal SystemInit
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
@@ -0,0 +1,287 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_ch32v20x_D8W.s
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.2
|
||||
;* Date : 2025/10/21
|
||||
;* Description : CH32V208x
|
||||
;* Startup File
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
.global _start
|
||||
.align 1
|
||||
_start:
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 1
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler /* NMI */
|
||||
.word HardFault_Handler /* Hard Fault */
|
||||
.word 0
|
||||
.word Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.word Break_Point_Handler /* Break Point */
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler /* SysTick */
|
||||
.word 0
|
||||
.word SW_Handler /* SW */
|
||||
.word 0
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.word TAMPER_IRQHandler /* TAMPER */
|
||||
.word RTC_IRQHandler /* RTC */
|
||||
.word FLASH_IRQHandler /* Flash */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.word ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
|
||||
.word USBFS_IRQHandler /* USBFS Break */
|
||||
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
|
||||
.word ETH_IRQHandler /* ETH global */
|
||||
.word ETHWakeUp_IRQHandler /* ETH Wake up */
|
||||
.word BB_IRQHandler /* BLE BB */
|
||||
.word LLE_IRQHandler /* BLE LLE */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
.word OSC32KCal_IRQHandler /* OSC32KCal */
|
||||
.word OSCWakeUp_IRQHandler /* OSC Wake Up */
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler /* NMI */
|
||||
.weak HardFault_Handler /* Hard Fault */
|
||||
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.weak Break_Point_Handler /* Break Point */
|
||||
.weak SysTick_Handler /* SysTick */
|
||||
.weak SW_Handler /* SW */
|
||||
.weak WWDG_IRQHandler /* Window Watchdog */
|
||||
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.weak TAMPER_IRQHandler /* TAMPER */
|
||||
.weak RTC_IRQHandler /* RTC */
|
||||
.weak FLASH_IRQHandler /* Flash */
|
||||
.weak RCC_IRQHandler /* RCC */
|
||||
.weak EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
.weak EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
.weak EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
.weak EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
.weak EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.weak ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.weak TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.weak TIM2_IRQHandler /* TIM2 */
|
||||
.weak TIM3_IRQHandler /* TIM3 */
|
||||
.weak TIM4_IRQHandler /* TIM4 */
|
||||
.weak I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.weak I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.weak I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.weak I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.weak SPI1_IRQHandler /* SPI1 */
|
||||
.weak SPI2_IRQHandler /* SPI2 */
|
||||
.weak USART1_IRQHandler /* USART1 */
|
||||
.weak USART2_IRQHandler /* USART2 */
|
||||
.weak USART3_IRQHandler /* USART3 */
|
||||
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||
.weak USBFS_IRQHandler /* USBFS */
|
||||
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
|
||||
.weak ETH_IRQHandler /* ETH global */
|
||||
.weak ETHWakeUp_IRQHandler /* ETHWakeUp */
|
||||
.weak BB_IRQHandler /* BLE BB */
|
||||
.weak LLE_IRQHandler /* BLE LLE */
|
||||
.weak TIM5_IRQHandler /* TIM5 */
|
||||
.weak UART4_IRQHandler /* UART4 */
|
||||
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
.weak OSC32KCal_IRQHandler /* OSC32 KCal */
|
||||
.weak OSCWakeUp_IRQHandler /* OSC Wake Up */
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Mode_Handler:
|
||||
Ecall_U_Mode_Handler:
|
||||
Break_Point_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
WWDG_IRQHandler:
|
||||
PVD_IRQHandler:
|
||||
TAMPER_IRQHandler:
|
||||
RTC_IRQHandler:
|
||||
FLASH_IRQHandler:
|
||||
RCC_IRQHandler:
|
||||
EXTI0_IRQHandler:
|
||||
EXTI1_IRQHandler:
|
||||
EXTI2_IRQHandler:
|
||||
EXTI3_IRQHandler:
|
||||
EXTI4_IRQHandler:
|
||||
DMA1_Channel1_IRQHandler:
|
||||
DMA1_Channel2_IRQHandler:
|
||||
DMA1_Channel3_IRQHandler:
|
||||
DMA1_Channel4_IRQHandler:
|
||||
DMA1_Channel5_IRQHandler:
|
||||
DMA1_Channel6_IRQHandler:
|
||||
DMA1_Channel7_IRQHandler:
|
||||
ADC1_2_IRQHandler:
|
||||
USB_HP_CAN1_TX_IRQHandler:
|
||||
USB_LP_CAN1_RX0_IRQHandler:
|
||||
CAN1_RX1_IRQHandler:
|
||||
CAN1_SCE_IRQHandler:
|
||||
EXTI9_5_IRQHandler:
|
||||
TIM1_BRK_IRQHandler:
|
||||
TIM1_UP_IRQHandler:
|
||||
TIM1_TRG_COM_IRQHandler:
|
||||
TIM1_CC_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
TIM4_IRQHandler:
|
||||
I2C1_EV_IRQHandler:
|
||||
I2C1_ER_IRQHandler:
|
||||
I2C2_EV_IRQHandler:
|
||||
I2C2_ER_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
SPI2_IRQHandler:
|
||||
USART1_IRQHandler:
|
||||
USART2_IRQHandler:
|
||||
USART3_IRQHandler:
|
||||
EXTI15_10_IRQHandler:
|
||||
RTCAlarm_IRQHandler:
|
||||
USBWakeUp_IRQHandler:
|
||||
USBFS_IRQHandler:
|
||||
USBFSWakeUp_IRQHandler:
|
||||
ETH_IRQHandler:
|
||||
ETHWakeUp_IRQHandler:
|
||||
BB_IRQHandler:
|
||||
LLE_IRQHandler:
|
||||
TIM5_IRQHandler:
|
||||
UART4_IRQHandler:
|
||||
DMA1_Channel8_IRQHandler:
|
||||
OSC32KCal_IRQHandler:
|
||||
OSCWakeUp_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
|
||||
la sp, _eusrstack
|
||||
|
||||
/* Load highcode code section from flash to RAM */
|
||||
la a0, _highcode_lma
|
||||
la a1, _highcode_vma_start
|
||||
la a2, _highcode_vma_end
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x88
|
||||
csrw mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
|
||||
jal SystemInit
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
|
||||
|
||||
@@ -0,0 +1,423 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"isNormalMRSProject": true,
|
||||
"basic": {
|
||||
"chipInfo": {
|
||||
"vendor": "WCH",
|
||||
"toolchain": "RISC-V",
|
||||
"series": "CH32V203",
|
||||
"rtos": "NoneOS",
|
||||
"mcu": "CH32V203RBT6",
|
||||
"description": "ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.",
|
||||
"artifactType": "executable",
|
||||
"link": "WCH-Link",
|
||||
"peripheral_version": "1.0",
|
||||
"calibrateSupport": false,
|
||||
"calibrateCommand": ""
|
||||
},
|
||||
"linkedFolders": [
|
||||
{
|
||||
"name": "Core",
|
||||
"location": "../../SRC/Core"
|
||||
},
|
||||
{
|
||||
"name": "Debug",
|
||||
"location": "../../SRC/Debug"
|
||||
},
|
||||
{
|
||||
"name": "Peripheral",
|
||||
"location": "../../SRC/Peripheral"
|
||||
}
|
||||
],
|
||||
"removedResources": [
|
||||
{
|
||||
"parentLogicPath": "",
|
||||
"type": "file",
|
||||
"name": "*.wvproj"
|
||||
}
|
||||
],
|
||||
"projectName": "Stop_Lp_Repeat_RTCwkup_02",
|
||||
"architecture": "RISC-V",
|
||||
"projectType": "c"
|
||||
},
|
||||
"buildConfig": {
|
||||
"configurations": [
|
||||
{
|
||||
"buildArtifact": {
|
||||
"artifact_name": "${ProjName}",
|
||||
"artifact_extension": "elf",
|
||||
"output_prefix": "",
|
||||
"artifact_type": "Executable"
|
||||
},
|
||||
"parallelizationNumber": "optimal",
|
||||
"stop_on_first_build_error": true,
|
||||
"pre_script": "",
|
||||
"pre_script_description": "",
|
||||
"post_script": "",
|
||||
"post_script_description": "",
|
||||
"excludeResources": [
|
||||
"${project}/Startup/startup_ch32v20x_D8W.S",
|
||||
"${project}/Startup/startup_ch32v20x_D8.S"
|
||||
],
|
||||
"optimization": {
|
||||
"level": "size",
|
||||
"message_length": true,
|
||||
"char_is_signed": true,
|
||||
"function_sections": true,
|
||||
"data_sections": true,
|
||||
"no_common_unitialized": true,
|
||||
"do_not_inline_functions": false,
|
||||
"assume_freestanding_environment": false,
|
||||
"disable_builtin": false,
|
||||
"single_precision_constants": false,
|
||||
"position_independent_code": false,
|
||||
"link_time_optimizer": false,
|
||||
"disable_loop_invariant_move": false,
|
||||
"optimize_unused_sections_declared_as_high_code": false,
|
||||
"code_generation_without_hardware_floating": false,
|
||||
"use_pipelines": false,
|
||||
"show_caret_indicating_the_column": false,
|
||||
"other_optimization_flags": ""
|
||||
},
|
||||
"warnings": {
|
||||
"check_syntax_only": false,
|
||||
"pedantic": false,
|
||||
"pedantic_warnings_as_errors": false,
|
||||
"inhibit_all_warnings": false,
|
||||
"warn_on_various_unused_elements": true,
|
||||
"warn_on_uninitialized_variables": true,
|
||||
"enable_all_common_warnings": false,
|
||||
"enable_extra_warnings": false,
|
||||
"warn_on_undeclared_global_function": false,
|
||||
"warn_on_implicit_conversions": false,
|
||||
"warn_if_pointer_arthmetic": false,
|
||||
"warn_if_padding_is_included": false,
|
||||
"warn_if_shadowed_variable": false,
|
||||
"warn_if_suspicious_logical_ops": false,
|
||||
"warn_if_struct_is_returned": false,
|
||||
"warn_if_floats_are_compared_as_equal": false,
|
||||
"generate_errors_instead_of_warnings": false,
|
||||
"other_warning_flags": ""
|
||||
},
|
||||
"debugging": {
|
||||
"debug_level": "default",
|
||||
"debug_format": "default",
|
||||
"generate_prof_information": false,
|
||||
"generate_gprof_information": false,
|
||||
"other_debugging_flags": ""
|
||||
},
|
||||
"assembler": {
|
||||
"preprocessor": {
|
||||
"use_preprocessor": true,
|
||||
"do_not_search_system_directories": false,
|
||||
"preprocess_only": false,
|
||||
"defined_symbols": [],
|
||||
"undefined_symbols": []
|
||||
},
|
||||
"includes": {
|
||||
"include_paths": [
|
||||
"${project}/Startup"
|
||||
],
|
||||
"include_system_paths": [],
|
||||
"include_files": []
|
||||
},
|
||||
"other_warning_flags": "",
|
||||
"miscellaneous": {
|
||||
"assembler_flags": [],
|
||||
"generate_assembler_listing": false,
|
||||
"save_temporary_files": false,
|
||||
"verbose": false,
|
||||
"other_assembler_flags": ""
|
||||
}
|
||||
},
|
||||
"ccompiler": {
|
||||
"preprocessor": {
|
||||
"do_not_search_system_directories": false,
|
||||
"preprocess_only": false,
|
||||
"defined_symbols": [],
|
||||
"undefined_symbols": []
|
||||
},
|
||||
"includes": {
|
||||
"include_paths": [
|
||||
"${project}/Debug",
|
||||
"${project}/Core",
|
||||
"${project}/User",
|
||||
"${project}/Peripheral/inc"
|
||||
],
|
||||
"include_system_paths": [],
|
||||
"include_files": []
|
||||
},
|
||||
"optimization": {
|
||||
"language_standard": "gnu99",
|
||||
"other_optimization_flags": ""
|
||||
},
|
||||
"warnings": {
|
||||
"warn_if_a_global_function_has_no_prototype": false,
|
||||
"warn_if_a_function_has_no_arg_type": false,
|
||||
"warn_if_wrong_cast": false,
|
||||
"other_warning_flags": ""
|
||||
},
|
||||
"miscellaneous": {
|
||||
"generate_assembler_listing": false,
|
||||
"save_temporary_files": false,
|
||||
"verbose": false,
|
||||
"other_compiler_flags": ""
|
||||
}
|
||||
},
|
||||
"cppcompiler": {
|
||||
"preprocessor": {
|
||||
"do_not_search_system_directories": false,
|
||||
"do_not_search_system_cpp_directories": false,
|
||||
"preprocess_only": false,
|
||||
"defined_symbols": [],
|
||||
"undefined_symbols": []
|
||||
},
|
||||
"includes": {
|
||||
"include_paths": [],
|
||||
"include_system_paths": [],
|
||||
"include_files": []
|
||||
},
|
||||
"optimization": {
|
||||
"cpp_language_standard": "gnucpp11",
|
||||
"abi_version": "0",
|
||||
"do_not_use_exceptions": false,
|
||||
"do_not_use_rtti": false,
|
||||
"do_not_use__cxa_atexit": false,
|
||||
"do_not_use_thread_safe_statics": false,
|
||||
"other_optimization_flags": ""
|
||||
},
|
||||
"warnings": {
|
||||
"warn_on_abi_violations": false,
|
||||
"warn_on_class_privacy": false,
|
||||
"warn_on_no_except_expressions": false,
|
||||
"warn_on_virtual_destructors": false,
|
||||
"warn_on_uncast_null": false,
|
||||
"warn_on_sign_promotion": false,
|
||||
"warn_about_effictive_cpp_violcations": false,
|
||||
"other_warning_flags": ""
|
||||
},
|
||||
"miscellaneous": {
|
||||
"generate_assembler_listing": false,
|
||||
"save_temporary_files": false,
|
||||
"verbose": false,
|
||||
"other_compiler_flags": ""
|
||||
}
|
||||
},
|
||||
"clinker": {
|
||||
"general": {
|
||||
"scriptFiles": [
|
||||
"${project}/Ld/Link.ld"
|
||||
],
|
||||
"do_not_use_standard_start_files": true,
|
||||
"do_not_use_default_libraries": false,
|
||||
"no_startup_or_default_libs": false,
|
||||
"remove_unused_sections": true,
|
||||
"print_removed_sections": false,
|
||||
"omit_all_symbol_information": false
|
||||
},
|
||||
"libraries": {
|
||||
"libraries": [],
|
||||
"library_search_path": []
|
||||
},
|
||||
"miscellaneous": {
|
||||
"picolibc": "disabled",
|
||||
"linker_flags": [],
|
||||
"other_objects": [],
|
||||
"generate_map": "\"${BuildArtifactFileBaseName}.map\"",
|
||||
"cross_reference": false,
|
||||
"print_link_map": false,
|
||||
"use_newlib_nano": true,
|
||||
"use_float_with_nano_printf": false,
|
||||
"use_float_with_nano_scanf": false,
|
||||
"do_not_use_syscalls": true,
|
||||
"verbose": false,
|
||||
"use_wch_printffloat": false,
|
||||
"use_wch_printf": false,
|
||||
"use_iqmath": false,
|
||||
"other_linker_flags": ""
|
||||
}
|
||||
},
|
||||
"cpplinker": {
|
||||
"general": {
|
||||
"scriptFiles": [
|
||||
"${project}/Ld/Link.ld"
|
||||
],
|
||||
"do_not_use_standard_start_files": true,
|
||||
"do_not_use_default_libraries": false,
|
||||
"no_startup_or_default_libs": false,
|
||||
"remove_unused_sections": true,
|
||||
"print_removed_sections": false,
|
||||
"omit_all_symbol_information": false
|
||||
},
|
||||
"libraries": {
|
||||
"libraries": [],
|
||||
"library_search_path": []
|
||||
},
|
||||
"miscellaneous": {
|
||||
"picolibc": "disabled",
|
||||
"linker_flags": [],
|
||||
"other_objects": [],
|
||||
"generate_map": "\"${BuildArtifactFileBaseName}.map\"",
|
||||
"cross_reference": false,
|
||||
"print_link_map": false,
|
||||
"use_newlib_nano": true,
|
||||
"use_float_with_nano_printf": false,
|
||||
"use_float_with_nano_scanf": false,
|
||||
"do_not_use_syscalls": true,
|
||||
"verbose": false,
|
||||
"use_wch_printffloat": false,
|
||||
"use_wch_printf": false,
|
||||
"use_iqmath": false,
|
||||
"other_linker_flags": ""
|
||||
}
|
||||
},
|
||||
"archiver": {
|
||||
"archiver_flags": "-r"
|
||||
},
|
||||
"createFlash": {
|
||||
"enabled": true,
|
||||
"outputFileFormat": "ihex",
|
||||
"copy_only_section_text": false,
|
||||
"copy_only_section_data": false,
|
||||
"copy_only_sections": [],
|
||||
"other_flags": ""
|
||||
},
|
||||
"createList": {
|
||||
"enabled": true,
|
||||
"display_source": false,
|
||||
"display_all_headers": true,
|
||||
"demangle_names": true,
|
||||
"display_debug_info": false,
|
||||
"disassemble": true,
|
||||
"display_file_headers": false,
|
||||
"display_line_numbers": false,
|
||||
"display_relocation_info": false,
|
||||
"display_symbols": false,
|
||||
"wide_lines": false,
|
||||
"other_flags": ""
|
||||
},
|
||||
"printSize": {
|
||||
"enabled": true,
|
||||
"size_format": "berkeley",
|
||||
"hex": false,
|
||||
"show_totals": false,
|
||||
"other_flags": ""
|
||||
},
|
||||
"configVariables": [],
|
||||
"riscvTargetProcessor": {
|
||||
"architecture": "rv32i",
|
||||
"multiply_extension": true,
|
||||
"atomic_extension": true,
|
||||
"floating_point": "none",
|
||||
"compressed_extension": true,
|
||||
"extra_compressed_extension": true,
|
||||
"bit_extension": false,
|
||||
"multiplication_subset_of_the_M_extension": false,
|
||||
"integer_ABI": "ilp32",
|
||||
"floating_point_ABI": "none",
|
||||
"tuning": "default",
|
||||
"code_model": "default",
|
||||
"small_data_limit": 8,
|
||||
"align": "default",
|
||||
"save_restore": true,
|
||||
"other_target_flags": ""
|
||||
},
|
||||
"component_toolchain": "${WCH:Toolchain:GCC8}",
|
||||
"name": "obj"
|
||||
}
|
||||
]
|
||||
},
|
||||
"flashConfig": {
|
||||
"mcutype": "CH32V20x",
|
||||
"address": "0x08000000",
|
||||
"target_path": "obj/Stop_Lp_Repeat_RTCwkup_02.hex",
|
||||
"clkSpeed": "High",
|
||||
"debug_interface_mode": "1-wire serial",
|
||||
"erase": true,
|
||||
"program": true,
|
||||
"verify": true,
|
||||
"reset": true,
|
||||
"sdiPrintf": false,
|
||||
"disablepowerout": false,
|
||||
"clearcodeflash": false,
|
||||
"disablecodeprotect": false,
|
||||
"exepath": "",
|
||||
"exearguments": ""
|
||||
},
|
||||
"debugConfigurations": {
|
||||
"openOCDCfg": {
|
||||
"useLocalOpenOCD": true,
|
||||
"executable": "${WCH:OpenOCD:default}",
|
||||
"gdbport": 3333,
|
||||
"telnetport": 4444,
|
||||
"tclport": 6666,
|
||||
"configOptions": [
|
||||
"-f \"${WCH:OpenOCD:default}/bin/wch-riscv.cfg\""
|
||||
],
|
||||
"host": "localhost",
|
||||
"port": 3333,
|
||||
"skipDownloadBeforeDebug": false,
|
||||
"enablePageEraser": false,
|
||||
"enableNoZeroWaitingAreaFlash": false
|
||||
},
|
||||
"gdbCfg": {
|
||||
"executable": "${WCH:Toolchain:GCC8}",
|
||||
"options": [],
|
||||
"commands": [
|
||||
"set mem inaccessible-by-default off",
|
||||
"set architecture riscv:rv32",
|
||||
"set remotetimeout unlimited",
|
||||
"set disassembler-options xw"
|
||||
]
|
||||
},
|
||||
"startup": {
|
||||
"initCommands": {
|
||||
"initReset": true,
|
||||
"initResetType": "init",
|
||||
"additionalCommands": [],
|
||||
"armSemihosting": false,
|
||||
"armSemihosting_old": false
|
||||
},
|
||||
"loadedFiles": {
|
||||
"loadSymbols": true,
|
||||
"useProjBinaryForSymbols": true,
|
||||
"useFileForSymbols": false,
|
||||
"symbolFile": "",
|
||||
"symbolFileOffset": "",
|
||||
"loadImage": true,
|
||||
"useProjBinaryForImage": true,
|
||||
"useFileForImage": false,
|
||||
"executableFile": "",
|
||||
"executableFileOffset": ""
|
||||
},
|
||||
"runCommands": {
|
||||
"runReset": true,
|
||||
"runResetType": "halt",
|
||||
"additionalCommands": [],
|
||||
"setBreakAt": "handle_reset",
|
||||
"continue": true,
|
||||
"setBreak": true,
|
||||
"setProgramCounter": false,
|
||||
"setProgramCounterAddress": ""
|
||||
},
|
||||
"debugInRAM": false
|
||||
},
|
||||
"svdpath": "${WCH:SDK:default}/RISC-V/CH32V203/NoneOS/CH32V203xx.svd",
|
||||
"output": {
|
||||
"showDebugGDBTrace": true,
|
||||
"saveDebugOutputToFile": false,
|
||||
"showDebugOutputTimestamps": true
|
||||
},
|
||||
"reserve": {
|
||||
"PROGRAM_NAME": "obj/Stop_Lp_Repeat_RTCwkup_02.elf",
|
||||
"PROJECT_ATTR": "Stop_Lp_Repeat_RTCwkup_02",
|
||||
"PROJECT_BUILD_CONFIG_AUTO_ATTR": true,
|
||||
"PROJECT_BUILD_CONFIG_ID_ATTR": "",
|
||||
"ATTR_BUILD_BEFORE_LAUNCH_ATTR": 2,
|
||||
"GdbServerAllocateConsole": true,
|
||||
"GdbServerAllocateTelnetConsole": false,
|
||||
"StartGdbCLient": true,
|
||||
"UPDATE_THREADLIST_ON_SUSPEND": false
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,49 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/12/29
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_it.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,442 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2025/09/29
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
/*
|
||||
*@Note
|
||||
* Stop Mode:
|
||||
* The example demonstrates WFI\WFE enter the STOP-Regulator_On mode or the STOP-Regulator_LowPower mode.
|
||||
* In the example, the RTC alarm clock serves as the wake-up source. By setting the frequency division coefficient of
|
||||
* the RTC clock and the alarm value, the system is awakened at regular intervals based on the set alarm time.
|
||||
* When using the STOP-Regulator_LowPower mode, The LDO and ULLDO need to be adjusted before the system
|
||||
* enters the stop mode and restored first after waking up.If the program is running in a non-zero wait state,
|
||||
* the sleep part of the program needs to be placed in RAM for execution(add prefix __attribute__((section("highcode")))
|
||||
* before function,printf functions and C function library is not applicable to run in RAM.).
|
||||
*
|
||||
*/
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
/* Global define */
|
||||
|
||||
/* definition of voltage regulator mode in stop mode */
|
||||
#define STOP_On_Mode 0
|
||||
#define STOP_LowPower_Mode 1
|
||||
#define STOP_Mode STOP_On_Mode
|
||||
// #define STOP_Mode STOP_LowPower_Mode
|
||||
|
||||
/* definition of program operate area */
|
||||
#define RunIn_ZeroWaitArea 0
|
||||
#define RunIn_NonZeroWaitArea 1
|
||||
#define Operating_Area_Type RunIn_ZeroWaitArea
|
||||
// #define Operating_Area_Type RunIn_NonZeroWaitArea
|
||||
|
||||
/* definition of execute with WFI or WFE */
|
||||
#define Enter_WFI_Mode 0
|
||||
#define Enter_WFE_Mode 1
|
||||
// #define Enter_Mode Enter_WFI_Mode
|
||||
#define Enter_Mode Enter_WFE_Mode
|
||||
|
||||
/* Global Variable */
|
||||
volatile uint32_t REGPSC, REGCNT, REGALR = 0;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_Alarm_WakeUp
|
||||
*
|
||||
* @brief Initializes RTC alarm wake-up function.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_Alarm_WakeUp(void)
|
||||
{
|
||||
EXTI_InitTypeDef EXTI_InitStructure = {0};
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
|
||||
PWR_BackupAccessCmd(ENABLE);
|
||||
RTC_ClearITPendingBit(RTC_IT_ALR);
|
||||
RTC_ClearITPendingBit(RTC_IT_SEC);
|
||||
/* Enable LSI oscillator */
|
||||
RCC_LSICmd(ENABLE);
|
||||
while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) != SET);
|
||||
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
|
||||
|
||||
/* Enable the RTC clock */
|
||||
RCC_RTCCLKCmd(ENABLE);
|
||||
RTC_WaitForLastTask();
|
||||
RTC_WaitForSynchro();
|
||||
/* Enable alarm interrupt */
|
||||
RTC_ITConfig( RTC_IT_ALR, ENABLE );
|
||||
RTC_WaitForLastTask();
|
||||
RTC_EnterConfigMode();
|
||||
/* Set the RTC prescaler value */
|
||||
RTC_SetPrescaler(32767);
|
||||
RTC_WaitForLastTask();
|
||||
RTC_SetCounter(0);
|
||||
RTC_WaitForLastTask();
|
||||
RTC_ExitConfigMode();
|
||||
#if(Enter_Mode == Enter_WFI_Mode)
|
||||
/* Enable the RTC alarm interrupt */
|
||||
NVIC_SetPriority(RTCAlarm_IRQn, 1);
|
||||
NVIC_EnableIRQ(RTCAlarm_IRQn);
|
||||
#endif
|
||||
/* Configure EXTI line */
|
||||
EXTI_InitStructure.EXTI_Line = EXTI_Line17;
|
||||
#if(Enter_Mode == Enter_WFI_Mode)
|
||||
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
#elif(Enter_Mode == Enter_WFE_Mode)
|
||||
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
|
||||
#endif
|
||||
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
|
||||
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||||
EXTI_Init(&EXTI_InitStructure);
|
||||
/* Set the RTC alarm value */
|
||||
RTC_SetAlarm(RTC_GetCounter()+5);
|
||||
RTC_WaitForLastTask();
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ALL_IPD
|
||||
*
|
||||
* @brief Set all pins mode to pull-down.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_ALL_IPD(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
/* To reduce power consumption, unused GPIOs need to be set as pull-down inputs */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_GPIOB|RCC_APB2Periph_GPIOC|
|
||||
RCC_APB2Periph_GPIOD|RCC_APB2Periph_AFIO, ENABLE);
|
||||
GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LDO_Deal
|
||||
*
|
||||
* @brief Deal LDO ULLDO mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
#if(Operating_Area_Type == RunIn_NonZeroWaitArea)
|
||||
__attribute__((section(".highcode")))
|
||||
#endif
|
||||
void LDO_Deal(void)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
REGPSC = 0;
|
||||
REGALR = 0;
|
||||
REGCNT = 0;
|
||||
if((uint8_t)((*(vu32*)0x4002203C >> 24) & 0xFF) != 0xAB)
|
||||
{
|
||||
if((RCC->APB1PCENR & (1 << 27)) == RESET)
|
||||
{
|
||||
RCC->APB1PCENR |= (1 << 27);
|
||||
REGPSC |= (1 << 27);
|
||||
}
|
||||
if((PWR->CTLR & (1 << 8)) == RESET)
|
||||
{
|
||||
PWR->CTLR |= (1 << 8);
|
||||
REGPSC |= (1 << 26);
|
||||
}
|
||||
if((EXTI->EVENR & (1 << 17)) == RESET)
|
||||
{
|
||||
EXTI->EVENR |= (1 << 17);
|
||||
REGPSC |= (1 << 25);
|
||||
}
|
||||
if((EXTI->RTENR & (1 << 17)) == RESET)
|
||||
{
|
||||
EXTI->RTENR |= (1 << 17);
|
||||
REGPSC |= (1 << 24);
|
||||
}
|
||||
|
||||
if((RCC->BDCTLR & (1 << 15)) == RESET)
|
||||
{
|
||||
if((RCC->RSTSCKR & (1 << 1)) == RESET) REGPSC |= (1 << 30);
|
||||
|
||||
if((RCC->BDCTLR & (1 << 8)) == RESET)
|
||||
{
|
||||
RCC->RSTSCKR |= (1 << 0);
|
||||
while ((RCC->RSTSCKR & (1 << 1)) == RESET);
|
||||
RCC->BDCTLR |= (1 << 9);
|
||||
}
|
||||
REGPSC |= (1 << 29);
|
||||
}
|
||||
}
|
||||
REGPSC |= (0xF << 20);
|
||||
|
||||
tmpreg = EXTEN->EXTEN_CTR;
|
||||
tmpreg &= ~(0xF << 8);
|
||||
tmpreg |= (0x3 << 8);
|
||||
EXTEN->EXTEN_CTR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LDO_Restore
|
||||
*
|
||||
* @brief Restore LDO Value.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
#if(Operating_Area_Type == RunIn_NonZeroWaitArea)
|
||||
__attribute__((section(".highcode")))
|
||||
#endif
|
||||
void LDO_Restore(void)
|
||||
{
|
||||
uint32_t tmpreg = 0, t = 0;
|
||||
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||
uint16_t low1 = 0, low2 = 0;
|
||||
|
||||
if((REGPSC & 0xF00000) == (uint32_t)0xF00000)
|
||||
{
|
||||
tmpreg = EXTEN->EXTEN_CTR;
|
||||
tmpreg &= ~(0xF << 8);
|
||||
tmpreg |= (0xA << 8);
|
||||
EXTEN->EXTEN_CTR = tmpreg;
|
||||
if(((*(vu32*)0x4002203C >> 24) & 0xFF) != 0xAB)
|
||||
{
|
||||
RCC->BDCTLR |= (1 << 15);
|
||||
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||
while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET);
|
||||
|
||||
REGPSC |= (((RTC->PSCRH & 0xF) << 16) | RTC->PSCRL);
|
||||
REGALR = (RTC->ALRMH << 16 | RTC->ALRML);
|
||||
do{
|
||||
high1a = RTC->CNTH;
|
||||
high1b = RTC->CNTH;
|
||||
}while(high1a != high1b);
|
||||
do{
|
||||
low1 = RTC->CNTL;
|
||||
low2 = RTC->CNTL;
|
||||
}while(low1 != low2);
|
||||
do{
|
||||
high2a = RTC->CNTH;
|
||||
high2b = RTC->CNTH;
|
||||
}while(high2a != high2b);
|
||||
if(high1b != high2b) {
|
||||
do{
|
||||
low1 = RTC->CNTL;
|
||||
low2 = RTC->CNTL;
|
||||
}while(low1 != low2);
|
||||
}
|
||||
REGCNT = (((uint32_t)high2b << 16) | low2);
|
||||
|
||||
RTC->CTLRL |= (1 << 4);
|
||||
RTC->PSCRH = 0;
|
||||
RTC->PSCRL = 1;
|
||||
RTC->CNTH = 0;
|
||||
RTC->CNTL = 0;
|
||||
RTC->ALRMH = 0;
|
||||
RTC->ALRML = 1;
|
||||
RTC->CTLRL &= (uint16_t) ~(1 << 4);
|
||||
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET);
|
||||
|
||||
PWR->CTLR &= ~(3 << 0);
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
NVIC->SCTLR |= (1 << 5);
|
||||
t = NVIC->SCTLR;
|
||||
t &= ~(1 << 5);
|
||||
t |= (1 << 3);
|
||||
NVIC->SCTLR = t;
|
||||
asm volatile ("wfi");
|
||||
t = NVIC->SCTLR;
|
||||
t &= ~(1 << 5);
|
||||
t |= (1 << 3);
|
||||
NVIC->SCTLR = t;
|
||||
asm volatile ("wfi");
|
||||
if(EXTEN->EXTEN_CTR & (1 << 6))
|
||||
{
|
||||
NVIC->SCTLR |= (1 << 5);
|
||||
}
|
||||
NVIC->SCTLR &= ~(1 << 2);
|
||||
|
||||
RTC->CTLRL |= (1 << 4);
|
||||
RTC->PSCRH = (uint16_t)((REGPSC >> 16) & 0xF);
|
||||
RTC->PSCRL = (uint16_t)(REGPSC & 0xFFFF);
|
||||
RTC->CNTH = (uint16_t)(REGCNT >> 16);
|
||||
RTC->CNTL = (uint16_t)(REGCNT & 0xFFFF);
|
||||
RTC->ALRMH = (uint16_t)(REGALR >> 16);
|
||||
RTC->ALRML = (uint16_t)(REGALR & 0xFFFF);
|
||||
RTC->CTLRL &= (uint16_t) ~(1 << 4);
|
||||
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET);
|
||||
|
||||
if(REGPSC & (1 << 29)) RCC->BDCTLR &= ~(1 << 15);
|
||||
if(REGPSC & (1 << 30)) RCC->RSTSCKR &= ~(1 << 0);
|
||||
if(REGPSC & (1 << 27)) RCC->APB1PCENR &= ~(1 << 27);
|
||||
if(REGPSC & (1 << 26)) PWR->CTLR &= ~(1 << 8);
|
||||
if(REGPSC & (1 << 25)) EXTI->EVENR &= ~(1 << 17);
|
||||
if(REGPSC & (1 << 24)) EXTI->RTENR &= ~(1 << 17);
|
||||
}
|
||||
else
|
||||
{
|
||||
FLASH->CTLR |= (1 << 23);
|
||||
}
|
||||
REGPSC &= ~(0xF << 20);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Enter_StopLowPower
|
||||
*
|
||||
* @brief Enter stop low-power mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
#if(Operating_Area_Type == RunIn_NonZeroWaitArea)
|
||||
__attribute__((section(".highcode")))
|
||||
#endif
|
||||
void Enter_StopLowPower(void)
|
||||
{
|
||||
/* The kernel voltage needs to be adjusted before waking up */
|
||||
LDO_Deal();
|
||||
|
||||
#if (Operating_Area_Type == RunIn_NonZeroWaitArea)
|
||||
|
||||
#if (Enter_Mode == Enter_WFI_Mode)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= ~(0x3);
|
||||
tmpreg |= 0x1;
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
NVIC->SCTLR &= ~(1 << 3);
|
||||
asm volatile ("wfi");
|
||||
NVIC->SCTLR &= ~(1 << 2);
|
||||
}
|
||||
#else
|
||||
{
|
||||
uint32_t tmpreg = 0, t=0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= ~(0x3);
|
||||
tmpreg |= 0x1;
|
||||
PWR->CTLR = tmpreg;
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
NVIC->SCTLR |= (1 << 5);
|
||||
t = NVIC->SCTLR;
|
||||
t &= ~(1 << 5);
|
||||
t |= (1 << 3);
|
||||
NVIC->SCTLR = t;
|
||||
asm volatile ("wfi");
|
||||
t = NVIC->SCTLR;
|
||||
t &= ~(1 << 5);
|
||||
t |= (1 << 3);
|
||||
NVIC->SCTLR = t;
|
||||
asm volatile ("wfi");
|
||||
if(EXTEN->EXTEN_CTR & (1 << 6))
|
||||
{
|
||||
NVIC->SCTLR |= (1 << 5);
|
||||
}
|
||||
NVIC->SCTLR &= ~(1 << 2);
|
||||
}
|
||||
#endif
|
||||
|
||||
#elif (Operating_Area_Type == RunIn_ZeroWaitArea)
|
||||
|
||||
#if (Enter_Mode == Enter_WFI_Mode)
|
||||
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
|
||||
#else
|
||||
PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFE);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (Enter_Mode == Enter_WFE_Mode)
|
||||
/* The kernel voltage must be restored first after waking up */
|
||||
LDO_Restore();
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
|
||||
SystemCoreClockUpdate();
|
||||
Delay_Init();
|
||||
Delay_Ms(1000);
|
||||
GPIO_ALL_IPD();
|
||||
USART_Printf_Init(115200);
|
||||
printf("SystemClk:%d\r\n", SystemCoreClock);
|
||||
printf("ChipID:%08x\r\n", DBGMCU_GetCHIPID() );
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
printf("\r\nenter stop mode ...\r\n");
|
||||
|
||||
RTC_Alarm_WakeUp();
|
||||
|
||||
#if (STOP_Mode == STOP_On_Mode)
|
||||
#if (Enter_Mode == Enter_WFI_Mode)
|
||||
PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
|
||||
#else
|
||||
PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFE);
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#else
|
||||
Enter_StopLowPower();
|
||||
#endif
|
||||
|
||||
Delay_Ms(100);
|
||||
printf("\r\n#####################\r\n");
|
||||
printf("wake up !!!\r\n");
|
||||
while(1)
|
||||
{
|
||||
Delay_Ms(1000);
|
||||
printf("run in main\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
#if (Enter_Mode == Enter_WFI_Mode)
|
||||
void RTCAlarm_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
/*********************************************************************
|
||||
* @fn RTCAlarm_IRQHandler
|
||||
*
|
||||
* @brief This function handles RTCAlarm Handler.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
#if(Operating_Area_Type == RunIn_NonZeroWaitArea)
|
||||
__attribute__((section(".highcode")))
|
||||
#endif
|
||||
void RTCAlarm_IRQHandler(void)
|
||||
{
|
||||
#if(STOP_Mode == STOP_LowPower_Mode)
|
||||
/* After waking up, the kernel voltage needs to be restored first */
|
||||
LDO_Restore();
|
||||
#endif
|
||||
SystemInit();
|
||||
if((EXTI->INTFR & EXTI_Line17))
|
||||
{
|
||||
/* Clear Flag */
|
||||
EXTI->INTFR = EXTI_Line17;
|
||||
RTC->CTLRL &= (uint16_t)~RTC_IT_ALR;
|
||||
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,987 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
|
||||
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
//GPIO_IPD_Unused();
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user