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qiyongshuang
2026-01-07 10:43:29 +08:00
parent 6209b6e7f9
commit d161f84c90
551 changed files with 23169 additions and 1518 deletions
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EVT/EXAM/SRC/Core/core_riscv.h
+4 -2
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.1
* Date : 2023/11/11
* Version : V1.0.2
* Date : 2025/04/28
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -142,6 +142,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
__asm volatile ("fence.i");
}
/*********************************************************************
@@ -182,6 +183,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Typ
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
__asm volatile ("fence.i");
}
/*********************************************************************
EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+9 -11
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/07/04
* Version : V1.0.1
* Date : 2025/11/04
* Description : CH32V20x Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -18,7 +18,7 @@ extern "C" {
#if !defined(CH32V20x_D8W) && !defined(CH32V20x_D8) && !defined(CH32V20x_D6)
#define CH32V20x_D6 /* CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8*/
//#define CH32V20x_D8 /* CH32V203RBT6 */
//#define CH32V20x_D8 /* CH32V203RBT */
//#define CH32V20x_D8W /* CH32V208 */
#endif
@@ -30,7 +30,11 @@ extern "C" {
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define HSE_VALUE ((uint32_t)32000000) /* Value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
#if defined(HSE_VALUE_12M)
#define HSE_VALUE ((uint32_t)12000000) /* Value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
#endif
#endif
#endif
@@ -41,7 +45,7 @@ extern "C" {
/* CH32V20x Standard Peripheral Library version number */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x03) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
@@ -841,9 +845,6 @@ typedef struct
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
@@ -898,9 +899,6 @@ typedef struct
#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
#define TKey1 ((ADC_TypeDef *)ADC1_BASE)
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_dbgmcu.h
+1 -6
View File
@@ -31,13 +31,8 @@ extern "C" {
#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000)
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000)
#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000)
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_dma.h
+2 -2
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dma.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Version : V1.0.1
* Date : 2025/04/28
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
*********************************************************************************
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h
+1 -1
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@@ -90,7 +90,7 @@ typedef enum
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x80000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h
+2 -20
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/07/23
* Version : V1.0.1
* Date : 2025/04/23
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*********************************************************************************
@@ -104,10 +104,8 @@ typedef enum
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
to TIM2 Internal Trigger 1 for calibration \
(only for Connectivity line devices) */
@@ -115,22 +113,9 @@ typedef enum
#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
/* PCFR2 */
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
/* GPIO_Port_Sources */
@@ -138,9 +123,6 @@ typedef enum
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
/* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00)
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_rcc.h
+3 -14
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/02/21
* Version : V1.0.1
* Date : 2025/04/26
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -140,38 +140,27 @@ typedef struct
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_tim.h
+92 -7
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_tim.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Version : V1.0.1
* Date : 2025/04/26
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
*********************************************************************************
@@ -42,7 +42,7 @@ typedef struct
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1 . */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
@@ -56,7 +56,7 @@ typedef struct
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1 . */
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
@@ -66,17 +66,79 @@ typedef struct
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
} TIM_OCInitTypeDef;
#if defined (CH32V20x_D8) || defined(CH32V20x_D8W)
typedef struct
{
uint32_t TIM_Period; /* Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFFFFFF. */
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_CounterMode; /* Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint16_t TIM_ClockDivision; /* Specifies the clock division.
This parameter can be a value of @ref TIM_Clock_Division_CKD */
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 . */
} TIM5_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
uint32_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFFFFFF */
uint16_t TIM_OCMode; /* Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 . */
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1. */
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1. */
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1. */
} TIM5_OCInitTypeDef;
#endif
/* TIM Input Capture Init structure definition */
typedef struct
{
@@ -501,6 +563,29 @@ void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
#if defined (CH32V20x_D8) || defined(CH32V20x_D8W)
void TIM5_TimeBaseInit(TIM_TypeDef *TIMx, TIM5_TimeBaseInitTypeDef *TIM5_TimeBaseInitStruct);
void TIM5_OC1Init(TIM_TypeDef *TIMx, TIM5_OCInitTypeDef *TIM5_OCInitStruct);
void TIM5_OC2Init(TIM_TypeDef *TIMx, TIM5_OCInitTypeDef *TIM5_OCInitStruct);
void TIM5_OC3Init(TIM_TypeDef *TIMx, TIM5_OCInitTypeDef *TIM5_OCInitStruct);
void TIM5_OC4Init(TIM_TypeDef *TIMx, TIM5_OCInitTypeDef *TIM5_OCInitStruct);
void TIM5_TimeBaseStructInit(TIM5_TimeBaseInitTypeDef *TIM5_TimeBaseInitStruct);
void TIM5_OCStructInit(TIM5_OCInitTypeDef *TIM5_OCInitStruct);
void TIM5_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter);
void TIM5_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload);
void TIM5_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1);
void TIM5_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2);
void TIM5_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3);
void TIM5_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4);
uint32_t TIM5_GetCapture1(TIM_TypeDef *TIMx);
uint32_t TIM5_GetCapture2(TIM_TypeDef *TIMx);
uint32_t TIM5_GetCapture3(TIM_TypeDef *TIMx);
uint32_t TIM5_GetCapture4(TIM_TypeDef *TIMx);
uint32_t TIM5_GetCounter(TIM_TypeDef *TIMx);
#endif
#ifdef __cplusplus
}
#endif
EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c
+3 -8
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_can.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Version : V1.0.1
* Date : 2025/04/26
* Description : This file provides all the CAN firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -55,7 +55,7 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
* @brief Deinitializes the CAN peripheral registers to their default reset
* values.
*
* @param CANx - where x can be 1 or 2 to select the CAN peripheral.
* @param CANx - where x can be 1 to select the CAN peripheral.
*
* @return none
*/
@@ -66,11 +66,6 @@ void CAN_DeInit(CAN_TypeDef* CANx)
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
}
else
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
}
}
/*********************************************************************
EVT/EXAM/SRC/Peripheral/src/ch32v20x_dbgmcu.c
+16 -16
View File
@@ -22,7 +22,7 @@
*/
uint32_t DBGMCU_GetREVID(void)
{
return ((*(uint32_t *)0x1FFFF704) >> 16);
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
}
/*********************************************************************
@@ -34,7 +34,7 @@ uint32_t DBGMCU_GetREVID(void)
*/
uint32_t DBGMCU_GetDEVID(void)
{
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
return ((*(uint32_t *)0x1FFFF704) >> 16);
}
/*********************************************************************
@@ -105,20 +105,20 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
*
* @return Device identifier.
* ChipID List-
* CH32V203C8U6-0x203005x0
* CH32V203C8T6-0x203105x0
* CH32V203K8T6-0x203205x0
* CH32V203C6T6-0x203305x0
* CH32V203G6U6-0x203605x0
* CH32V203G8R6-0x203B05x0
* CH32V203F8U6-0x203E05x0
* CH32V203F6P6-0x203705x0-0x203905x0
* CH32V203F8P6-0x203A05x0
* CH32V203RBT6-0x203405xC
* CH32V208WBU6-0x208005xC
* CH32V208RBT6-0x208105xC
* CH32V208CBU6-0x208205xC
* CH32V208GBU6-0x208305xC
* CH32V203C8U-0x203005x0
* CH32V203C8T-0x203105x0
* CH32V203K8T-0x203205x0
* CH32V203C6T-0x203305x0
* CH32V203G6U-0x203605x0
* CH32V203G8R-0x203B05x0
* CH32V203F8U-0x203D05x0
* CH32V203F6P-0x203705x0-0x203905x0
* CH32V203F8P-0x203A05x0
* CH32V203RBT-0x203405xC
* CH32V208WBU-0x208005xC
* CH32V208RBT-0x208105xC
* CH32V208CBU-0x208205xC
* CH32V208GBU-0x208305xC
*/
uint32_t DBGMCU_GetCHIPID( void )
{
EVT/EXAM/SRC/Peripheral/src/ch32v20x_dma.c
+32 -32
View File
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dma.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Version : V1.0.1
* Date : 2025/04/28
* Description : This file provides all the DMA firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -34,8 +34,8 @@
* @brief Deinitializes the DMAy Channelx registers to their default
* reset values.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 select the DMA Channel.
*
* @return none
*/
@@ -86,8 +86,8 @@ void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
@@ -115,8 +115,8 @@ void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruc
*
* @brief Fills each DMA_InitStruct member with its default value.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
@@ -142,8 +142,8 @@ void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
*
* @brief Enables or disables the specified DMAy Channelx.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA to select the DMA Channel.
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
@@ -165,8 +165,8 @@ void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
*
* @brief Enables or disables the specified DMAy Channelx interrupts.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA to select the DMA Channel.
* DMA_IT - specifies the DMA interrupts sources to be enabled
* or disabled.
* DMA_IT_TC - Transfer complete interrupt mask
@@ -193,8 +193,8 @@ void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, Functiona
*
* @brief Sets the number of data units in the current DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA to select the DMA Channel.
* DataNumber - The number of data units in the current DMAy Channelx
* transfer.
*
@@ -211,8 +211,8 @@ void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNum
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA to select the DMA Channel.
*
* @return DataNumber - The number of remaining data units in the current
* DMAy Channelx transfer.
@@ -256,10 +256,10 @@ uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* DMA1_FLAG_GL8 - DMA1 Channel8 global flag.
* DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag.
* @return The new state of DMAy_FLAG (SET or RESET).
*/
@@ -316,10 +316,10 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* DMA1_FLAG_GL8 - DMA1 Channel8 global flag.
* DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag.
* @return none
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
@@ -362,10 +362,10 @@ void DMA_ClearFlag(uint32_t DMAy_FLAG)
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* DMA1_IT_GL8 - DMA1 Channel8 global flag.
* DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_IT_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_IT_TE8 - DMA1 Channel8 transfer error flag.
* @return The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
@@ -420,10 +420,10 @@ ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* DMA1_IT_GL8 - DMA1 Channel8 global flag.
* DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_IT_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_IT_TE8 - DMA1 Channel8 transfer error flag.
* @return none
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c
+17 -5
View File
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_flash.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Version : V1.0.1
* Date : 2025/01/09
* Description : This file provides all the FLASH firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -56,7 +56,7 @@
#define EEPROM_ADDRESS ((uint32_t)0x8070000)
/* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000)
#define EraseTimeout ((uint32_t)0x00130000)
#define ProgramTimeout ((uint32_t)0x00005000)
/* Flash Program Valid Address */
@@ -73,6 +73,9 @@
#define Size_4KB 0x1000
#define Size_32KB 0x8000
#define FLASH_EraseAll_Delay(t) ({for(uint32_t i = 0; i<t; i++){asm("nop");}})
/*********************************************************************
* @fn FLASH_Unlock
*
@@ -177,7 +180,11 @@ FLASH_Status FLASH_EraseAllPages(void)
FLASH->CTLR &= CR_MER_Reset;
}
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
FLASH_EraseAll_Delay(180000);
#else
FLASH_EraseAll_Delay(150000);
#endif
return status;
}
@@ -203,6 +210,11 @@ FLASH_Status FLASH_EraseAllBank1Pages(void)
FLASH->CTLR &= CR_MER_Reset;
}
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
FLASH_EraseAll_Delay(180000);
#else
FLASH_EraseAll_Delay(150000);
#endif
return status;
}
@@ -643,7 +655,7 @@ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
{
if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
if((FLASH->OBR & (1<<0)) != (uint32_t)RESET)
{
bitstatus = SET;
}
EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c
+27 -46
View File
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_gpio.c
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/06
* Version : V1.0.1
* Date : 2025/04/26
* Description : This file provides all the GPIO firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -30,7 +30,7 @@ uint8_t MCU_Version = 0;
* @brief Deinitializes the GPIOx peripheral registers to their default
* reset values.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
*
* @return none
*/
@@ -56,11 +56,6 @@ void GPIO_DeInit(GPIO_TypeDef *GPIOx)
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
}
else if(GPIOx == GPIOE)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
}
}
/*********************************************************************
@@ -80,7 +75,7 @@ void GPIO_AFIODeInit(void)
/*********************************************************************
* @fn GPIO_Init
*
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @brief GPIOx - where x can be (A..D) to select the GPIO peripheral.
*
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO peripheral.
@@ -192,7 +187,7 @@ void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
/*********************************************************************
* @fn GPIO_ReadInputDataBit
*
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @brief GPIOx - where x can be (A..D) to select the GPIO peripheral.
*
* @param GPIO_Pin - specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
@@ -227,7 +222,7 @@ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
*
* @brief Reads the specified GPIO input data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
*
* @return The output port pin value.
*/
@@ -255,7 +250,7 @@ return ( val );
*
* @brief Reads the specified output data port bit.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
*
@@ -289,7 +284,7 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
*
* @brief Reads the specified GPIO output data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
*
* @return GPIO output port pin value.
*/
@@ -317,7 +312,7 @@ uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
*
* @brief Sets the selected data port bits.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
@@ -340,7 +335,7 @@ void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
*
* @brief Clears the selected data port bits.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
@@ -395,7 +390,7 @@ void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
*
* @brief Writes data to the specified GPIO data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
* PortVal - specifies the value to be written to the port output data register.
*
* @return none
@@ -417,7 +412,7 @@ void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
*
* @brief Locks GPIO Pins configuration registers.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @param GPIOx - where x can be (A..D) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
@@ -449,7 +444,7 @@ void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
*
* @param GPIO_PortSource - selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
* GPIO_PinSource - specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
*
@@ -515,28 +510,14 @@ void GPIO_EventOutputCmd(FunctionalState NewState)
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
* GPIO_Remap_ETH - Ethernet remapping
* GPIO_Remap_CAN2 - CAN2 remapping
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
* NewState - ENABLE or DISABLE.
*
@@ -623,7 +604,7 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
* @brief Selects the GPIO pin used as EXTI Line.
*
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
* GPIO_PinSource - specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
*
@@ -680,7 +661,7 @@ void GPIO_IPD_Unused(void)
switch(chip)
{
#ifdef CH32V20x_D6
case 0x20370500: //CH32V203F6P6
case 0x20370500: //CH32V203F6P
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_15;
@@ -712,7 +693,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203A0500: //CH32V203F8P6
case 0x203A0500: //CH32V203F8P
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11|GPIO_Pin_12\
@@ -746,7 +727,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203E0500: //CH32V203F8U6
case 0x203D0500: //CH32V203F8U
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
@@ -779,7 +760,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20360500: //CH32V203G6U6
case 0x20360500: //CH32V203G6U
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
@@ -810,7 +791,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203B0500: //CH32V203G8R6
case 0x203B0500: //CH32V203G8R
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
@@ -840,7 +821,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20320500: //CH32V203K8T6
case 0x20320500: //CH32V203K8T
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
@@ -868,7 +849,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20330500: //CH32V203C6T6
case 0x20330500: //CH32V203C6T
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
@@ -886,7 +867,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20310500: //CH32V203C8T6
case 0x20310500: //CH32V203C8T
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
@@ -904,7 +885,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20300500: //CH32V203C8U6
case 0x20300500: //CH32V203C8U
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
@@ -923,7 +904,7 @@ void GPIO_IPD_Unused(void)
break;
}
#elif defined(CH32V20x_D8)
case 0x2034050C: //CH32V203RBT6
case 0x2034050C: //CH32V203RBT
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6;
@@ -932,7 +913,7 @@ void GPIO_IPD_Unused(void)
break;
}
#elif defined(CH32V20x_D8W)
case 0x2083050C: //CH32V208GBU6
case 0x2083050C: //CH32V208GBU
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_15;
@@ -964,7 +945,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2082050C: //CH32V208CBU6
case 0x2082050C: //CH32V208CBU
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
@@ -982,7 +963,7 @@ void GPIO_IPD_Unused(void)
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2081050C: //CH32V208RBT6
case 0x2081050C: //CH32V208RBT
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6;
EVT/EXAM/SRC/Peripheral/src/ch32v20x_rcc.c
+2 -6
View File
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_rcc.c
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/30
* Version : V1.0.1
* Date : 2025/04/20
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -676,12 +676,10 @@ void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
* RCC_APB2Periph_GPIOB.
* RCC_APB2Periph_GPIOC.
* RCC_APB2Periph_GPIOD.
* RCC_APB2Periph_GPIOE
* RCC_APB2Periph_ADC1.
* RCC_APB2Periph_ADC2
* RCC_APB2Periph_TIM1.
* RCC_APB2Periph_SPI1.
* RCC_APB2Periph_TIM8
* RCC_APB2Periph_USART1.
* NewState - ENABLE or DISABLE
*
@@ -747,12 +745,10 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
* RCC_APB2Periph_GPIOB.
* RCC_APB2Periph_GPIOC.
* RCC_APB2Periph_GPIOD.
* RCC_APB2Periph_GPIOE
* RCC_APB2Periph_ADC1.
* RCC_APB2Periph_ADC2
* RCC_APB2Periph_TIM1.
* RCC_APB2Periph_SPI1.
* RCC_APB2Periph_TIM8
* RCC_APB2Periph_USART1.
* NewState - ENABLE or DISABLE
*
EVT/EXAM/SRC/Peripheral/src/ch32v20x_spi.c
+30 -30
View File
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_spi.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Version : V1.0.1
* Date : 2025/04/26
* Description : This file provides all the SPI firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -51,7 +51,7 @@
* @brief Deinitializes the SPIx peripheral registers to their default
* reset values (Affects also the I2Ss).
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
*
* @return none
*/
@@ -75,7 +75,7 @@ void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral.
*
@@ -103,7 +103,7 @@ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* (configured in I2S mode).
* I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral
@@ -226,7 +226,7 @@ void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
*
* @brief Enables or disables the specified SPI peripheral.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
@@ -248,7 +248,7 @@ void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
*
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
@@ -271,8 +271,8 @@ void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
* @brief Enables or disables the specified SPI/I2S interrupts.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
* enabled or disabled.
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
@@ -304,8 +304,8 @@ void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState New
* @brief Enables or disables the SPIx/I2Sx DMA interface.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
* be enabled or disabled.
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
@@ -332,8 +332,8 @@ void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* Data - Data to be transmitted.
*
* @return none
@@ -349,8 +349,8 @@ void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* Data - Data to be transmitted.
*
* @return SPIx->DATAR - The value of the received data.
@@ -365,7 +365,7 @@ uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
*
* @brief Configures internally by software the NSS pin for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* SPI_NSSInternalSoft -
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
@@ -389,7 +389,7 @@ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSo
*
* @brief Enables or disables the SS output for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* NewState - new state of the SPIx SS output.
*
* @return none
@@ -411,7 +411,7 @@ void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
*
* @brief Configures the data size for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* SPI_DataSize - specifies the SPI data size.
* SPI_DataSize_16b - Set data frame format to 16bit.
* SPI_DataSize_8b - Set data frame format to 8bit.
@@ -429,7 +429,7 @@ void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
*
* @brief Transmit the SPIx CRC value.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
*
* @return none
*/
@@ -443,7 +443,7 @@ void SPI_TransmitCRC(SPI_TypeDef *SPIx)
*
* @brief Enables or disables the CRC value calculation of the transferred bytes.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* NewState - new state of the SPIx CRC value calculation.
*
* @return none
@@ -465,7 +465,7 @@ void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
*
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* SPI_CRC - specifies the CRC register to be read.
* SPI_CRC_Tx - Selects Tx CRC register.
* SPI_CRC_Rx - Selects Rx CRC register.
@@ -493,7 +493,7 @@ uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
*
* @brief Returns the CRC Polynomial register value for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
*
* @return SPIx->CRCR - The CRC Polynomial register value.
*/
@@ -508,7 +508,7 @@ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
* @brief Selects the data transfer direction in bi-directional mode
* for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* @param SPIx - where x can be 1, 2 to select the SPI peripheral.
* SPI_Direction - specifies the data transfer direction in
* bi-directional mode.
* SPI_Direction_Tx - Selects Tx transmission direction.
@@ -534,8 +534,8 @@ void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
* @brief Checks whether the specified SPI/I2S flag is set or not.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
@@ -570,8 +570,8 @@ FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
* @brief Clears the SPIx CRC Error (CRCERR) flag.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* SPI_I2S_FLAG - specifies the SPI flag to clear.
* SPI_FLAG_CRCERR - CRC Error flag.
* Note-
@@ -596,8 +596,8 @@ void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* - 1, 2 in SPI mode.
* - 2 in I2S mode.
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
@@ -636,7 +636,7 @@ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 1, 2 in SPI mode.
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
* SPI_IT_CRCERR - CRC Error interrupt.
* Note-
EVT/EXAM/SRC/Peripheral/src/ch32v20x_tim.c
+475 -134
View File
File diff suppressed because it is too large Load Diff
EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c
+14 -9
View File
@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_usart.c
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/06
* Version : V1.0.1
* Date : 2025/09/11
* Description : This file provides all the USART firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -98,16 +98,12 @@ void USART_DeInit(USART_TypeDef *USARTx)
*/
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
{
uint32_t tmpreg = 0x00, apbclock = 0x00;
uint64_t tmpreg = 0x00, apbclock = 0x00;
uint32_t integerdivider = 0x00;
uint32_t fractionaldivider = 0x00;
uint32_t usartxbase = 0;
RCC_ClocksTypeDef RCC_ClocksStatus;
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
{
}
usartxbase = (uint32_t)USARTx;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_STOP_CLEAR_Mask;
@@ -138,8 +134,17 @@ void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
tmpreg = (integerdivider / 100) << 4;
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
USARTx->BRR = (uint16_t)tmpreg;
fractionaldivider = (((fractionaldivider * 16) + 50) / 100);
if (fractionaldivider > 0xf)
{
tmpreg += 1 << 4;
}
else
{
tmpreg |= fractionaldivider & ((uint8_t)0x0f);
}
USARTx->BRR = (uint16_t)tmpreg;
}
/*********************************************************************
EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S
+6 -6
View File
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D6.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2024/01/31
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
;* vector table for eclipse toolchain.
;* Version : V1.0.2
;* Date : 2025/10/21
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
;* Startup File.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -208,9 +208,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S
+5 -5
View File
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2024/01/31
;* Version : V1.0.2
;* Date : 2025/10/21
;* Description : CH32V203RB
;* vector table for eclipse toolchain.
;* Startup File.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -225,9 +225,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S
+5 -5
View File
@@ -1,10 +1,10 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8W.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2023/11/11
;* Version : V1.0.2
;* Date : 2025/10/21
;* Description : CH32V208x
;* vector table for eclipse toolchain.
;* Startup File
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
@@ -229,9 +229,9 @@ handle_reset:
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma