bstanwell/ch32v20x-examples
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qiyongshuang
2026-01-07 10:43:29 +08:00
parent 6209b6e7f9
commit d161f84c90
551 changed files with 23169 additions and 1518 deletions
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EVT/EXAM/SRC/Core/core_riscv.h
+4 -2
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@@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.1
* Date : 2023/11/11
* Version : V1.0.2
* Date : 2025/04/28
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -142,6 +142,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
__asm volatile ("fence.i");
}
/*********************************************************************
@@ -182,6 +183,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Typ
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
__asm volatile ("fence.i");
}
/*********************************************************************