From ec059e0b18046b111ee850e44f105fcd095e775c Mon Sep 17 00:00:00 2001
From: qiyongshuang <1210052066@qq.com>
Date: Fri, 1 Dec 2023 10:33:09 +0800
Subject: [PATCH] V1.9

---
 EVT/CH32V20x_List.txt                         |    55 +-
 EVT/CH32V20x_List_EN.txt                      |    51 +-
 EVT/EXAM/ADC/ADC_DMA/User/main.c              |     2 +-
 EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c   |     1 +
 .../ADC/AnalogWatchdog/User/system_ch32v20x.c |     1 +
 EVT/EXAM/ADC/Auto_Injection/User/main.c       |     3 +-
 .../ADC/Auto_Injection/User/system_ch32v20x.c |     1 +
 EVT/EXAM/ADC/Discontinuous_mode/User/main.c   |     4 +-
 .../Discontinuous_mode/User/system_ch32v20x.c |     1 +
 .../ADC/DualADC_AlternateTrigger/User/main.c  |     2 +-
 .../User/system_ch32v20x.c                    |     1 +
 .../User/main.c                               |     2 +-
 .../User/system_ch32v20x.c                    |     1 +
 .../ADC/DualADC_FastInterleaved/User/main.c   |     2 +-
 .../User/system_ch32v20x.c                    |     1 +
 .../ADC/DualADC_InjectionSimul/User/main.c    |     4 +-
 .../User/system_ch32v20x.c                    |     1 +
 EVT/EXAM/ADC/DualADC_RegSimul/User/main.c     |     6 +-
 .../DualADC_RegSimul/User/system_ch32v20x.c   |     1 +
 .../ADC/DualADC_SlowInterleaved/User/main.c   |     2 +-
 .../User/system_ch32v20x.c                    |     1 +
 EVT/EXAM/ADC/ExtLines_Trigger/User/main.c     |     2 +-
 .../ExtLines_Trigger/User/system_ch32v20x.c   |     1 +
 EVT/EXAM/ADC/Internal_Temperature/User/main.c |     4 +-
 .../User/system_ch32v20x.c                    |     1 +
 .../USBPD/CH223 Demo板使用说明.pdf            |   Bin 0 -> 782169 bytes
 .../USBPD/CH233 Demo Board Reference-EN.pdf   |   Bin 0 -> 807769 bytes
 .../APPLICATION/USBPD/I2C_OP_CH223/.cproject  |   143 +
 .../APPLICATION/USBPD/I2C_OP_CH223/.project   |    64 +
 .../APPLICATION/USBPD/I2C_OP_CH223/.template  |    17 +
 .../USBPD/I2C_OP_CH223/I2C_OP_CH223.wvproj}   |     0
 .../USBPD/I2C_OP_CH223/User/CH223.c           |   300 +
 .../USBPD/I2C_OP_CH223/User/CH223.h           |    33 +
 .../USBPD/I2C_OP_CH223}/User/ch32v20x_conf.h  |     0
 .../USBPD/I2C_OP_CH223}/User/ch32v20x_it.c    |     0
 .../USBPD/I2C_OP_CH223}/User/ch32v20x_it.h    |     0
 .../USBPD/I2C_OP_CH223/User/main.c            |   392 +
 .../I2C_OP_CH223}/User/system_ch32v20x.c      |     1 +
 .../I2C_OP_CH223}/User/system_ch32v20x.h      |     0
 EVT/EXAM/APPLICATION/WS2812_LED/.cproject     |   143 +
 .../{OPA => APPLICATION/WS2812_LED}/.project  |    12 +-
 EVT/EXAM/APPLICATION/WS2812_LED/.template     |    17 +
 .../WS2812_LED}/User/ch32v20x_conf.h          |     0
 .../APPLICATION/WS2812_LED/User/ch32v20x_it.c |    45 +
 .../WS2812_LED}/User/ch32v20x_it.h            |     0
 EVT/EXAM/APPLICATION/WS2812_LED/User/main.c   |   527 +
 .../WS2812_LED}/User/system_ch32v20x.c        |     1 +
 .../WS2812_LED}/User/system_ch32v20x.h        |     0
 .../WS2812_LED/WS2812_LED.wvproj}             |     0
 EVT/EXAM/{OPA => BKP/BKP}/.cproject           |     8 +-
 EVT/EXAM/BKP/{ => BKP}/.project               |    10 +-
 EVT/EXAM/{IWDG => BKP/BKP}/.template          |     3 +-
 .../{OPA/OPA.wvproj => BKP/BKP/BKP.wvproj}    |     0
 .../BKP}/User/ch32v20x_conf.h                 |     0
 EVT/EXAM/BKP/{ => BKP}/User/ch32v20x_it.c     |     0
 EVT/EXAM/{OPA => BKP/BKP}/User/ch32v20x_it.h  |     0
 EVT/EXAM/BKP/{ => BKP}/User/main.c            |     0
 EVT/EXAM/BKP/{ => BKP}/User/system_ch32v20x.c |     1 +
 .../{OPA => BKP/BKP}/User/system_ch32v20x.h   |     0
 EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c    |     1 +
 .../BackupUpgrade_IAP/APP/system_ch32v20x.c   |     1 +
 .../BackupUpgrade_OTA/APP/system_ch32v20x.c   |     1 +
 .../BLE/Broadcaster/APP/system_ch32v20x.c     |     1 +
 EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/Central/APP/system_ch32v20x.c    |     1 +
 .../BLE/CyclingSensor/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/Direct_Test_Mode/.cproject       |     9 +-
 EVT/EXAM/BLE/Direct_Test_Mode/APP/buf.c       |    81 +-
 .../APP/ch32v20x_usbfs_device.c               |   796 +
 EVT/EXAM/BLE/Direct_Test_Mode/APP/hci_test.c  |     1 +
 .../BLE/Direct_Test_Mode/APP/include/buf.h    |     2 +
 .../APP/include}/ch32v20x_usb.h               |     0
 .../APP/include/ch32v20x_usbfs_device.h       |   106 +
 .../BLE/Direct_Test_Mode/APP/include/uart.h   |    45 +-
 .../Direct_Test_Mode/APP/include/usb_desc.h   |    67 +
 EVT/EXAM/BLE/Direct_Test_Mode/APP/main.c      |    10 +-
 .../Direct_Test_Mode/APP/system_ch32v20x.c    |     1 +
 EVT/EXAM/BLE/Direct_Test_Mode/APP/test_dtm.c  |    17 +-
 EVT/EXAM/BLE/Direct_Test_Mode/APP/uart.c      |   415 +-
 EVT/EXAM/BLE/Direct_Test_Mode/APP/usb_desc.c  |    90 +
 EVT/EXAM/BLE/HAL/RTC.c                        |     2 +-
 .../BLE/HID_Consumer/APP/system_ch32v20x.c    |     1 +
 .../BLE/HID_Keyboard/APP/system_ch32v20x.c    |     1 +
 EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c  |     1 +
 EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c  |     1 +
 EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c  |     1 +
 EVT/EXAM/BLE/LIB/libwchble.a                  |   Bin 1214712 -> 1216412 bytes
 EVT/EXAM/BLE/LIB/wchble_rom.hex               | 23648 ++++++++--------
 EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c       |     1 +
 EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a          |   Bin 654960 -> 654948 bytes
 EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a       |   Bin 647756 -> 647740 bytes
 .../BLE/MESH/MESH_LIB/wchble_rom_mesh.hex     | 16221 +++++------
 .../MESH/adv_ali_light/APP/system_ch32v20x.c  |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 EVT/EXAM/BLE/MESH/adv_proxy/.cproject         |     2 +-
 .../BLE/MESH/adv_proxy/APP/system_ch32v20x.c  |     1 +
 .../BLE/MESH/adv_vendor/APP/system_ch32v20x.c |     1 +
 .../adv_vendor_friend/APP/system_ch32v20x.c   |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 .../BLE/MultiCentPeri/APP/system_ch32v20x.c   |     1 +
 .../BLE/MultiCentral/APP/system_ch32v20x.c    |     1 +
 EVT/EXAM/BLE/Observer/APP/observer.c          |     2 +-
 EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c   |     1 +
 .../OnlyUpdateApp_IAP/APP/system_ch32v20x.c   |     1 +
 .../APP/system_ch32v20x.c                     |     1 +
 EVT/EXAM/BLE/PAwR_ADV/.cproject               |     2 +-
 EVT/EXAM/BLE/PAwR_ADV/APP/adv_periodic.c      |     2 -
 EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c |     1 +
 .../APP/include/system_ch32v20x.h             |     2 +-
 EVT/EXAM/BLE/Peripheral_ETH/APP/peripheral.c  |     7 +-
 .../BLE/Peripheral_ETH/APP/system_ch32v20x.c  |  1251 +-
 EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c     |     1 +
 .../BLE/RF_PHY_Auto/APP/system_ch32v20x.c     |     1 +
 EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c |     1 +
 .../BLE/RunningSensor/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/SYNC_SCAN/APP/observer.c         |     2 +-
 EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c  |     1 +
 EVT/EXAM/BLE/SpeedTest_Central/.cproject      |     4 +-
 EVT/EXAM/BLE/SpeedTest_Central/APP/central.c  |    20 +-
 .../SpeedTest_Central/APP/system_ch32v20x.c   |     1 +
 EVT/EXAM/BLE/SpeedTest_Peripheral/.cproject   |     4 +-
 .../APP/system_ch32v20x.c                     |     1 +
 .../app/system_ch32v20x.c                     |     1 +
 .../CAN/Networking/User/system_ch32v20x.c     |     1 +
 EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c  |     1 +
 .../CAN/Time-triggered/User/system_ch32v20x.c |     1 +
 .../CRC_Calculation/User/system_ch32v20x.c    |     1 +
 .../.settings/language.settings.xml           |    14 -
 .../DMA/DMA_MEM2MEM/User/system_ch32v20x.c    |     1 +
 EVT/EXAM/ETH/DHCP/.cproject                   |     1 -
 EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c      |     7 +-
 EVT/EXAM/ETH/DNS/User/system_ch32v20x.c       |     7 +-
 EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c   |     7 +-
 EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c   |     7 +-
 EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c  |     7 +-
 .../ETH/IPRaw_PING/User/system_ch32v20x.c     |     7 +-
 EVT/EXAM/ETH/MAC_RAW/.cproject                |     2 +-
 EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c  |     2 +
 EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c   |     7 +-
 EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c      |     7 +-
 EVT/EXAM/ETH/Mail/User/system_ch32v20x.c      |     7 +-
 EVT/EXAM/ETH/NetLib/eth_driver.c              |     2 +
 EVT/EXAM/ETH/NetLib/libwchnet.a               |   Bin 222966 -> 222978 bytes
 EVT/EXAM/ETH/NetLib/wchnet.h                  |     4 +-
 EVT/EXAM/ETH/TcpClient/.cproject              |     2 +-
 EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c |     7 +-
 EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c |     7 +-
 EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c |     7 +-
 EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c |     7 +-
 ...rotocol Stack Library Application Note.PDF |   Bin 220582 -> 220647 bytes
 EVT/EXAM/ETH/WCHNET使用文档.PDF               |   Bin 236439 -> 237197 bytes
 EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c |     7 +-
 EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c    |     1 +
 EVT/EXAM/FLASH/FLASH_Program/User/main.c      |   107 +-
 .../FLASH_Program/User/system_ch32v20x.c      |     1 +
 EVT/EXAM/FreeRTOS/FreeRTOS_Core/.cproject     |   312 +-
 EVT/EXAM/FreeRTOS/FreeRTOS_Core/.project      |    12 +-
 .../Startup/startup_ch32v20x_D6.S             |   146 +-
 .../Startup/startup_ch32v20x_D8.S             |   269 +
 .../Startup/startup_ch32v20x_D8W.S            |   275 +
 .../FreeRTOS_Core/User/system_ch32v20x.c      |     1 +
 .../GPIO/GPIO_Toggle/User/system_ch32v20x.c   |     1 +
 EVT/EXAM/HarmonyOS/LiteOS_m/.cproject         |   522 +-
 EVT/EXAM/HarmonyOS/LiteOS_m/.project          |    12 +-
 .../LiteOS_m/Startup/startup_ch32v20x_D6.S    |   146 +-
 .../LiteOS_m/Startup/startup_ch32v20x_D8.S    |   269 +
 .../LiteOS_m/Startup/startup_ch32v20x_D8W.S   |   275 +
 .../HarmonyOS/LiteOS_m/User/system_ch32v20x.c |     1 +
 .../I2C/I2C_10bit_Mode/User/system_ch32v20x.c |     1 +
 .../I2C_7bit_Interrupt_Mode}/.cproject        |     8 +-
 EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.project |    61 +
 .../I2C/I2C_7bit_Interrupt_Mode/.template     |    17 +
 .../I2C_7bit_Interrupt_Mode.wvproj}           |     0
 .../User/ch32v20x_conf.h                      |     0
 .../User/ch32v20x_it.c                        |    59 +
 .../User/ch32v20x_it.h                        |     0
 .../I2C/I2C_7bit_Interrupt_Mode/User/main.c   |   204 +
 .../User/system_ch32v20x.c                    |   987 +
 .../User/system_ch32v20x.h                    |     0
 .../I2C/I2C_7bit_Mode/User/system_ch32v20x.c  |     1 +
 EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c   |     1 +
 .../I2C/I2C_EEPROM/User/system_ch32v20x.c     |     1 +
 EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c   |     1 +
 .../CH32V20x_APP/User/system_ch32v20x.c       |     1 +
 EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c |     2 +
 .../CH32V20x_IAP/User/system_ch32v20x.c       |     1 +
 .../INT/Interrupt_VTF/User/system_ch32v20x.c  |     1 +
 EVT/EXAM/IWDG/{ => IWDG}/.cproject            |     8 +-
 EVT/EXAM/IWDG/{ => IWDG}/.project             |    10 +-
 EVT/EXAM/{OPA => IWDG/IWDG}/.template         |     3 +-
 .../TOUCHKEY.wvproj => IWDG/IWDG/IWDG.wvproj} |     0
 EVT/EXAM/IWDG/IWDG/User/ch32v20x_conf.h       |    42 +
 .../IWDG}/User/ch32v20x_it.c                  |     0
 .../{WWDG => IWDG/IWDG}/User/ch32v20x_it.h    |     0
 EVT/EXAM/IWDG/{ => IWDG}/User/main.c          |     0
 EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c     |   987 +
 .../IWDG}/User/system_ch32v20x.h              |     0
 .../OPA_Voltage_Follower}/.cproject           |     8 +-
 EVT/EXAM/OPA/OPA_Voltage_Follower/.project    |    61 +
 EVT/EXAM/OPA/OPA_Voltage_Follower/.template   |    17 +
 .../OPA_Voltage_Follower.wvproj}              |     0
 .../User/ch32v20x_conf.h                      |     0
 .../User/ch32v20x_it.c                        |     0
 .../OPA_Voltage_Follower/User/ch32v20x_it.h   |    20 +
 .../{ => OPA_Voltage_Follower}/User/main.c    |     0
 .../User/system_ch32v20x.c                    |     1 +
 .../User/system_ch32v20x.h                    |     0
 .../PWR/Sleep_Mode/User/system_ch32v20x.c     |     1 +
 .../PWR/Standby_Mode/User/system_ch32v20x.c   |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 .../Standby_RAM_Mode/User/system_ch32v20x.c   |     1 +
 EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c |     1 +
 EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c   |     1 +
 .../RCC/HSI_PLL_Source/User/system_ch32v20x.c |     1 +
 EVT/EXAM/RCC/MCO/User/system_ch32v20x.c       |     1 +
 EVT/EXAM/RT-Thread/rt-thread/.cproject        |   336 +-
 EVT/EXAM/RT-Thread/rt-thread/.project         |     6 +-
 .../rt-thread/Startup/startup_ch32v20x_D6.S   |   146 +-
 .../rt-thread/Startup/startup_ch32v20x_D8.S   |   269 +
 .../rt-thread/Startup/startup_ch32v20x_D8W.S  |   275 +
 .../rt-thread/User/system_ch32v20x.c          |     1 +
 EVT/EXAM/RTC/RTC_Calendar/.cproject           |   143 +
 EVT/EXAM/RTC/RTC_Calendar/.project            |    61 +
 EVT/EXAM/RTC/RTC_Calendar/.template           |    17 +
 EVT/EXAM/RTC/RTC_Calendar/RTC_Calendar.wvproj |     2 +
 .../{ => RTC_Calendar}/User/ch32v20x_conf.h   |     0
 .../RTC/{ => RTC_Calendar}/User/ch32v20x_it.c |     0
 .../RTC/{ => RTC_Calendar}/User/ch32v20x_it.h |     0
 EVT/EXAM/RTC/{ => RTC_Calendar}/User/main.c   |     0
 .../RTC/RTC_Calendar/User/system_ch32v20x.c   |   987 +
 .../RTC/RTC_Calendar/User/system_ch32v20x.h   |    32 +
 EVT/EXAM/SDI_Printf/SDI_Printf/.cproject      |   278 +-
 EVT/EXAM/SDI_Printf/SDI_Printf/.project       |   116 +-
 EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.c  |   248 -
 EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.h  |    58 -
 .../SDI_Printf/User/system_ch32v20x.c         |     1 +
 .../1Lines_half-duplex/User/system_ch32v20x.c |     1 +
 .../2Lines_FullDuplex/User/system_ch32v20x.c  |     1 +
 .../FullDuplex_HardNSS/User/system_ch32v20x.c |     1 +
 EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c   |     1 +
 EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c   |     1 +
 EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c |     1 +
 EVT/EXAM/SPI/SPI_LCD/.cproject                |   144 +
 EVT/EXAM/{RTC => SPI/SPI_LCD}/.project        |    12 +-
 EVT/EXAM/{RTC => SPI/SPI_LCD}/.template       |     3 +-
 EVT/EXAM/SPI/SPI_LCD/LCD/config.h             |    51 +
 EVT/EXAM/SPI/SPI_LCD/LCD/flash.c              |   462 +
 EVT/EXAM/SPI/SPI_LCD/LCD/flash.h              |    57 +
 EVT/EXAM/SPI/SPI_LCD/LCD/lcd.c                |   407 +
 EVT/EXAM/SPI/SPI_LCD/LCD/lcd.h                |    57 +
 EVT/EXAM/SPI/SPI_LCD/LCD/spi.c                |   253 +
 EVT/EXAM/SPI/SPI_LCD/LCD/spi.h                |    39 +
 EVT/EXAM/SPI/SPI_LCD/SPI_LCD.wvproj           |     2 +
 EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_conf.h     |    42 +
 EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c       |    40 +
 EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.h       |    20 +
 EVT/EXAM/SPI/SPI_LCD/User/main.c              |    80 +
 EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c   |   987 +
 EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.h   |    32 +
 EVT/EXAM/SRC/Core/core_riscv.c                |     6 +-
 EVT/EXAM/SRC/Core/core_riscv.h                |    45 +-
 EVT/EXAM/SRC/Debug/debug.c                    |    60 +-
 EVT/EXAM/SRC/Debug/debug.h                    |    12 +-
 EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h        |     2 +-
 EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h  |     7 +-
 .../Peripheral/inc}/ch32v20x_usb.h            |    23 +-
 EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c    |    23 +-
 EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c  |   287 +-
 EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c   |    12 +-
 EVT/EXAM/SRC/Peripheral/src/ch32v20x_rtc.c    |    65 +-
 EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S    |   144 +-
 EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S    |   154 +-
 EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S   |   158 +-
 .../SYSTICK_Interrupt/User/system_ch32v20x.c  |     1 +
 .../TIM/Clock_Select/User/system_ch32v20x.c   |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c |     1 -
 .../TIM/Input_Capture/User/system_ch32v20x.c  |     1 +
 EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 .../TIM/PWM_Output/User/system_ch32v20x.c     |     1 +
 .../Synchro_ExtTrigger/User/system_ch32v20x.c |     1 +
 .../TIM/Synchro_Timer/User/system_ch32v20x.c  |     1 +
 EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c   |     1 +
 EVT/EXAM/TOUCHKEY/.cproject                   |   143 -
 EVT/EXAM/TOUCHKEY/.template                   |    16 -
 EVT/EXAM/TOUCHKEY/TKEY/.cproject              |   143 +
 EVT/EXAM/TOUCHKEY/{ => TKEY}/.project         |    10 +-
 EVT/EXAM/TOUCHKEY/TKEY/.template              |    17 +
 EVT/EXAM/TOUCHKEY/TKEY/TOUCHKEY.wvproj        |     2 +
 EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_conf.h   |    42 +
 EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c     |    42 +
 EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.h     |    20 +
 EVT/EXAM/TOUCHKEY/{ => TKEY}/User/main.c      |     0
 EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c |   987 +
 EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.h |    32 +
 EVT/EXAM/TencentOS/TencentOS/.cproject        |     4 +-
 .../TencentOS/Startup/startup_ch32v20x_D6.S   |   146 +-
 .../TencentOS/Startup/startup_ch32v20x_D8.S   |   269 +
 .../TencentOS/Startup/startup_ch32v20x_D8W.S  |   275 +
 .../TencentOS/User/system_ch32v20x.c          |     1 +
 .../USART/USART_DMA/User/system_ch32v20x.c    |     1 +
 .../USART_HalfDuplex/User/system_ch32v20x.c   |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 .../{WWDG => USART/USART_Idle_Recv}/.cproject |     8 +-
 EVT/EXAM/USART/USART_Idle_Recv/.project       |    61 +
 EVT/EXAM/USART/USART_Idle_Recv/.template      |    17 +
 .../USART_Idle_Recv/USART_Idle_Recv.wvproj    |     2 +
 .../USART_Idle_Recv/User/ch32v20x_conf.h      |    42 +
 .../USART/USART_Idle_Recv/User/ch32v20x_it.c  |    42 +
 .../USART/USART_Idle_Recv/User/ch32v20x_it.h  |    20 +
 EVT/EXAM/USART/USART_Idle_Recv/User/main.c    |   277 +
 .../USART_Idle_Recv}/User/system_ch32v20x.c   |     1 +
 .../USART_Idle_Recv/User/system_ch32v20x.h    |    32 +
 .../USART_Interrupt/User/system_ch32v20x.c    |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 .../USART_Polling/User/system_ch32v20x.c      |     1 +
 .../USART/USART_Printf/User/system_ch32v20x.c |     1 +
 .../User/system_ch32v20x.c                    |     1 +
 .../USBD/CH372/User/USBLIB/CONFIG/usb_prop.c  |    58 +-
 .../User/USBLIB/CONFIG/usb_prop.c             |    36 +-
 .../User/USBLIB/CONFIG/hw_config.c            |    10 +-
 .../CompositeKM/User/USBLIB/CONFIG/usb_prop.c |    29 +-
 .../USBD/CompositeKM/User/usbd_compostie_km.c |    21 +-
 .../MSC_CD-ROM/User/USBLIB/CONFIG/usb_prop.c  |    58 +-
 .../MSC_U-Disk/User/USBLIB/CONFIG/usb_prop.c  |    58 +-
 .../User/USBLIB/CONFIG/usb_endp.c             |     2 +-
 .../User/USBLIB/CONFIG/usb_prop.c             |    90 +-
 .../SimulateCDC/User/USBLIB/CONFIG/usb_prop.c |    48 +-
 .../USB/USBFS/DEVICE/CH372Device/.cproject    |    12 +-
 .../DEVICE/CH372Device/User/ch32v20x_usb.h    |   534 -
 .../CH372Device/User/ch32v20x_usbfs_device.c  |    10 +-
 .../USBFS/DEVICE/CH372Device/User/usb_desc.c  |     2 +-
 .../USBFS/DEVICE/CompatibilityHID/.cproject   |    12 +-
 .../CompatibilityHID/User/ch32v20x_usb.h      |   531 -
 .../User/ch32v20x_usbfs_device.c              |     7 +-
 .../USB/USBFS/DEVICE/CompositeKM/.cproject    |    12 +-
 .../DEVICE/CompositeKM/User/ch32v20x_usb.h    |   540 -
 .../CompositeKM/User/ch32v20x_usbfs_device.c  |     8 +-
 .../CompositeKM/User/usbd_compostie_km.c      |    13 +-
 .../DEVICE/MSC_CD-ROM/User/ch32v20x_usb.h     |   534 -
 .../MSC_CD-ROM/User/ch32v20x_usbfs_device.c   |     3 +-
 .../USB/USBFS/DEVICE/MSC_U-Disk/.cproject     |    12 +-
 .../DEVICE/MSC_U-Disk/User/ch32v20x_usb.h     |   534 -
 .../MSC_U-Disk/User/ch32v20x_usbfs_device.c   |     3 +-
 .../User/USB_Device/ch32v20x_usbfs_device.c   |     8 +-
 .../User/USB_Device/usb_desc.c                |     2 +-
 .../User/USB_Device/ch32v20x_usbfs_device.c   |     8 +-
 .../USB/USBFS/HOST_IAP/HOST_IAP/.cproject     |     6 +-
 .../HOST_IAP/HOST_IAP/User/ch32v20x_conf.h    |     1 +
 .../HOST_IAP/HOST_IAP/User/ch32v20x_usb.h     |   539 -
 EVT/EXAM/USB/USBFS/HOST_KM/.cproject          |    12 +-
 .../User/USB_Host/ch32v20x_usbfs_host.c       |    21 +-
 .../USB/USBFS/HOST_KM/User/ch32v20x_usb.h     |   540 -
 .../User/USB_Host/ch32v20x_usbfs_host.c       |    21 +-
 .../HOST_MTP_FileSystem/User/ch32v20x_usb.h   |   540 -
 .../USB/USBFS/HOST_Udisk/User/ch32v20x_usb.h  |   539 -
 EVT/EXAM/WWDG/.template                       |    16 -
 EVT/EXAM/WWDG/User/system_ch32v20x.c          |   986 -
 EVT/EXAM/WWDG/WWDG/.cproject                  |   143 +
 EVT/EXAM/WWDG/{ => WWDG}/.project             |    10 +-
 EVT/EXAM/{BKP => WWDG/WWDG}/.template         |     3 +-
 EVT/EXAM/WWDG/WWDG/User/ch32v20x_conf.h       |    42 +
 EVT/EXAM/WWDG/{ => WWDG}/User/ch32v20x_it.c   |     0
 EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.h         |    20 +
 EVT/EXAM/WWDG/{ => WWDG}/User/main.c          |     0
 EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c     |   987 +
 EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.h     |    32 +
 EVT/EXAM/WWDG/WWDG/WWDG.wvproj                |     2 +
 EVT/PUB/CH32V20xSCH.pdf                       |   Bin 1855834 -> 1854962 bytes
 .../CH32F&V208C-R0-1v1.PcbDoc                 |   Bin
 .../CH32F&V208C-R0/CH32F&V208C-R0.SchDoc      |   Bin 0 -> 345600 bytes
 .../CH32F&V208C_R0/CH32F&V208C-R0.SchDoc      |   Bin 348160 -> 0 bytes
 .../CH32F&V208G-R0.PcbDoc}                    |   Bin
 .../CH32F&V208G-R0/CH32F&V208G-R0.SchDoc      |   Bin 0 -> 450048 bytes
 .../CH32F&V208G_R0/CH32F&V208G-R0.SchDoc      |   Bin 451072 -> 0 bytes
 .../CH32F&V208R-R0-1v1.PcbDoc                 |   Bin
 .../CH32F&V208R-R0.SchDoc                     |   Bin
 .../CH32F&V208W-R0-1v4.PcbDoc                 |   Bin
 .../CH32F&V208W-R0.SchDoc                     |   Bin
 .../CH32V20xG8-R0-1v1.PcbDoc                  |   Bin
 .../CH32V20xG8-R0.SchDoc                      |   Bin
 395 files changed, 37947 insertions(+), 28760 deletions(-)
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/CH223 Demo板使用说明.pdf
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/CH233 Demo Board Reference-EN.pdf
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.cproject
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.project
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.template
 rename EVT/EXAM/{BKP/BKP.wvproj => APPLICATION/USBPD/I2C_OP_CH223/I2C_OP_CH223.wvproj} (100%)
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.h
 rename EVT/EXAM/{BKP => APPLICATION/USBPD/I2C_OP_CH223}/User/ch32v20x_conf.h (100%)
 rename EVT/EXAM/{IWDG => APPLICATION/USBPD/I2C_OP_CH223}/User/ch32v20x_it.c (100%)
 rename EVT/EXAM/{BKP => APPLICATION/USBPD/I2C_OP_CH223}/User/ch32v20x_it.h (100%)
 create mode 100644 EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c
 rename EVT/EXAM/{RTC => APPLICATION/USBPD/I2C_OP_CH223}/User/system_ch32v20x.c (99%)
 rename EVT/EXAM/{BKP => APPLICATION/USBPD/I2C_OP_CH223}/User/system_ch32v20x.h (100%)
 create mode 100644 EVT/EXAM/APPLICATION/WS2812_LED/.cproject
 rename EVT/EXAM/{OPA => APPLICATION/WS2812_LED}/.project (81%)
 create mode 100644 EVT/EXAM/APPLICATION/WS2812_LED/.template
 rename EVT/EXAM/{IWDG => APPLICATION/WS2812_LED}/User/ch32v20x_conf.h (100%)
 create mode 100644 EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c
 rename EVT/EXAM/{IWDG => APPLICATION/WS2812_LED}/User/ch32v20x_it.h (100%)
 create mode 100644 EVT/EXAM/APPLICATION/WS2812_LED/User/main.c
 rename EVT/EXAM/{IWDG => APPLICATION/WS2812_LED}/User/system_ch32v20x.c (99%)
 rename EVT/EXAM/{IWDG => APPLICATION/WS2812_LED}/User/system_ch32v20x.h (100%)
 rename EVT/EXAM/{IWDG/IWDG.wvproj => APPLICATION/WS2812_LED/WS2812_LED.wvproj} (100%)
 rename EVT/EXAM/{OPA => BKP/BKP}/.cproject (97%)
 rename EVT/EXAM/BKP/{ => BKP}/.project (83%)
 rename EVT/EXAM/{IWDG => BKP/BKP}/.template (94%)
 rename EVT/EXAM/{OPA/OPA.wvproj => BKP/BKP/BKP.wvproj} (100%)
 rename EVT/EXAM/{TOUCHKEY => BKP/BKP}/User/ch32v20x_conf.h (100%)
 rename EVT/EXAM/BKP/{ => BKP}/User/ch32v20x_it.c (100%)
 rename EVT/EXAM/{OPA => BKP/BKP}/User/ch32v20x_it.h (100%)
 rename EVT/EXAM/BKP/{ => BKP}/User/main.c (100%)
 rename EVT/EXAM/BKP/{ => BKP}/User/system_ch32v20x.c (99%)
 rename EVT/EXAM/{OPA => BKP/BKP}/User/system_ch32v20x.h (100%)
 create mode 100644 EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c
 rename EVT/EXAM/{USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device => BLE/Direct_Test_Mode/APP/include}/ch32v20x_usb.h (100%)
 create mode 100644 EVT/EXAM/BLE/Direct_Test_Mode/APP/include/ch32v20x_usbfs_device.h
 create mode 100644 EVT/EXAM/BLE/Direct_Test_Mode/APP/include/usb_desc.h
 create mode 100644 EVT/EXAM/BLE/Direct_Test_Mode/APP/usb_desc.c
 delete mode 100644 EVT/EXAM/DMA/DMA_MEM2MEM/.settings/language.settings.xml
 create mode 100644 EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S
 create mode 100644 EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S
 create mode 100644 EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S
 create mode 100644 EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S
 rename EVT/EXAM/{BKP => I2C/I2C_7bit_Interrupt_Mode}/.cproject (97%)
 create mode 100644 EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.project
 create mode 100644 EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template
 rename EVT/EXAM/{RTC/RTC.wvproj => I2C/I2C_7bit_Interrupt_Mode/I2C_7bit_Interrupt_Mode.wvproj} (100%)
 rename EVT/EXAM/{WWDG => I2C/I2C_7bit_Interrupt_Mode}/User/ch32v20x_conf.h (100%)
 create mode 100644 EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c
 rename EVT/EXAM/{TOUCHKEY => I2C/I2C_7bit_Interrupt_Mode}/User/ch32v20x_it.h (100%)
 create mode 100644 EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c
 create mode 100644 EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c
 rename EVT/EXAM/{RTC => I2C/I2C_7bit_Interrupt_Mode}/User/system_ch32v20x.h (100%)
 rename EVT/EXAM/IWDG/{ => IWDG}/.cproject (97%)
 rename EVT/EXAM/IWDG/{ => IWDG}/.project (83%)
 rename EVT/EXAM/{OPA => IWDG/IWDG}/.template (94%)
 rename EVT/EXAM/{TOUCHKEY/TOUCHKEY.wvproj => IWDG/IWDG/IWDG.wvproj} (100%)
 create mode 100644 EVT/EXAM/IWDG/IWDG/User/ch32v20x_conf.h
 rename EVT/EXAM/{TOUCHKEY => IWDG/IWDG}/User/ch32v20x_it.c (100%)
 rename EVT/EXAM/{WWDG => IWDG/IWDG}/User/ch32v20x_it.h (100%)
 rename EVT/EXAM/IWDG/{ => IWDG}/User/main.c (100%)
 create mode 100644 EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c
 rename EVT/EXAM/{TOUCHKEY => IWDG/IWDG}/User/system_ch32v20x.h (100%)
 rename EVT/EXAM/{RTC => OPA/OPA_Voltage_Follower}/.cproject (97%)
 create mode 100644 EVT/EXAM/OPA/OPA_Voltage_Follower/.project
 create mode 100644 EVT/EXAM/OPA/OPA_Voltage_Follower/.template
 rename EVT/EXAM/{WWDG/WWDG.wvproj => OPA/OPA_Voltage_Follower/OPA_Voltage_Follower.wvproj} (100%)
 rename EVT/EXAM/OPA/{ => OPA_Voltage_Follower}/User/ch32v20x_conf.h (100%)
 rename EVT/EXAM/OPA/{ => OPA_Voltage_Follower}/User/ch32v20x_it.c (100%)
 create mode 100644 EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.h
 rename EVT/EXAM/OPA/{ => OPA_Voltage_Follower}/User/main.c (100%)
 rename EVT/EXAM/OPA/{ => OPA_Voltage_Follower}/User/system_ch32v20x.c (99%)
 rename EVT/EXAM/{WWDG => OPA/OPA_Voltage_Follower}/User/system_ch32v20x.h (100%)
 create mode 100644 EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8.S
 create mode 100644 EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8W.S
 create mode 100644 EVT/EXAM/RTC/RTC_Calendar/.cproject
 create mode 100644 EVT/EXAM/RTC/RTC_Calendar/.project
 create mode 100644 EVT/EXAM/RTC/RTC_Calendar/.template
 create mode 100644 EVT/EXAM/RTC/RTC_Calendar/RTC_Calendar.wvproj
 rename EVT/EXAM/RTC/{ => RTC_Calendar}/User/ch32v20x_conf.h (100%)
 rename EVT/EXAM/RTC/{ => RTC_Calendar}/User/ch32v20x_it.c (100%)
 rename EVT/EXAM/RTC/{ => RTC_Calendar}/User/ch32v20x_it.h (100%)
 rename EVT/EXAM/RTC/{ => RTC_Calendar}/User/main.c (100%)
 create mode 100644 EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c
 create mode 100644 EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.h
 delete mode 100644 EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.c
 delete mode 100644 EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/.cproject
 rename EVT/EXAM/{RTC => SPI/SPI_LCD}/.project (81%)
 rename EVT/EXAM/{RTC => SPI/SPI_LCD}/.template (93%)
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/config.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/flash.c
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/flash.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/lcd.c
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/lcd.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/spi.c
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/LCD/spi.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/SPI_LCD.wvproj
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_conf.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.h
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/User/main.c
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c
 create mode 100644 EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.h
 rename EVT/EXAM/{USB/USBFS/DEVICE/SimulateCDC/User/USB_Device => SRC/Peripheral/inc}/ch32v20x_usb.h (93%)
 delete mode 100644 EVT/EXAM/TOUCHKEY/.cproject
 delete mode 100644 EVT/EXAM/TOUCHKEY/.template
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/.cproject
 rename EVT/EXAM/TOUCHKEY/{ => TKEY}/.project (83%)
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/.template
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/TOUCHKEY.wvproj
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_conf.h
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.h
 rename EVT/EXAM/TOUCHKEY/{ => TKEY}/User/main.c (100%)
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c
 create mode 100644 EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.h
 create mode 100644 EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8.S
 create mode 100644 EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8W.S
 rename EVT/EXAM/{WWDG => USART/USART_Idle_Recv}/.cproject (97%)
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/.project
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/.template
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/USART_Idle_Recv.wvproj
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_conf.h
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.h
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/User/main.c
 rename EVT/EXAM/{TOUCHKEY => USART/USART_Idle_Recv}/User/system_ch32v20x.c (99%)
 create mode 100644 EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.h
 delete mode 100644 EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_usb.h
 delete mode 100644 EVT/EXAM/WWDG/.template
 delete mode 100644 EVT/EXAM/WWDG/User/system_ch32v20x.c
 create mode 100644 EVT/EXAM/WWDG/WWDG/.cproject
 rename EVT/EXAM/WWDG/{ => WWDG}/.project (83%)
 rename EVT/EXAM/{BKP => WWDG/WWDG}/.template (94%)
 create mode 100644 EVT/EXAM/WWDG/WWDG/User/ch32v20x_conf.h
 rename EVT/EXAM/WWDG/{ => WWDG}/User/ch32v20x_it.c (100%)
 create mode 100644 EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.h
 rename EVT/EXAM/WWDG/{ => WWDG}/User/main.c (100%)
 create mode 100644 EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c
 create mode 100644 EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.h
 create mode 100644 EVT/EXAM/WWDG/WWDG/WWDG.wvproj
 rename EVT/PUB/SCHPCB/{CH32F&V208C_R0 => CH32F&V208C-R0}/CH32F&V208C-R0-1v1.PcbDoc (100%)
 create mode 100644 EVT/PUB/SCHPCB/CH32F&V208C-R0/CH32F&V208C-R0.SchDoc
 delete mode 100644 EVT/PUB/SCHPCB/CH32F&V208C_R0/CH32F&V208C-R0.SchDoc
 rename EVT/PUB/SCHPCB/{CH32F&V208G_R0/CH32F&V208G-R0-1v0.PcbDoc => CH32F&V208G-R0/CH32F&V208G-R0.PcbDoc} (100%)
 create mode 100644 EVT/PUB/SCHPCB/CH32F&V208G-R0/CH32F&V208G-R0.SchDoc
 delete mode 100644 EVT/PUB/SCHPCB/CH32F&V208G_R0/CH32F&V208G-R0.SchDoc
 rename EVT/PUB/SCHPCB/{CH32F&V208R_R0 => CH32F&V208R-R0}/CH32F&V208R-R0-1v1.PcbDoc (100%)
 rename EVT/PUB/SCHPCB/{CH32F&V208R_R0 => CH32F&V208R-R0}/CH32F&V208R-R0.SchDoc (100%)
 rename EVT/PUB/SCHPCB/{CH32F&V208W_R0 => CH32F&V208W-R0}/CH32F&V208W-R0-1v4.PcbDoc (100%)
 rename EVT/PUB/SCHPCB/{CH32F&V208W_R0 => CH32F&V208W-R0}/CH32F&V208W-R0.SchDoc (100%)
 rename EVT/PUB/SCHPCB/{CH32V20xG8_R0 => CH32V20xG8-R0}/CH32V20xG8-R0-1v1.PcbDoc (100%)
 rename EVT/PUB/SCHPCB/{CH32V20xG8_R0 => CH32V20xG8-R0}/CH32V20xG8-R0.SchDoc (100%)

diff --git a/EVT/CH32V20x_List.txt b/EVT/CH32V20x_List.txt
index 1f36e65..6dfe479 100644
--- a/EVT/CH32V20x_List.txt
+++ b/EVT/CH32V20x_List.txt
@@ -1,5 +1,5 @@
 
-�Ͼ��ߺ�΢���ӹɷ����޹�˾ 2023.09
+�Ͼ��ߺ�΢���ӹɷ����޹�˾ 2023.10
 ���������뵽���ǵ���վ�ϲ�ѯ
 https://wch.cn
 
@@ -36,6 +36,11 @@ https://wch.cn
   |      |      |      |      |-- DualADC_SlowInterleaved��˫ADC���ٽ���������� ������������CH32V20x_D6
   |      |      |      |      |-- ExtLines_Trigger���ⲿ����ADCת������
   |      |      |      |      |-- Internal_Temperature���ڲ��¶ȴ��������� 
+  |      |      |      |-- APPLICATION
+  |      |      |      |      |-- USBPD
+  |      |      |      |      |      |-- I2C_OP_CH223��ͨ��I2C����CH223���� ������������CH32V20x_D8
+  |      |      |      |      |-- WS2812_LED
+  |      |      |      |      |      |-- WS2812_LED��ͨ��SPI\PWM����WS2812���� 
   |      |      |      |-- BLE ������������CH32V20x_D8W  
   |      |      |      |      |-- BackupUpgrade_IAP��������������IAP���̣���⵱ǰ�����־���ж��Ƿ���˱��������뵽�û����������û������� 
   |      |      |      |      |-- BackupUpgrade_OTA���������������û����̣�����ӻ����̻���������OTA���ܣ��ɽ������̼����浽����������תIAP�����������  
@@ -92,12 +97,14 @@ https://wch.cn
   |      |      |      |      |      |-- MESH_LIB��MESHЭ��ջ���ļ�����ͷ�ļ�
   |      |      |      |      |      |-- �ߺ�MESH APP��������Ӧ���ֲ�.pdf
   |      |      |      |      |      |-- �ߺ�͹�������MESH���������ο��ֲ�.pdf
-  |      |      |      |-- BKP��BKP����
+  |      |      |      |-- BKP
+  |      |      |      |      |-- BKP��BKP����  
   |      |      |      |-- CAN  ������������CH32V20x_D6-CH32V20x_D8W
   |      |      |      |      |-- Networking��CAN���̣�����ģʽ����׼֡����չ֡�����շ�
   |      |      |      |      |-- TestMode������ģʽ��������Ĭģʽ���ػ�ģʽ���ػ���Ĭģʽ
   |      |      |      |      |-- Time-triggered��ʱ�䴥��ͨ��ģʽ   
-  |      |      |      |-- CRC��CRC����  
+  |      |      |      |-- CRC
+  |      |      |      |      |-- CRC_Calculation��CRC���� 
   |      |      |      |-- DMA
   |      |      |      |      |-- DMA_MEM2MEM����������������ģʽ����
   |      |      |      |      |-- DMA_MEM2PERIP��������������ģʽ�����赽������ģʽ���̼�������������
@@ -117,24 +124,31 @@ https://wch.cn
   |      |      |      |      |-- UdpClient����ʾUdp Client�������ݲ��ش�
   |      |      |      |      |-- UdpServer����ʾUdp Server�������ݲ��ش�
   |      |      |      |      |-- WebServer�� ��ʾͨ��Web���������WCHNETоƬ�Ĺ��ܣ�WCHNETоƬ����web������ ��ͨ����ҳ����ʵ��WCHNET������������ã��Լ��������  
-  |      |      |      |-- EXTI���ⲿ�ж�������
-  |      |      |      |-- FLASH��FLASH�IJ�/��/д���Լ����ٱ��
+  |      |      |      |-- EXTI
+  |      |      |      |      |-- EXTI0���ⲿ�ж������� 
+  |      |      |      |-- FLASH
+  |      |      |      |      |-- FLASH_Program��FLASH�IJ�/��/д���Լ����ٱ��  
   |      |      |      |-- FreeRTOS
   |      |      |      |      |-- FreeRTOS_Core��FreeRTOS��ֲ����
-  |      |      |      |-- GPIO��GPIO����
-  |      |      |      |-- HarmonyOS��HarmonyOS��ֲ����  
+  |      |      |      |-- GPIO
+  |      |      |      |      |-- GPIO_Toggle��GPIO���� 
+  |      |      |      |-- HarmonyOS
+  |      |      |      |      |-- LiteOS_m��HarmonyOS��ֲ����
   |      |      |      |-- I2C
   |      |      |      |      |-- I2C_7bit_Mode��7λ��ַģʽ��Master/Slave ģʽ�շ�����
   |      |      |      |      |-- I2C_10bit_Mode��10λ��ַģʽ��Master/Slave ģʽ�շ�����
   |      |      |      |      |-- I2C_DMA��I2Cʹ��DMA��Master/Slave ģʽ�շ�����
   |      |      |      |      |-- I2C_EEPROM��I2C�ӿڲ���EEPROM��������
-  |      |      |      |      |-- I2C_PEC��ʹ��PEC����У�飬Master/Slave ģʽ�շ�����  
+  |      |      |      |      |-- I2C_PEC��ʹ��PEC����У�飬Master/Slave ģʽ�շ����� 
+  |      |      |      |      |-- I2C_7bit_Interrupt_Mode��ʹ���жϽ����շ����� 
   |      |      |      |-- INT
   |      |      |      |      |-- Interrupt_VTF��ʹ��VTF IRQ�ж�����  
   |      |      |      |-- IAP��IAP��������-����HexתBin���ߺ�IAP��������  
   |      |      |      |      |-- USB_UART��USB+UART IAP����   
-  |      |      |      |-- IWDG���������Ź�����
-  |      |      |      |-- OPA��OPA4����ѹ�������������
+  |      |      |      |-- IWDG
+  |      |      |      |      |-- IWDG���������Ź�����  
+  |      |      |      |-- OPA
+  |      |      |      |      |-- OPA_Voltage_Follower��OPA4����ѹ������������� 
   |      |      |      |-- PWR
   |      |      |      |      |-- Sleep_Mode���͹��ģ�˯��ģʽ����
   |      |      |      |      |-- Standby_Mode���͹��ģ�����ģʽ����
@@ -145,8 +159,10 @@ https://wch.cn
   |      |      |      |      |-- Get_CLK����ȡsystem-HCLK-AHB1-AHB2ʱ������   
   |      |      |      |      |-- MCO��MCO����ʱ���������
   |      |      |      |      |-- HSI_PLL_Source��HSI��HSI/2��ΪPLL����ʱ������   
-  |      |      |      |-- RT-Thread��RT-Thread��ֲ���� 
-  |      |      |      |-- RTC����������  
+  |      |      |      |-- RT-Thread 
+  |      |      |      |      |-- RT_Thread_Core��RT-Thread��ֲ����  
+  |      |      |      |-- RTC
+  |      |      |      |      |-- RTC_Calendar����������
   |      |      |      |-- SPI
   |      |      |      |      |-- 1Lines_half-duplex�����߰�˫��ģʽ��Master/Slave ģʽ�����շ�
   |      |      |      |      |-- 2Lines_FullDuplex��˫��ȫ˫��ģʽ��Master/Slave ģʽ�����շ�
@@ -154,9 +170,13 @@ https://wch.cn
   |      |      |      |      |-- SPI_CRC��ʹ��CRC����У�飬Master/Slave ģʽ�շ�����
   |      |      |      |      |-- SPI_DMA��SPIʹ��DMA��Master/Slave ģʽ�շ�����
   |      |      |      |      |-- SPI_FLASH��SPI�ӿڲ���FLASH��������
-  |      |      |      |-- TencentOS��TencentOS��ֲ���� 
-  |      |      |      |-- SDI_Printf�����Կڴ�ӡ����       
-  |      |      |      |-- SYSTICK���δ�ʱ������       
+  |      |      |      |      |-- SPI_LCD��SPI�ӿڲ���FLASH��LCD����
+  |      |      |      |-- TencentOS 
+  |      |      |      |      |-- TencentOS��TencentOS��ֲ���� 
+  |      |      |      |-- SDI_Printf       
+  |      |      |      |      |-- SDI_Printf�����Կڴ�ӡ����       
+  |      |      |      |-- SYSTICK 
+  |      |      |      |      |-- SYSTICK_Interrupt���δ�ʱ������       
   |      |      |      |-- TIM
   |      |      |      |      |-- Clock_Select��ʱ��Դѡ������
   |      |      |      |      |-- ComplementaryOutput_DeadTime�������������������ģʽ����
@@ -168,7 +188,8 @@ https://wch.cn
   |      |      |      |      |-- Synchro_ExtTrigger����ģʽ���̣�������λģʽ���ſ�ģʽ������ģʽ
   |      |      |      |      |-- Synchro_Timer����ʱ��ͬ��ģʽ
   |      |      |      |      |-- TIM_DMA����ʱ��ʹ��DMA����
-  |      |      |      |-- TOUCHKEY��TouchKey������� 
+  |      |      |      |-- TOUCHKEY
+  |      |      |      |      |-- TKey��TouchKey�������  
   |      |      |      |-- USART
   |      |      |      |      |-- USART_DMA��USARTʹ��DMA��Master/Slave ģʽ�շ�����
   |      |      |      |      |-- USART_HalfDuplex�����߰�˫��ģʽ��Master/Slave ģʽ�շ�����
@@ -178,6 +199,7 @@ https://wch.cn
   |      |      |      |      |-- USART_Polling����ѯ�շ�ģʽ��Master/Slave ģʽ�շ�����
   |      |      |      |      |-- USART_Printf�����ڴ�ӡ��������
   |      |      |      |      |-- USART_SynchronousMode��ͬ��ģʽ��Master/Slave ģʽ�շ�����
+  |      |      |      |      |-- USART_Idle_Recv������ʹ��DMA���в�������������
   |      |      |      |-- USB
   |      |      |      |      |-- USBD
   |      |      |      |      |      |-- CH372��ģ���Զ���USB�豸��CH372�豸�����˵�1��3�´���2��4�ϴ����˵�1�´������ݴӶ˵�3�ϴ�����ȡ�����˵�2�´������ݴӶ˵�4�ϴ���ȡ����
@@ -204,3 +226,4 @@ https://wch.cn
   |      |      |      |      |      |-- Udisk_Lib��U���ļ�ϵͳ���ļ�
   |      |      |      |      |      |-- Host_Udisk��USB��������U������     
   |      |      |      |-- WWDG�����ڿ��Ź�����
+  |      |      |      |      |-- WWDG�����ڿ��Ź�����  
diff --git a/EVT/CH32V20x_List_EN.txt b/EVT/CH32V20x_List_EN.txt
index 1cdb2e4..67f124f 100644
--- a/EVT/CH32V20x_List_EN.txt
+++ b/EVT/CH32V20x_List_EN.txt
@@ -35,6 +35,11 @@ Directory
   |      |      |      |      |-- DualADC_SlowInterleaved: dual ADC slow interleaved sampling routine, only applied to CH32V20x_D6
   |      |      |      |      |-- ExtLines_Trigger: external lines trigger ADC conversion routine
   |      |      |      |      |-- Internal_Temperature: internal temperature sensor routine 
+  |      |      |      |-- APPLICATION
+  |      |      |      |      |-- USBPD
+  |      |      |      |      |      |-- I2C_OP_CH223：I2C Operates CH223 routine, only applied to CH32V20x_D8
+  |      |      |      |      |-- WS2812_LED
+  |      |      |      |      |      |-- WS2812_LED：SPI\PWM Operates WS2812_LED routine
   |      |      |      |-- BLE ----only for CH32V20x_D8W 
   |      |      |      |      |-- BackupUpgrade_IAP: backup wireless upgrade IAP routine. Detect the current code flag, determine whether to move the code from the backup area to the user area, and run the code in the user area 
   |      |      |      |      |-- BackupUpgrade_OTA: backup wireless upgrade user routine. Add OTA function to peripheral slave routines, save the upgrade firmware to the backup area and jump to the IAP program to upgrade 
@@ -91,12 +96,14 @@ Directory
   |      |      |      |      |      |-- MESH_LIB: MESH protocol stack library file and header file
   |      |      |      |      |      |-- Qinheng MESH APP Management Distribution Network Application Manual.pdf
   |      |      |      |      |      |-- Qinheng Low Energy Bluetooth MESH Software Development Reference Manual.pdf
-  |      |      |      |-- BKP: BKP routine
+  |      |      |      |-- BKP
+  |      |      |      |      |-- BKP:BKP routines
   |      |      |      |-- CAN ----only for CH32V20x_D6-CH32V20x_D8W 
   |      |      |      |      |-- Networking: CAN routine: normal mode, standard frame and expanded frame data transceiver
   |      |      |      |      |-- TestMode: test mode, including silent mode, loopback mode and loopback silent mode
   |      |      |      |      |-- Time-triggered: time triggered communication mode   
-  |      |      |      |-- CRC: CRC routine
+  |      |      |      |-- CRC
+  |      |      |      |      |-- CRC_Calculation:CRC routines  
   |      |      |      |-- DMA
   |      |      |      |      |-- DMA_MEM2MEM: Memory to memory mode routine
   |      |      |      |      |-- DMA_MEM2PERIP: Memory to peripheral mode, and peripheral to memory mode routine, see peripheral sub-routines
@@ -116,24 +123,31 @@ Directory
   |      |      |      |      |-- UdpClient: demonstration routine that Udp Client receives data and returns data
   |      |      |      |      |-- UdpServer: demonstration routine that Udp Server receives data and returns data
   |      |      |      |      |-- WebServer: Web Server routine, to demonstrate the configuration of WCHNET device functions through Web browser. As the WCHNET devices have built-in web server, the network parameter configuration and password management of WCHNET can be implemented on the web page.   
-  |      |      |      |-- EXTI: external interrupt line routine
-  |      |      |      |-- FLASH: FLASH erase/read/write, and fast programming
+  |      |      |      |-- EXTI
+  |      |      |      |      |-- EXTI0:External Interrupt Routine
+  |      |      |      |-- FLASH
+  |      |      |      |      |-- FLASH_Program:FLASH erase/read/write, and fast programming 
   |      |      |      |-- FreeRTOS
   |      |      |      |      |-- FreeRTOS_Core:FreeRTOS migration routines
-  |      |      |      |-- GPIO: GPIO routine
-  |      |      |      |-- HarmonyOS:HarmonyOS migration routine  
+  |      |      |      |-- GPIO
+  |      |      |      |      |-- GPIO_Toggle:GPIO routines 
+  |      |      |      |-- HarmonyOS
+  |      |      |      |      |-- LiteOS_m：HarmonyOS migration routine
   |      |      |      |-- I2C
   |      |      |      |      |-- I2C_7bit_Mode: 7-bit addressing mode, master/slave mode, transceiver routine
   |      |      |      |      |-- I2C_10bit_Mode: 10-bit addressing mode, master/slave mode transceiver routine
   |      |      |      |      |-- I2C_DMA: I2C DMA, master/slave mode transceiver routine
   |      |      |      |      |-- I2C_EEPROM: I2C interface routine to operate EEPROM peripheral 
   |      |      |      |      |-- I2C_PEC: PEC error check, master/slave mode transceiver routine
+  |      |      |      |      |-- I2C_7bit_Interrupt_Mode：Use interrupt to receive and send routine 
   |      |      |      |-- INT
   |      |      |      |      |-- Interrupt_VTF: VTF IRQ interrupt routine   
   |      |      |      |-- IAP: IAP upgrade routine, including the Hex to Bin tool and IAP upgrade tool  
   |      |      |      |      |-- USB_UART: USB+UART IAP routine    
-  |      |      |      |-- IWDG: independent watchdog routine
-  |      |      |      |-- OPA: OPA4 as voltage follower output routine
+  |      |      |      |-- IWDG
+  |      |      |      |      |-- IWDG:Independent Watchdog routine 
+  |      |      |      |-- OPA
+  |      |      |      |      |-- OPA_Voltage_Follower：OPA4 as voltage follower output routine 
   |      |      |      |-- PWR
   |      |      |      |      |-- Sleep_Mode: low power, sleep mode routine
   |      |      |      |      |-- Standby_Mode: low power, standby mode routine
@@ -144,8 +158,10 @@ Directory
   |      |      |      |      |-- Get_CLK:Get system-HCLK-AHB1-AHB2 clock routine   
   |      |      |      |      |-- MCO: MCO pin clock output routine
   |      |      |      |      |-- HSI_PLL_Source:HSI or HSI/2 as PLL input clock routine       
-  |      |      |      |-- RT-Thread:RT thread migration routine 
-  |      |      |      |-- RTC: calendar routine
+  |      |      |      |-- RT-Thread
+  |      |      |      |      |-- RT_Thread_Core:RT-Thread migration routine  
+  |      |      |      |-- RTC
+  |      |      |      |      |-- RTC_Calendar:Calendar Routines  
   |      |      |      |-- SPI
   |      |      |      |      |-- 1Lines_half-duplex: single wire half duplex mode, master/slave mode, data transceiver
   |      |      |      |      |-- 2Lines_FullDuplex: two-wire full duplex mode, master/slave mode, data transceiver
@@ -153,10 +169,13 @@ Directory
   |      |      |      |      |-- SPI_CRC: CRC error check and master/slave mode transceiver routine
   |      |      |      |      |-- SPI_DMA: SPI DMA, master/slave mode transceiver routine
   |      |      |      |      |-- SPI_FLASH: SPI interface operation flash peripheral routine
-  |      |      |      |-- TencentOS: TencentOS migration routine     
+  |      |      |      |      |-- SPI_LCD:SPI interface operation FLASH  and LCD peripheral routines
+  |      |      |      |-- TencentOS
+  |      |      |      |      |-- TencentOS:TencentOS migration routine  
   |      |      |      |-- SDI_Printf
   |      |      |      |      |-- SDI_Printf：debug interface SDI, virtual serial port. 
-  |      |      |      |-- SYSTICK: Systick timer routine     
+  |      |      |      |-- SYSTICK 
+  |      |      |      |      |-- SYSTICK_Interrupt：Systick timer routine       
   |      |      |      |-- TIM
   |      |      |      |      |-- Clock_Select: clock source selection routine
   |      |      |      |      |-- ComplementaryOutput_DeadTime: complementary output and deadband insertion mode routines
@@ -168,7 +187,8 @@ Directory
   |      |      |      |      |-- Synchro_ExtTrigger:slave mode routine, including reset mode, gating mode and trigger mode
   |      |      |      |      |-- Synchro_Timer:timer synchronization mode
   |      |      |      |      |-- TIM_DMA: timer DMA routines
-  |      |      |      |-- TOUCHKEY:touchkey detection routine
+  |      |      |      |-- TOUCHKEY
+  |      |      |      |      |-- TKey:TouchKey Detection Routine 
   |      |      |      |-- USART
   |      |      |      |      |-- USART_DMA: USART DMA, master/slave mode transceiver routine
   |      |      |      |      |-- USART_HalfDuplex: single wire half duplex mode, master/slave mode transceiver routine
@@ -178,6 +198,8 @@ Directory
   |      |      |      |      |-- USART_Polling: polling transceiver mode, master/slave transceiver routine
   |      |      |      |      |-- USART_Printf: USART Print debugging routine
   |      |      |      |      |-- USART_SynchronousMode: synchronous mode, master/slave mode, transceiver routine
+  |      |      |      |      |-- USART_Printf:Serial port printing debugging routines
+  |      |      |      |      |-- USART_Idle_Recv：USART use DMA receiving indeterminate length data routines
   |      |      |      |-- USB
   |      |      |      |      |-- USBD
   |      |      |      |      |      |-- CH372:Simulates a custom USB device (CH372 device) with endpoints 1, 3 down and 2, 4 up. Data down from endpoint 1 is uploaded from endpoint 3 and not reversed, and data down from endpoint 2 is uploaded from endpoint 4 and reversed.
@@ -203,5 +225,6 @@ Directory
   |      |      |      |      |      |-- HOST_MTP_FileSystem:Enumeration process of a USB host to a device that supports MTP and PTP protocols, supports MTP and PTP protocols, and reads its files
   |      |      |      |      |      |-- Host_Udisk:USB host operation USB disk routine 
   |      |      |      |      |      |-- Udisk_Lib:U disk file system library file     
-  |      |      |      |-- WWDG: window watchdog routine
+  |      |      |      |-- WWDG
+  |      |      |      |      |-- WWDG:Window Watchdog Routine
 
diff --git a/EVT/EXAM/ADC/ADC_DMA/User/main.c b/EVT/EXAM/ADC/ADC_DMA/User/main.c
index b42e490..429f9ed 100644
--- a/EVT/EXAM/ADC/ADC_DMA/User/main.c
+++ b/EVT/EXAM/ADC/ADC_DMA/User/main.c
@@ -149,7 +149,7 @@ void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsiz
  */
 u16 Get_ConversionVal(s16 val)
 {
-    if((val + Calibrattion_Val) < 0)
+    if((val + Calibrattion_Val) < 0 || val==0)
         return 0;
     if((Calibrattion_Val + val) > 4095||val==4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/ADC_DMA/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/AnalogWatchdog/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/Auto_Injection/User/main.c b/EVT/EXAM/ADC/Auto_Injection/User/main.c
index a8898b9..a226c06 100644
--- a/EVT/EXAM/ADC/Auto_Injection/User/main.c
+++ b/EVT/EXAM/ADC/Auto_Injection/User/main.c
@@ -54,6 +54,7 @@ void ADC_Function_Init(void)
     ADC_InitStructure.ADC_NbrOfChannel = 1;
     ADC_Init(ADC1, &ADC_InitStructure);
 
+    ADC_InjectedSequencerLengthConfig(ADC1, 1);
     ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 1, ADC_SampleTime_239Cycles5);
     ADC_InjectedChannelConfig(ADC1, ADC_Channel_3, 1, ADC_SampleTime_239Cycles5);
     ADC_AutoInjectedConvCmd(ADC1, ENABLE);
@@ -119,7 +120,7 @@ u16 Get_ADC_Val(u8 ch)
  */
 u16 Get_ConversionVal(s16 val)
 {
-    if((val + Calibrattion_Val) < 0)
+    if((val + Calibrattion_Val) < 0||val==0)
         return 0;
     if((Calibrattion_Val + val) > 4095||val==4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Auto_Injection/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/main.c b/EVT/EXAM/ADC/Discontinuous_mode/User/main.c
index 97551f5..a98808d 100644
--- a/EVT/EXAM/ADC/Discontinuous_mode/User/main.c
+++ b/EVT/EXAM/ADC/Discontinuous_mode/User/main.c
@@ -57,7 +57,7 @@ void ADC_Function_Init(void)
     ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
     ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigInjecConv_T1_CC4;
     ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
-    ADC_InitStructure.ADC_NbrOfChannel = 3;
+    ADC_InitStructure.ADC_NbrOfChannel = 1;
     ADC_Init(ADC1, &ADC_InitStructure);
 
     ADC_InjectedSequencerLengthConfig(ADC1, 3);
@@ -133,7 +133,7 @@ void TIM1_PWM_In(u16 arr, u16 psc, u16 ccp)
  */
 u16 Get_ConversionVal(s16 val)
 {
-    if((val + Calibrattion_Val) < 0)
+    if((val + Calibrattion_Val) < 0||val==0)
         return 0;
     if((Calibrattion_Val + val) > 4095||val==4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Discontinuous_mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c
index a74d758..e40f32f 100644
--- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/main.c
@@ -151,7 +151,7 @@ void TIM2_PWM_In(u16 arr, u16 psc, u16 ccp)
  */
 u16 Get_ConversionVal1(s16 val)
 {
-    if((val + Calibrattion_Val1) < 0)
+    if((val + Calibrattion_Val1) < 0|| val==0)
         return 0;
     if((Calibrattion_Val1 + val) > 4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_AlternateTrigger/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c
index 4e824bc..321c46e 100644
--- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/main.c
@@ -166,7 +166,7 @@ void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsiz
  */
 u16 Get_ConversionVal1(s16 val)
 {
-    if((val + Calibrattion_Val1) < 0)
+    if((val + Calibrattion_Val1) < 0|| val==0)
         return 0;
     if((Calibrattion_Val1 + val) > 4095||val==4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_Combined_RegInjectionSimul/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c
index 61d5d7d..46a5ccd 100644
--- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/main.c
@@ -110,7 +110,7 @@ void ADC_Function_Init(void)
  */
 u16 Get_ConversionVal1(s16 val)
 {
-    if((val + Calibrattion_Val1) < 0)
+    if((val + Calibrattion_Val1) < 0|| val==0)
         return 0;
     if((Calibrattion_Val1 + val) > 4095||val==4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_FastInterleaved/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c
index 2de8e1f..697147d 100644
--- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/main.c
@@ -101,9 +101,9 @@ void ADC_Function_Init(void)
  */
 u16 Get_ConversionVal1(s16 val)
 {
-    if((val + Calibrattion_Val1) < 0)
+    if((val + Calibrattion_Val1) < 0|| val==0)
         return 0;
-    if((Calibrattion_Val1 + val) > 4095)
+    if((Calibrattion_Val1 + val) > 4095|| val==4095)
         return 4095;
     return (val + Calibrattion_Val1);
 }
diff --git a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_InjectionSimul/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c
index 3274a6e..d3853a6 100644
--- a/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/main.c
@@ -16,7 +16,7 @@
  *ADC1 channel 1 (PA1), ADC2 channel 3 (PA3)), and the rule group channel obtains
  *dual ADC conversion data through DMA interrupt.
  *
- *Note��only applied toCH32V203
+ *Note:only applied toCH32V203
  */
 
 #include "debug.h"
@@ -162,9 +162,9 @@ u16 Get_ConversionVal1(s16 val)
  */
 u16 Get_ConversionVal2(s16 val)
 {
-    if((val + Calibrattion_Val2) < 0)
+    if((val + Calibrattion_Val2) < 0||val==0)
         return 0;
-    if((Calibrattion_Val2 + val) > 4095)
+    if((Calibrattion_Val2 + val) > 4095||val==4095)
         return 4095;
     return (val + Calibrattion_Val2);
 }
diff --git a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_RegSimul/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c
index a9d71e0..eef2acf 100644
--- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c
+++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/main.c
@@ -111,7 +111,7 @@ void ADC_Function_Init(void)
  */
 u16 Get_ConversionVal1(s16 val)
 {
-    if((val + Calibrattion_Val1) < 0)
+    if((val + Calibrattion_Val1) < 0|| val==0)
         return 0;
     if((Calibrattion_Val1 + val) > 4095 || val == 4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/DualADC_SlowInterleaved/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c
index 9e785dc..4102332 100644
--- a/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c
+++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/main.c
@@ -116,7 +116,7 @@ void EXTI_Event_Init(void)
  */
 u16 Get_ConversionVal(s16 val)
 {
-    if((val + Calibrattion_Val) < 0)
+    if((val + Calibrattion_Val) < 0|| val==0)
         return 0;
     if((Calibrattion_Val + val) > 4095 || val==4095)
         return 4095;
diff --git a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/ExtLines_Trigger/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/main.c b/EVT/EXAM/ADC/Internal_Temperature/User/main.c
index dd2cceb..dd27c5d 100644
--- a/EVT/EXAM/ADC/Internal_Temperature/User/main.c
+++ b/EVT/EXAM/ADC/Internal_Temperature/User/main.c
@@ -161,9 +161,9 @@ u16 Get_ADC_Average(u8 ch, u8 times)
  */
 u16 Get_ConversionVal(s16 val)
 {
-    if((val + Calibrattion_Val) < 0)
+    if((val + Calibrattion_Val) < 0|| val==0)
         return 0;
-    if((Calibrattion_Val + val) > 4095)
+    if((Calibrattion_Val + val) > 4095|| val==4095)
         return 4095;
     return (val + Calibrattion_Val);
 }
diff --git a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c
+++ b/EVT/EXAM/ADC/Internal_Temperature/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/APPLICATION/USBPD/CH223 Demo板使用说明.pdf b/EVT/EXAM/APPLICATION/USBPD/CH223 Demo板使用说明.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..0ae9a3883a4c8c5d050943c3dff28b56bddd9ff0
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diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.cproject b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.cproject
new file mode 100644
index 0000000..adbd3f0
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.cproject
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
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+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="ld|Core|Peripheral|Debug|Startup" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry excluding="startup_ch32v20x_D8W.S|startup_ch32v20x_D6.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="ld"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
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+</cproject>
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.project b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.project
new file mode 100644
index 0000000..13aa2f8
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.project
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<projectDescription>
+	<name>I2C_OP_CH223</name>
+	<comment/>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Core</name>
+			<type>2</type>
+			<locationURI>PARENT-3-PROJECT_LOC/SRC/Core</locationURI>
+		</link>
+		<link>
+			<name>Debug</name>
+			<type>2</type>
+			<locationURI>PARENT-3-PROJECT_LOC/SRC/Debug</locationURI>
+		</link>
+		<link>
+			<name>Peripheral</name>
+			<type>2</type>
+			<locationURI>PARENT-3-PROJECT_LOC/SRC/Peripheral</locationURI>
+		</link>
+		<link>
+			<name>Startup</name>
+			<type>2</type>
+			<locationURI>PARENT-3-PROJECT_LOC/SRC/Startup</locationURI>
+		</link>
+		<link>
+			<name>ld</name>
+			<type>2</type>
+			<locationURI>PARENT-3-PROJECT_LOC/SRC/Ld</locationURI>
+		</link>
+	</linkedResources>
+	<filteredResources>
+		<filter>
+			<id>1595986042669</id>
+			<name/>
+			<type>22</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+</projectDescription>
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.template b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.template
new file mode 100644
index 0000000..f9de1ff
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\I2C_OP_CH223.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/BKP/BKP.wvproj b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/I2C_OP_CH223.wvproj
similarity index 100%
rename from EVT/EXAM/BKP/BKP.wvproj
rename to EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/I2C_OP_CH223.wvproj
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c
new file mode 100644
index 0000000..825189e
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.c
@@ -0,0 +1,300 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : CH223.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/08/15
+ * Description        : CH223оƬ��������ļ�
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+/******************************************************************************/
+#include "debug.h"
+#include "CH223.h"
+#include "string.h"
+
+u32 Buffer[7] = {0};//NDO raw data in SRCCAP
+u16 BufferV[SIZE] = {0};//Analyzing voltage data in SRCCAP
+u16 BufferI[SIZE] = {0};//Analyzing Current Data in SRCCAP
+u16 BufferVPPS[SIZE] = {0};//Parsing PPS data in SRCCAP
+
+/*********************************************************************
+ * @fn      IIC_Init
+ *
+ * @brief   Initializes the IIC peripheral.
+ *
+ *  PB11------SDA
+ *  PB10------SCL
+ *
+ * @return  none
+ */
+void IIC_Init(u32 bound, u16 address)
+{
+    GPIO_InitTypeDef GPIO_InitStructure={0};
+    I2C_InitTypeDef I2C_InitTSturcture={0};
+
+    RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE );
+//    GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE);
+    RCC_APB1PeriphClockCmd( RCC_APB1Periph_I2C2, ENABLE );
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init( GPIOB, &GPIO_InitStructure );
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init( GPIOB, &GPIO_InitStructure );
+
+    I2C_InitTSturcture.I2C_ClockSpeed = bound;
+    I2C_InitTSturcture.I2C_Mode = I2C_Mode_I2C;
+    I2C_InitTSturcture.I2C_DutyCycle = I2C_DutyCycle_16_9;
+    I2C_InitTSturcture.I2C_OwnAddress1 = address;
+    I2C_InitTSturcture.I2C_Ack = I2C_Ack_Enable;
+    I2C_InitTSturcture.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+    I2C_Init( I2C2, &I2C_InitTSturcture );
+
+    I2C_Cmd( I2C2, ENABLE );
+}
+/*********************************************************************
+ * @fn      CH223_Init
+ *
+ * @brief   Initializes CH223.
+ *
+ * @return  none
+ */
+void CH223_Init()
+{
+    IIC_Init(100000, 0XA0);
+}
+
+/*********************************************************************
+ * @fn      CH223_ReadOneByte
+ *
+ * @brief   Read one data from CH223.
+ *
+ * @param   ReadAddr - Read frist address.
+ *
+ * @return  temp - Read data.
+ */
+u8 CH223_ReadOneByte(u16 ReadAddr)
+{
+    u8 temp = 0;
+    while( I2C_GetFlagStatus( I2C2, I2C_FLAG_BUSY ) != RESET )
+    {
+
+    }
+    I2C_GenerateSTART( I2C2, ENABLE );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_MODE_SELECT ) );
+
+    I2C_Send7bitAddress( I2C2, 0X44, I2C_Direction_Transmitter );
+
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ) );
+
+    #if (Address_Lenth  == Address_8bit)
+        I2C_SendData( I2C2, (u8)(ReadAddr&0x00FF) );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+
+    #elif (Address_Lenth  == Address_16bit)
+    I2C_SendData( I2C2, (u8)(ReadAddr>>8) );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+
+    I2C_SendData( I2C2, (u8)(ReadAddr&0x00FF) );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+
+    #endif
+
+    I2C_GenerateSTART( I2C2, ENABLE );
+
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_MODE_SELECT ) );
+    I2C_Send7bitAddress( I2C2, 0X45, I2C_Direction_Receiver );
+
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) );
+    while( I2C_GetFlagStatus( I2C2, I2C_FLAG_RXNE ) ==  RESET )
+    I2C_AcknowledgeConfig( I2C2, DISABLE );
+
+    temp = I2C_ReceiveData( I2C2 );
+    I2C_GenerateSTOP( I2C2, ENABLE );
+
+    return temp;
+}
+
+/*********************************************************************
+ * @fn      CH223_WriteOneByte
+ *
+ * @brief   Write one data to CH223.
+ *
+ * @param   WriteAddr - Write frist address.
+ *
+ * @return  DataToWrite - Write data.
+ */
+void CH223_WriteOneByte(u16 WriteAddr, u8 DataToWrite)
+{
+    while( I2C_GetFlagStatus( I2C2, I2C_FLAG_BUSY ) != RESET );
+    I2C_GenerateSTART( I2C2, ENABLE );
+
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_MODE_SELECT ) );
+    I2C_Send7bitAddress( I2C2, 0X45, I2C_Direction_Transmitter );
+
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ) );
+
+    #if (Address_Lenth  == Address_8bit)
+    I2C_SendData( I2C2, (u8)(WriteAddr&0x00FF) );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+
+    #elif (Address_Lenth  == Address_16bit)
+        I2C_SendData( I2C2, (u8)(WriteAddr>>8) );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+
+    I2C_SendData( I2C2, (u8)(WriteAddr&0x00FF) );
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+
+    #endif
+
+    if( I2C_GetFlagStatus( I2C2, I2C_FLAG_TXE ) !=  RESET )
+    {
+        I2C_SendData( I2C2, DataToWrite );
+    }
+
+    while( !I2C_CheckEvent( I2C2, I2C_EVENT_MASTER_BYTE_TRANSMITTED ) );
+    I2C_GenerateSTOP( I2C2, ENABLE );
+}
+
+/*********************************************************************
+ * @fn      CH223_Read
+ *
+ * @brief   Read multiple data from CH223.
+ *
+ * @param   ReadAddr - Read frist address.
+ *          pBuffer - Read data.
+ *          NumToRead - Data number.
+ *
+ * @return  none
+ */
+void CH223_Read(u16 ReadAddr, u32 *pBuffer, u16 NumToRead)
+{
+    u8 t = 0;
+    u32 temp[4] = {0};
+    u32 temp1 = 0;
+
+    while(NumToRead)
+    {
+        temp[4] = 0;
+        for (t = 0; t < 4; t++)
+        {
+            temp[t] = CH223_ReadOneByte(ReadAddr++);
+        }
+        temp1 = (temp[0] + (temp[1] << 8) + (temp[2] << 16) + (temp[3] << 24));
+        *pBuffer++=temp1;
+        NumToRead--;
+    }
+}
+/*********************************************************************
+ * @fn      CH223_Write
+ *
+ * @brief   Write multiple data to CH223.
+ *
+ * @param   WriteAddr - Write frist address.
+ *          pBuffer - Write data.
+ *          NumToWrite - Data number.
+ *
+ * @return  none
+ */
+void CH223_Write(u16 WriteAddr, u8 *pBuffer, u16 NumToWrite)
+{
+    while(NumToWrite--)
+    {
+        CH223_WriteOneByte(WriteAddr, *pBuffer);
+        WriteAddr++;
+        pBuffer++;
+        Delay_Ms(2);
+    }
+}
+
+
+/*********************************************************************
+ * @fn      Buffer_Change
+ *
+ * @brief   Analysis of SRCCAP message
+ *
+ * @param   buffer[] - NDO data.
+ *                 n - NDO_Number.
+ *
+ * @return  none
+*/
+void Buffer_Change(u32 buffer[], int n)
+{
+    int i = 0;
+    u32 tempV = 0, tempI = 0, tempVmax = 0;
+    for(i = 0; i < n; i++)
+    {
+        tempV = buffer[i];
+        tempI = buffer[i];
+        if((tempV & 0xC0000000) == 0)
+        {
+            tempV >>= 10;
+            tempV &= 0x03FF;
+            BufferV[i] = tempV * 0.5;
+
+            tempI &= 0x03FF;
+            BufferI[i] = tempI * 0.1;
+        }
+        else {
+            tempV >>= 8;
+            tempVmax = tempV >> 9;
+            tempV &= 0x00FF;
+            BufferV[i] = tempV * 1;
+            tempVmax &= 0x00FF;
+            BufferVPPS[i] = tempVmax * 1;
+
+            tempI &= 0x00FF;
+            BufferI[i] = tempI * 0.5;
+        }
+    }
+}
+/*********************************************************************
+ * @fn      Current_VI
+ *
+ * @brief   Read and display the current output voltage value
+ *
+ * @param   ndo_select - NDO_Select.
+ *
+ *
+ * @return  none
+*/
+void Current_VI(u8 ndo_select)
+{
+    u8 tempV = 0, tempI = 0;
+    u8 current[2];
+    tempV = BufferV[ndo_select] % 10;
+    current[0] = BufferV[ndo_select] / 10;
+
+    tempI = BufferI[ndo_select] % 10;
+    current[1] = BufferI[ndo_select] / 10;
+
+    printf("The current regulating voltage is��%d.%dV,%d.%dA\t\r\n", current[0], tempV, current[1], tempI);
+}
+/*********************************************************************
+ * @fn      User_Set_VI
+ *
+ * @brief   Set VBUS voltage
+ *
+ * @param   TargetData - Target voltage value.
+ *             VBUS voltage=TargetData*200mv
+ *
+ * @return  none
+*/
+
+void User_Set_VI(u8 TargetData)
+{
+    u8 ndo_select = 0, state_flag = 0;
+    CH223_WriteOneByte(0xB6, TargetData);
+    Delay_Ms(5000);
+    state_flag = CH223_ReadOneByte(0xB5);
+    ndo_select = (state_flag >> 3) & 0x07;
+    printf("nod_select_user-->%d\r\n",ndo_select);
+    Current_VI(ndo_select - 1);
+}
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.h b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.h
new file mode 100644
index 0000000..c6ba34e
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/CH223.h
@@ -0,0 +1,33 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : CH223.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/08/15
+ * Description        : header file for CH223.c
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#include"debug.h"
+
+#define Address_8bit    0
+#define Address_16bit   1
+#define Address_Lenth   Address_8bit
+#define SIZE sizeof(Buffer)
+
+extern u32 Buffer[7] ;//NDO raw data in SRCCAP
+extern u16 BufferV[SIZE];//Analyzing voltage data in SRCCAP
+extern u16 BufferI[SIZE];//Analyzing Current Data in SRCCAP
+extern u16 BufferVPPS[SIZE];//Parsing PPS data in SRCCAP
+
+void IIC_Init(u32 bound, u16 address);
+void CH223_Init();
+u8 CH223_ReadOneByte(u16 ReadAddr);
+void CH223_WriteOneByte(u16 WriteAddr, u8 DataToWrite);
+void CH223_Read(u16 ReadAddr, u32 *pBuffer, u16 NumToRead);
+void CH223_Write(u16 WriteAddr, u8 *pBuffer, u16 NumToWrite);
+void Buffer_Change(u32 buffer[], int n);
+void Current_VI(u8 ndo_select);
+void User_Set_VI(u8 TargetData);
diff --git a/EVT/EXAM/BKP/User/ch32v20x_conf.h b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_conf.h
similarity index 100%
rename from EVT/EXAM/BKP/User/ch32v20x_conf.h
rename to EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_conf.h
diff --git a/EVT/EXAM/IWDG/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c
similarity index 100%
rename from EVT/EXAM/IWDG/User/ch32v20x_it.c
rename to EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.c
diff --git a/EVT/EXAM/BKP/User/ch32v20x_it.h b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.h
similarity index 100%
rename from EVT/EXAM/BKP/User/ch32v20x_it.h
rename to EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/ch32v20x_it.h
diff --git a/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c
new file mode 100644
index 0000000..429a433
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/main.c
@@ -0,0 +1,392 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : main.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/06/06
+ * Description        : Main program body.
+*********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+/*
+ *@Note
+CH223 chip application routine
+
+*/
+
+#include "debug.h"
+#include"CH223.h"
+
+u8 ndo = 0;//Number of NDOs in SrcCap
+u8 IT_flag = 0;
+u8 rst_IT = 0, cc_IT = 0, srccap_IT = 0, ps_IT = 0;//Interrupt flag
+s16 Calibrattion_Val = 0;
+u16 TxBuf[1024];
+
+/*********************************************************************
+ * @fn      ADC_Function_Init
+ *
+ * @brief   Initializes ADC collection.
+ *          PB0-->ADC_IN
+ *
+ * @return  none
+ */
+void ADC_Function_Init(void)
+{
+    ADC_InitTypeDef  ADC_InitStructure = {0};
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+    RCC_ADCCLKConfig(RCC_PCLK2_Div8);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    ADC_DeInit(ADC1);
+    ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
+    ADC_InitStructure.ADC_ScanConvMode = DISABLE;
+    ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
+    ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+    ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+    ADC_InitStructure.ADC_NbrOfChannel = 1;
+    ADC_Init(ADC1, &ADC_InitStructure);
+
+    ADC_DMACmd(ADC1, ENABLE);
+    ADC_Cmd(ADC1, ENABLE);
+
+    ADC_BufferCmd(ADC1, DISABLE); //disable buffer
+    ADC_ResetCalibration(ADC1);
+    while(ADC_GetResetCalibrationStatus(ADC1));
+    ADC_StartCalibration(ADC1);
+    while(ADC_GetCalibrationStatus(ADC1));
+    Calibrattion_Val = Get_CalibrationValue(ADC1);
+
+}
+
+/*********************************************************************
+ * @fn      Get_ADC_Val
+ *
+ * @brief   Returns ADCx conversion result data.
+ *
+ * @param   ch - ADC channel.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *
+ * @return  none
+ */
+u16 Get_ADC_Val(u8 ch)
+{
+    u16 val;
+
+    ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5);
+    ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+
+    while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));
+    val = ADC_GetConversionValue(ADC1);
+
+    return val;
+}
+
+/*********************************************************************
+ * @fn      DMA_Tx_Init
+ *
+ * @brief   Initializes the DMAy Channelx configuration.
+ *
+ * @param   DMA_CHx - x can be 1 to 7.
+ *          ppadr - Peripheral base address.
+ *          memadr - Memory base address.
+ *          bufsize - DMA channel buffer size.
+ *
+ * @return  none
+ */
+void DMA_Tx_Init(DMA_Channel_TypeDef *DMA_CHx, u32 ppadr, u32 memadr, u16 bufsize)
+{
+    DMA_InitTypeDef DMA_InitStructure = {0};
+
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    DMA_DeInit(DMA_CHx);
+    DMA_InitStructure.DMA_PeripheralBaseAddr = ppadr;
+    DMA_InitStructure.DMA_MemoryBaseAddr = memadr;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    DMA_InitStructure.DMA_BufferSize = bufsize;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+    DMA_Init(DMA_CHx, &DMA_InitStructure);
+}
+/*********************************************************************
+ * @fn      Get_ConversionVal
+ *
+ * @brief   Get Conversion Value.
+ *
+ * @param   val - Sampling value
+ *
+ * @return  val+Calibrattion_Val - Conversion Value.
+ */
+u16 Get_ConversionVal(s16 val)
+{
+    if((val + Calibrattion_Val) < 0)
+        return 0;
+    if((Calibrattion_Val + val) > 4095||val==4095)
+        return 4095;
+    return (val + Calibrattion_Val);
+}
+
+/*********************************************************************
+ * @fn      EXTI0_INT_INIT
+ *
+ * @brief   Initialize external trigger interrupt.
+ *
+ *  PB13-->INT
+ *
+ * @return  none
+ */
+/*********************************************************************
+ * @fn      EXTI0_INT_INIT
+ *
+ * @brief   Initializes EXTI0 collection.
+ *
+ * @return  none
+ */
+void EXTI0_INT_INIT(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+    EXTI_InitTypeDef EXTI_InitStructure = {0};
+    NVIC_InitTypeDef NVIC_InitStructure = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    /* GPIOB ----> EXTI_Line0 */
+    GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource13);
+    EXTI_InitStructure.EXTI_Line = EXTI_Line13;
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+    EXTI_Init(&EXTI_InitStructure);
+
+    NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+/*********************************************************************
+ * @fn      Adc_test
+ *
+ * @brief   ADC measure VBUS output voltage.
+ *
+ *
+ * @return  none
+ */
+void Adc_test(){
+    u16 i = 0;
+    float sum=0;
+    DMA_Tx_Init(DMA1_Channel1, (u32)&ADC1->RDATAR, (u32)TxBuf, 1024);
+    DMA_Cmd(DMA1_Channel1, ENABLE);
+    ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 1, ADC_SampleTime_239Cycles5);
+    ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+    Delay_Ms(50);
+    ADC_SoftwareStartConvCmd(ADC1, DISABLE);
+    for(i = 0; i < 1024; i++){
+         sum+=Get_ConversionVal(TxBuf[i]);
+    }
+    printf("ADC_Value=%0.1fV\r\n",sum/1024/4095*3.3*6.1);
+}
+
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    u16 n = 0;
+    u8 tempV = 0, tempI = 0, tempV0 = 0, tempI0 = 0, tempVmax = 0;
+    u8 res = 0, ndo_select = 0, STATE_flag = 0;
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+    Delay_Init();
+    USART_Printf_Init( 115200 );
+    CH223_Init();
+    ADC_Function_Init();
+    EXTI0_INT_INIT();
+    printf("PD_CH223 Demo��\r\n");
+    printf("\r\n");
+    IT_flag = CH223_ReadOneByte(0xB4);
+    if (IT_flag==0x0c)
+    {
+        printf("power-on reset������\r\n");
+        printf("\r\n");
+        Delay_Ms(10);
+        printf("CC Connecting...\r\n");
+        printf("\r\n");
+    }
+    while(1)
+    {
+        Delay_Ms(1);
+        while(ps_IT)      //PS_RDY -->The power supply reaches the required working state
+        {
+            CH223_WriteOneByte(0xB6, 0x19);                    //The initial voltage is set to 9V��0x2D
+            res = CH223_ReadOneByte(0xB6);
+            printf("The initial voltage is set to��%dV\r\n",res*200/1000);
+            printf("\r\n");
+            Delay_Ms(300);
+            if (rst_IT == 1)
+            {
+                printf("power-on reset������\r\n");
+                printf("\r\n");
+            }
+            if (cc_IT == 1)
+            {
+                printf("CC Connecting...\r\n");
+                printf("\r\n");
+            }
+            STATE_flag = CH223_ReadOneByte(0xB5);               //Read IIC status register
+            ndo = STATE_flag & 0x07;                            //NDO_Number
+            printf("Number of NDOs in SRCCAP:%d\r\n", ndo);
+            printf("\r\n");
+            CH223_Read(0x84, Buffer, ndo);                      //SRCCAP message
+            Buffer_Change(Buffer, ndo);
+            if (srccap_IT == 1)        //Display SRCCAP message
+            {
+                printf("Received SrcCap,NDO data is��\n");
+                printf("\r\n");
+                for(n = 0; n < ndo; n++)
+                {
+                    if((Buffer[n] & 0xC0000000) == 0)
+                    {
+                        tempV = BufferV[n] % 10;
+                        tempV0 = BufferV[n] / 10;
+                        tempI = BufferI[n] % 10;
+                        tempI0 = BufferI[n] / 10;
+                        printf("%d.%dV,%d.%dA\t", tempV0, tempV, tempI0, tempI);
+                    }
+                    else
+                    {
+                        tempV = BufferV[n] % 10;
+                        tempV0 = BufferV[n] / 10;
+                        tempVmax = BufferVPPS[n] % 10;
+                        BufferVPPS[n] /= 10;
+                        tempI = BufferI[n] % 10;
+                        tempI0 = BufferI[n] / 10;
+                        printf("%d.%dV/%d.%dV,%d.%dA\t", tempV0, tempV, BufferVPPS[n], tempVmax, tempI0, tempI);
+                    }
+                }
+                printf("\r\n");
+            }
+            ndo_select = (STATE_flag >> 3) & 0x07;
+            printf("ndo_select:%d\r\n", ndo_select);
+            printf("Waiting PS_RDY...\r\n");
+            Delay_Ms(500);
+            if (ps_IT == 1)
+            {
+                printf("Received PS_RDY\r\n");
+                Current_VI(ndo_select - 1);
+            }
+            //Set VBUS voltage
+            printf("\r\n");
+            Delay_Ms(10);
+            printf("Set voltage output 5V-->0x19\r\n");
+            User_Set_VI(0x19); //0x19---5V
+            Adc_test();
+            Delay_Ms(50);
+            printf("\r\n");
+            Delay_Ms(10);
+            printf("Set voltage output 9V-->0x2d\r\n");
+            User_Set_VI(0x2d);   //0x2d---9V
+            Adc_test();
+            Delay_Ms(50);
+            printf("\r\n");
+            Delay_Ms(10);
+            printf("Set voltage output 12V-->0x3c\r\n");
+            User_Set_VI(0x3c);   //0x3c---12V
+            Adc_test();
+            Delay_Ms(50);
+            printf("\r\n");
+            Delay_Ms(10);
+            printf("Set voltage output 15V-->0x4b\r\n");
+            User_Set_VI(0x4b);   //0x4b---15V
+            Adc_test();
+            Delay_Ms(50);
+            printf("\r\n");
+            Delay_Ms(10);
+            printf("Set voltage output 20V-->0x64\r\n");
+            User_Set_VI(0x64);   //0x64---20V
+            Adc_test();
+            Delay_Ms(50);
+            ps_IT = 0;
+           }
+       }
+
+}
+
+void EXTI15_10_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+void EXTI15_10_IRQHandler(void)
+{
+    if(EXTI_GetITStatus(EXTI_Line13) != RESET)
+    {
+        Delay_Us(500);
+        if(EXTI_GetITStatus(EXTI_Line13) != RESET)
+        {
+            IT_flag = CH223_ReadOneByte(0xB4);
+            if ((IT_flag&0xF))
+            {
+                if (IT_flag&0x7)
+                {
+                    if(IT_flag&0x3)
+                    {
+                        if (IT_flag&0x1)
+                        {
+                            ps_IT = 1;
+                        }
+                        else
+                        {
+                            srccap_IT = 1;
+                        }
+                    }
+                    else
+                    {
+                        rst_IT = 1;
+                    }
+                }else
+                {
+                    cc_IT = 1;
+                }
+            }
+            EXTI_ClearITPendingBit(EXTI_Line13);     /* Clear Flag */
+        }
+    }
+}
diff --git a/EVT/EXAM/RTC/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c
similarity index 99%
rename from EVT/EXAM/RTC/User/system_ch32v20x.c
rename to EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/RTC/User/system_ch32v20x.c
+++ b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BKP/User/system_ch32v20x.h b/EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.h
similarity index 100%
rename from EVT/EXAM/BKP/User/system_ch32v20x.h
rename to EVT/EXAM/APPLICATION/USBPD/I2C_OP_CH223/User/system_ch32v20x.h
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/.cproject b/EVT/EXAM/APPLICATION/WS2812_LED/.cproject
new file mode 100644
index 0000000..35043f3
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/.cproject
@@ -0,0 +1,143 @@
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+									<listOptionValue builtIn="false" value="&quot;../LD&quot;"/>
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+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
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+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry excluding="startup_ch32v20x_D8.S|startup_ch32v20x_D8W.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
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+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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diff --git a/EVT/EXAM/OPA/.project b/EVT/EXAM/APPLICATION/WS2812_LED/.project
similarity index 81%
rename from EVT/EXAM/OPA/.project
rename to EVT/EXAM/APPLICATION/WS2812_LED/.project
index 41c6ac7..0974069 100644
--- a/EVT/EXAM/OPA/.project
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/.project
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <projectDescription>
-  <name>OPA</name>
+  <name>WS2812_LED</name>
   <comment/>
   <projects/>
   <buildSpec>
@@ -35,27 +35,27 @@
     <link>
       <name>Core</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Core</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
     </link>
     <link>
       <name>Debug</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Debug</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
     </link>
     <link>
       <name>Ld</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Ld</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
     </link>
     <link>
       <name>Peripheral</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Peripheral</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
     </link>
     <link>
       <name>Startup</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Startup</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
     </link>
   </linkedResources>
 </projectDescription>
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/.template b/EVT/EXAM/APPLICATION/WS2812_LED/.template
new file mode 100644
index 0000000..3c7f718
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\WS2812_LED.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/IWDG/User/ch32v20x_conf.h b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_conf.h
similarity index 100%
rename from EVT/EXAM/IWDG/User/ch32v20x_conf.h
rename to EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_conf.h
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c
new file mode 100644
index 0000000..ea6d338
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.c
@@ -0,0 +1,45 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main Interrupt Service Routines.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+  printf("\nHardFault \n");
+  printf("mepc %x \n",__get_MEPC());
+  printf("mcause %x \n",__get_MCAUSE());
+  while (1)
+  {
+  }
+}
+
+
diff --git a/EVT/EXAM/IWDG/User/ch32v20x_it.h b/EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.h
similarity index 100%
rename from EVT/EXAM/IWDG/User/ch32v20x_it.h
rename to EVT/EXAM/APPLICATION/WS2812_LED/User/ch32v20x_it.h
diff --git a/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c
new file mode 100644
index 0000000..6bcefe9
--- /dev/null
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/main.c
@@ -0,0 +1,527 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : main.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main program body.
+ *********************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * Attention: This software (modified or not) and binary are used for 
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
+ *******************************************************************************/
+
+/*
+ *@Note
+ *  This example demonstrates control w2812 by using SPI or PWM.
+ *
+ *  In spi mode
+ *  PA7 - w2812
+ *  In PWM mode
+ *  PA8 - w2812
+ */
+
+#include "debug.h"
+
+/* Global define */
+
+#define LED_SPI_MODE 1
+#define LED_PWM_MODE 2
+
+#define LED_MODE LED_SPI_MODE
+//#define LED_MODE LED_PWM_MODE
+
+#define Pixel_NUM (8)
+
+#define LIST_SIZE(list) (sizeof(list)/sizeof(list[0]))
+#define hex2rgb(c) (((c)>>16)&0xff),(((c)>>8)&0xff),((c)&0xff)
+
+/* Global Variable */
+
+#if LED_MODE == LED_SPI_MODE
+
+/** spi mode
+ * When you using spi mode, you should make sure your spi work at 6M clock
+ */
+
+#define Pixel_PRE_LEN (12u)
+#define Pixel_RESET_LEN (25u)
+#define COLOR_BUFFER_LEN (((Pixel_NUM)*Pixel_PRE_LEN)+Pixel_RESET_LEN)
+#define SPI1_DMA_TX_CH   DMA1_Channel3
+
+
+uint8_t color_buf[COLOR_BUFFER_LEN] = {0};
+
+
+/*********************************************************************
+ * @fn      convToBit
+ *
+ * @brief   Convert hex to spi bit
+ *
+ * @param   res  - the result
+ *          input - input data
+ *
+ * @return  none
+ */
+void convToBit(uint8_t *res, uint8_t input)
+{
+    uint8_t mask = 0x80;
+    for (int i = 0; i < 4; i++) {
+        uint8_t result = (input & mask) ? 0xE : 0x8;
+        result <<= 4;
+        mask >>= 1;
+        result |= (input & mask) ? 0xE : 0x8;
+        mask >>= 1;
+        res[i] = result;
+    }
+}
+
+
+/*********************************************************************
+ * @fn      colorToBit
+ *
+ * @brief   Convert color to spi bit
+ *
+ * @param   buf  - the result
+ *          r  - red channel
+ *          g  - green channel
+ *          b  - blue channel
+ *
+ * @return  none
+ */
+void colorToBit(uint8_t *buf, uint8_t r, uint8_t g, uint8_t b)
+{
+    uint8_t *res = buf;
+    convToBit(res, g);
+    convToBit(&(res[4]), r);
+    convToBit(&(res[8]), b);
+}
+
+
+/*********************************************************************
+ * @fn      setPixelColor
+ *
+ * @brief   Set the pixel color of an LED
+ *
+ * @param   index - index of LED
+ *          r  - red channel
+ *          g  - green channel
+ *          b  - blue channel
+ *
+ *
+ * @return  none
+ */
+void setPixelColor(uint16_t index, uint8_t r, uint8_t g, uint8_t b)
+{
+    uint8_t *buf = &(color_buf[index * Pixel_PRE_LEN]);
+    colorToBit(buf,r,g,b);
+}
+
+/*********************************************************************
+ * @fn      SPI_1Lines_HalfDuplex_Init
+ *
+ * @brief   Configuring the SPI for half-duplex communication.
+ *
+ * @return  none
+ */
+void SPI_1Lines_HalfDuplex_Init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure= {0};
+    SPI_InitTypeDef SPI_InitStructure= {0};
+
+    RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1, ENABLE );
+
+
+    // the clock output
+//    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+//    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+//    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+//    GPIO_Init( GPIOA, &GPIO_InitStructure );
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init( GPIOA, &GPIO_InitStructure );
+
+    SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
+    SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+    SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+    SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;
+    SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStructure.SPI_CRCPolynomial = 7;
+    SPI_Init( SPI1, &SPI_InitStructure );
+
+    SPI_Cmd( SPI1, ENABLE );
+}
+
+/*********************************************************************
+ * @fn      SPI1_DMA_Init
+ *
+ * @brief   Initialize DMA for SPI2
+ *
+ * @return  none
+ */
+void SPI1_DMA_Init()
+{
+    DMA_InitTypeDef DMA_InitStructure = {0};
+
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    DMA_DeInit(SPI1_DMA_TX_CH);
+
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DATAR;
+    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)color_buf;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize = COLOR_BUFFER_LEN;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+
+    DMA_Init(SPI1_DMA_TX_CH, &DMA_InitStructure);
+
+    SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, ENABLE);
+}
+#elif    LED_MODE == LED_PWM_MODE
+
+void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+#define CODE_0      (3)
+#define CODE_1      (7)
+#define RESET_LEN    (60)
+#define TIM_DMA_CH1_CH   DMA1_Channel5
+#define COLOR_BUFFER_LEN (((Pixel_NUM)*(3*8))+RESET_LEN)
+
+uint16_t color_buf[COLOR_BUFFER_LEN] = {0};
+
+/*********************************************************************
+ * @fn      TIM1_Init
+ *
+ * @brief   Initialize TIM1
+ *
+ * @return  none
+ */
+void TIM1_Init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+    TIM_OCInitTypeDef TIM_OCInitStructure = {0};
+    TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure = {0};
+
+    RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_TIM1, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init( GPIOA, &GPIO_InitStructure);
+
+    TIM_TimeBaseInitStructure.TIM_Period = 10 - 1;
+    TIM_TimeBaseInitStructure.TIM_Prescaler = SystemCoreClock / 8000000 - 1;
+    TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
+    TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
+    TIM_TimeBaseInit( TIM1, &TIM_TimeBaseInitStructure);
+
+    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+    TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+    TIM_OCInitStructure.TIM_Pulse = 0;
+    TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+    TIM_OC1Init( TIM1, &TIM_OCInitStructure);
+
+    TIM_OC1PreloadConfig( TIM1, TIM_OCPreload_Enable);
+    TIM_ARRPreloadConfig( TIM1, ENABLE);
+    TIM_CtrlPWMOutputs(TIM1, ENABLE);
+    TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
+    TIM_Cmd( TIM1, ENABLE);
+}
+
+/*********************************************************************
+ * @fn      DMA1_Init
+ *
+ * @brief   Initialize DMA for TIM1 ch1
+ *
+ * @return  none
+ */
+void DMA1_Init(void)
+{
+    DMA_InitTypeDef DMA_InitStructure = {0};
+    NVIC_InitTypeDef NVIC_InitStructure = {0};
+
+    RCC_AHBPeriphClockCmd( RCC_AHBPeriph_DMA1, ENABLE);
+
+    DMA_DeInit( TIM_DMA_CH1_CH);
+    DMA_Cmd( TIM_DMA_CH1_CH, DISABLE);
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &TIM1->CH1CVR;
+    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) color_buf;
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize = COLOR_BUFFER_LEN;
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+    DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+    DMA_Init( TIM_DMA_CH1_CH, &DMA_InitStructure);
+
+    DMA_Cmd( TIM_DMA_CH1_CH, DISABLE);
+
+    DMA_ITConfig( DMA1_Channel5, DMA_IT_TC, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+}
+
+/*********************************************************************
+ * @fn      setPixelColor
+ *
+ * @brief   Set the pixel color of an LED
+ *
+ * @param   id - index of LED
+ *          r  - red channel
+ *          g  - green channel
+ *          b  - blue channel
+ *
+ *
+ * @return  none
+ */
+void setPixelColor(uint16_t id, uint8_t r, uint8_t g, uint8_t b)
+{
+    int i = 0, j = id * 24u;
+    if (id >= Pixel_NUM) {
+        return;
+    }
+
+    for (i = 0; i < 8; i++) {
+        if (g & (0x80 >> i)) {
+            color_buf[j] = CODE_1;
+        } else {
+            color_buf[j] = CODE_0;
+        }
+        j++;
+    }
+    for (i = 0; i < 8; i++) {
+        if (r & (0x80 >> i)) {
+            color_buf[j] = CODE_1;
+        } else {
+            color_buf[j] = CODE_0;
+        }
+        j++;
+    }
+    for (i = 0; i < 8; i++) {
+        if (b & (0x80 >> i)) {
+            color_buf[j] = CODE_1;
+        } else {
+            color_buf[j] = CODE_0;
+        }
+        j++;
+    }
+}
+#endif
+
+/*********************************************************************
+ * @fn      w2812_sync
+ *
+ * @brief   Write data to LEDs
+ *
+ * @return  none
+ */
+void w2812_sync()
+{
+#if LED_MODE == LED_SPI_MODE
+    while(SPI1_DMA_TX_CH->CNTR!=0);
+    DMA_ClearFlag(DMA1_FLAG_TC3);
+    DMA_Cmd(SPI1_DMA_TX_CH, DISABLE);
+    SPI1_DMA_TX_CH->CNTR = COLOR_BUFFER_LEN;
+    DMA_Cmd(SPI1_DMA_TX_CH, ENABLE);
+#elif  LED_MODE == LED_PWM_MODE
+    while(DMA_GetCurrDataCounter(TIM_DMA_CH1_CH)!=0);
+    DMA_SetCurrDataCounter( TIM_DMA_CH1_CH, COLOR_BUFFER_LEN);
+    DMA_Cmd( TIM_DMA_CH1_CH, ENABLE);
+    TIM_Cmd( TIM1, ENABLE);
+#endif
+}
+
+#define MAX_STEP (200)
+/*********************************************************************
+ * @fn      interpolateColors
+ *
+ * @brief   Set the pixel color of an LED
+ *
+ * @param   color1 - The color at the beginning
+ *          color2 - The color at the ending
+ *          step   -
+ *
+ *
+ * @return  color
+ */
+uint32_t interpolateColors(uint32_t color1, uint32_t color2, uint8_t step)
+{
+    uint8_t r1 = (color1 >> 16) & 0xFF;
+    uint8_t g1 = (color1 >> 8) & 0xFF;
+    uint8_t b1 = color1 & 0xFF;
+
+    uint8_t r2 = (color2 >> 16) & 0xFF;
+    uint8_t g2 = (color2 >> 8) & 0xFF;
+    uint8_t b2 = color2 & 0xFF;
+
+    float tmp1 = (r2 - r1) * (step / (float) MAX_STEP);
+    float tmp2 = (g2 - g1) * (step / (float) MAX_STEP);
+    float tmp3 = (b2 - b1) * (step / (float) MAX_STEP);
+
+    uint8_t r = (uint8_t) (r1 + tmp1);
+    uint8_t g = (uint8_t) (g1 + tmp2);
+    uint8_t b = (uint8_t) (b1 + tmp3);
+
+    return ((uint32_t) r << 16) | ((uint32_t) g << 8) | b;
+}
+
+uint32_t color_list[] = {
+        0xff0000,
+        0x00ff00,
+        0x0000ff,
+        0xffff00,
+        0xff00ff,
+        0x00ffff,
+        0xffffff,
+//        0x000000,
+        };
+
+/*********************************************************************
+ * @fn      led_example_0
+ *
+ * @brief   In this example, all leds will gradually change from one color to another
+ *
+ * @return  none
+ */
+void led_example_0(void)
+{
+    uint32_t i = 0, j = 0;
+    uint32_t c = 0x0f0f00;
+    while(1) {
+        c = color_list[i];
+        uint32_t next_color = color_list[i+1];
+        i++;
+        if((i+1)>=LIST_SIZE(color_list)) {
+            i=0;
+        }
+        for(j = 0; j<MAX_STEP;j+=1) {
+            uint32_t color = interpolateColors(c,next_color,j);
+            for (int var = 0; var < Pixel_NUM; ++var) {
+                setPixelColor(var,hex2rgb(color));
+
+            }
+            w2812_sync();
+            Delay_Ms(10);
+
+        }
+
+    }
+}
+
+/*********************************************************************
+ * @fn      led_example_1
+ *
+ * @brief   In this example, all leds will blink
+ *
+ * @return  none
+ */
+void led_example_1(void)
+{
+    uint32_t i = 0;
+    uint32_t c = 0x0f0f00;
+    while(1) {
+        c = color_list[i];
+        printf("color[%d] %08x  %08x \n",i,c,color_list[i]);
+        i++;
+        if(i>=LIST_SIZE(color_list)) {
+            i=0;
+        }
+        for (int var = 0; var < Pixel_NUM; ++var) {
+            setPixelColor(var,hex2rgb(c));
+        }
+        w2812_sync();
+        Delay_Ms(100);
+
+    }
+}
+
+/*********************************************************************
+ * @fn      led_example_2
+ *
+ * @brief   In this example, the leds will blink one by one
+ *
+ * @return  none
+ */
+void led_example_2(void)
+{
+    uint32_t i = 0;
+    uint32_t c = 0x0f0f00;
+    while(1) {
+        c = color_list[i];
+        printf("color[%d] %08x  %08x \n",i,c,color_list[i]);
+        i++;
+        if(i>=LIST_SIZE(color_list)) {
+            i=0;
+        }
+
+        for (int var = 0; var < Pixel_NUM; var+=1) {
+            setPixelColor(var, hex2rgb(c));
+            w2812_sync();
+            Delay_Ms(100);
+            setPixelColor(var,0,0,0);
+            w2812_sync();
+        }
+    }
+}
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    uint16_t i = 0;
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
+    Delay_Init();
+    USART_Printf_Init(115200);
+    printf("SystemClk:%d\r\n", SystemCoreClock);
+
+    // Turn off all LEDs
+    for (i = 0; i < Pixel_NUM; i++) {
+        setPixelColor(i, 0, 0, 0);
+    }
+#if LED_MODE == LED_SPI_MODE
+    SPI_1Lines_HalfDuplex_Init();
+    SPI1_DMA_Init();
+    DMA_Cmd(SPI1_DMA_TX_CH, ENABLE);
+#elif  LED_MODE == LED_PWM_MODE
+    TIM1_Init();
+    DMA1_Init();
+    DMA_Cmd( TIM_DMA_CH1_CH, ENABLE);
+#endif
+
+    led_example_0();
+//    led_example_2();
+
+}
+
+#if  LED_MODE == LED_PWM_MODE
+void DMA1_Channel5_IRQHandler(void)
+{
+    if (DMA_GetFlagStatus( DMA1_FLAG_TC5)) {
+        TIM_Cmd( TIM1, DISABLE);
+        DMA_Cmd( TIM_DMA_CH1_CH, DISABLE);
+        DMA_ClearFlag( DMA1_FLAG_TC5);
+    }
+}
+#endif
diff --git a/EVT/EXAM/IWDG/User/system_ch32v20x.c b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c
similarity index 99%
rename from EVT/EXAM/IWDG/User/system_ch32v20x.c
rename to EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/IWDG/User/system_ch32v20x.c
+++ b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/IWDG/User/system_ch32v20x.h b/EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.h
similarity index 100%
rename from EVT/EXAM/IWDG/User/system_ch32v20x.h
rename to EVT/EXAM/APPLICATION/WS2812_LED/User/system_ch32v20x.h
diff --git a/EVT/EXAM/IWDG/IWDG.wvproj b/EVT/EXAM/APPLICATION/WS2812_LED/WS2812_LED.wvproj
similarity index 100%
rename from EVT/EXAM/IWDG/IWDG.wvproj
rename to EVT/EXAM/APPLICATION/WS2812_LED/WS2812_LED.wvproj
diff --git a/EVT/EXAM/OPA/.cproject b/EVT/EXAM/BKP/BKP/.cproject
similarity index 97%
rename from EVT/EXAM/OPA/.cproject
rename to EVT/EXAM/BKP/BKP/.cproject
index 7e5eb99..93c33ac 100644
--- a/EVT/EXAM/OPA/.cproject
+++ b/EVT/EXAM/BKP/BKP/.cproject
@@ -45,11 +45,11 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.932587520" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1091914013" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.2003631682" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.1819910041" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1179366128" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/BKP}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/GPIO_Toggle}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
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 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
diff --git a/EVT/EXAM/BKP/.project b/EVT/EXAM/BKP/BKP/.project
similarity index 83%
rename from EVT/EXAM/BKP/.project
rename to EVT/EXAM/BKP/BKP/.project
index 705f6c6..45d5bbe 100644
--- a/EVT/EXAM/BKP/.project
+++ b/EVT/EXAM/BKP/BKP/.project
@@ -35,27 +35,27 @@
     <link>
       <name>Core</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Core</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
     </link>
     <link>
       <name>Debug</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Debug</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
     </link>
     <link>
       <name>Ld</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Ld</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
     </link>
     <link>
       <name>Peripheral</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Peripheral</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
     </link>
     <link>
       <name>Startup</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Startup</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
     </link>
   </linkedResources>
 </projectDescription>
diff --git a/EVT/EXAM/IWDG/.template b/EVT/EXAM/BKP/BKP/.template
similarity index 94%
rename from EVT/EXAM/IWDG/.template
rename to EVT/EXAM/BKP/BKP/.template
index 3ef64f1..fe2049d 100644
--- a/EVT/EXAM/IWDG/.template
+++ b/EVT/EXAM/BKP/BKP/.template
@@ -1,6 +1,6 @@
 Mcu Type=CH32V20x
 Address=0x08000000
-Target Path=obj/IWDG.hex
+Target Path=obj\BKP.hex
 Erase All=true
 Program=true
 Verify=true
@@ -14,3 +14,4 @@ Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH
 
 PeripheralVersion=1.0
 MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/OPA/OPA.wvproj b/EVT/EXAM/BKP/BKP/BKP.wvproj
similarity index 100%
rename from EVT/EXAM/OPA/OPA.wvproj
rename to EVT/EXAM/BKP/BKP/BKP.wvproj
diff --git a/EVT/EXAM/TOUCHKEY/User/ch32v20x_conf.h b/EVT/EXAM/BKP/BKP/User/ch32v20x_conf.h
similarity index 100%
rename from EVT/EXAM/TOUCHKEY/User/ch32v20x_conf.h
rename to EVT/EXAM/BKP/BKP/User/ch32v20x_conf.h
diff --git a/EVT/EXAM/BKP/User/ch32v20x_it.c b/EVT/EXAM/BKP/BKP/User/ch32v20x_it.c
similarity index 100%
rename from EVT/EXAM/BKP/User/ch32v20x_it.c
rename to EVT/EXAM/BKP/BKP/User/ch32v20x_it.c
diff --git a/EVT/EXAM/OPA/User/ch32v20x_it.h b/EVT/EXAM/BKP/BKP/User/ch32v20x_it.h
similarity index 100%
rename from EVT/EXAM/OPA/User/ch32v20x_it.h
rename to EVT/EXAM/BKP/BKP/User/ch32v20x_it.h
diff --git a/EVT/EXAM/BKP/User/main.c b/EVT/EXAM/BKP/BKP/User/main.c
similarity index 100%
rename from EVT/EXAM/BKP/User/main.c
rename to EVT/EXAM/BKP/BKP/User/main.c
diff --git a/EVT/EXAM/BKP/User/system_ch32v20x.c b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c
similarity index 99%
rename from EVT/EXAM/BKP/User/system_ch32v20x.c
rename to EVT/EXAM/BKP/BKP/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/BKP/User/system_ch32v20x.c
+++ b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/OPA/User/system_ch32v20x.h b/EVT/EXAM/BKP/BKP/User/system_ch32v20x.h
similarity index 100%
rename from EVT/EXAM/OPA/User/system_ch32v20x.h
rename to EVT/EXAM/BKP/BKP/User/system_ch32v20x.h
diff --git a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BLE_UART/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BLE_USB/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c
index 6a3f498..4c5042c 100644
--- a/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BackupUpgrade_IAP/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/BackupUpgrade_OTA/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Broadcaster/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/CentPeri/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Central/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/CyclingSensor/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/.cproject b/EVT/EXAM/BLE/Direct_Test_Mode/.cproject
index dc06208..8f24b5f 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/.cproject
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/.cproject
@@ -56,11 +56,12 @@
 							</tool>
 							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.1567947810" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/UART}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/APP/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/SRC/Core}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/SRC/Startup}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/SRC/Debug}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/SRC/Peripheral/inc}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/APP/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Profile/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/HAL/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/LIB}&quot;"/>
@@ -133,11 +134,11 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="APP"/>
+						<entry excluding="include/cdc.h|cdc.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="APP"/>
 						<entry excluding="Profile" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="HAL"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="LIB"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Profile"/>
-						<entry excluding="Startup/startup_ch32v20x_D8.S|Startup/startup_ch32v20x_D6.S|Ld/" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="SRC"/>
+						<entry excluding="Ld/|Startup/startup_ch32v20x_D6.S|Startup/startup_ch32v20x_D8.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="SRC"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -159,5 +160,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/buf.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/buf.c
index 6f13b67..1988ec3 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/buf.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/buf.c
@@ -18,6 +18,18 @@
 #else
 #define SIMPLE_BUF_DBG(...)
 #endif
+
+/*********************************************************************
+ * @fn      simple_buf_create
+ *
+ * @brief   Create a simple_buf structure object.
+ *
+ * @param   buf    -   defined simple_buf structural object.
+ *          buf_pool  - a pointer to the buffer where data is stored.
+ *          pool_size - the size of the buffer.
+ *
+ * @return  none
+ */
 struct simple_buf *simple_buf_create(struct simple_buf *buf, 
             uint8_t *buf_pool, uint16_t pool_size)
 {
@@ -29,13 +41,24 @@ struct simple_buf *simple_buf_create(struct simple_buf *buf,
     return buf;
 }
 
+/*********************************************************************
+ * @fn      simple_buf_add
+ *
+ * @brief   Add data to the buf object.
+ *
+ * @param   buf  -  defined simple_buf structural object.
+ *          len  -  length of the data to be added.
+ *
+ * @return  none
+ */
 void *simple_buf_add(struct simple_buf *buf, size_t len)
 {
-	uint8_t *tail = buf->data + buf->len;
+    uint8_t *tail = buf->data + buf->len;
 
     SIMPLE_BUF_DBG("buf %p add len %ld\n", buf, len);
 
-    if((buf->size - (buf->data - buf->__buf) - buf->len) < len) {
+    if((buf->size - (buf->data - buf->__buf) - buf->len) < len)
+    {
         SIMPLE_BUF_DBG("simple_buf_add: no memory\n");
         while(1);
     }
@@ -45,39 +68,71 @@ void *simple_buf_add(struct simple_buf *buf, size_t len)
     return tail;
 }
 
+/*********************************************************************
+ * @fn      simple_buf_pull
+ *
+ * @brief   pull data from the buf object.
+ *
+ * @param   buf  -  defined simple_buf structural object.
+ *          len  -  The length of data to be retrieved.
+ *
+ * @return  none
+ */
 void *simple_buf_pull(struct simple_buf *buf, size_t len)
 {
-	void *data = buf->data;
+    void *data = buf->data;
 
     SIMPLE_BUF_DBG("buf %p pull len %ld\n", buf, len);
 
-    if(buf->len < len) {
+    if(buf->len < len)
+    {
         SIMPLE_BUF_DBG("simple_buf_pull: no data\n");
         while(1);
     }
 
-	buf->len -= len;
-	buf->data += len;
+    buf->len -= len;
+    buf->data += len;
 
-	return data;
+    return data;
 }
 
+/*********************************************************************
+ * @fn      simple_buf_add_mem
+ *
+ * @brief   Add a segment of memory data to the buf object.
+ *
+ * @param   buf  -  defined simple_buf structural object.
+ *          mem  -  a pointer to the memory data to be added.
+ *          len  -  the length of the data to be added.
+ *
+ * @return  The function returns a pointer to the starting position of the added data.
+ */
 void *simple_buf_add_mem(struct simple_buf *buf, const void *mem,
-			     size_t len)
+                 size_t len)
 {
     SIMPLE_BUF_DBG("buf %p add len %ld\n", buf, len);
 
-	return memcpy(simple_buf_add(buf, len), mem, len);
+    return memcpy(simple_buf_add(buf, len), mem, len);
 }
 
+/*********************************************************************
+ * @fn      simple_buf_add_u8
+ *
+ * @brief   Add an 8-bit unsigned integer to the buf object.
+ *
+ * @param   buf  -  defined simple_buf structural object.
+ *          val  -  the 8-bit unsigned integer to be added.
+ *
+ * @return  The function returns a pointer to the starting position of the added data.
+ */
 uint8_t *simple_buf_add_u8(struct simple_buf *buf, uint8_t val)
 {
-	uint8_t *u8;
+    uint8_t *u8;
 
     SIMPLE_BUF_DBG("buf %p add val 0x%02x\n", buf, val);
 
-	u8 = simple_buf_add(buf, 1);
-	*u8 = val;
+    u8 = simple_buf_add(buf, 1);
+    *u8 = val;
 
-	return u8;
+    return u8;
 }
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c
new file mode 100644
index 0000000..71ec1d9
--- /dev/null
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/ch32v20x_usbfs_device.c
@@ -0,0 +1,796 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v20x_usbfs_device.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2022/08/20
+* Description        : This file provides all the USBOTG firmware functions.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#include "ch32v20x_usbfs_device.h"
+#include "buf.h"
+#include "uart.h"
+/*******************************************************************************/
+/* Variable Definition */
+/* Global */
+const    uint8_t  *pUSBFS_Descr;
+
+/* Setup Request */
+volatile uint8_t  USBFS_SetupReqCode;
+volatile uint8_t  USBFS_SetupReqType;
+volatile uint16_t USBFS_SetupReqValue;
+volatile uint16_t USBFS_SetupReqIndex;
+volatile uint16_t USBFS_SetupReqLen;
+
+/* USB Device Status */
+volatile uint8_t  USBFS_DevConfig;
+volatile uint8_t  USBFS_DevAddr;
+volatile uint8_t  USBFS_DevSleepStatus;
+volatile uint8_t  USBFS_DevEnumStatus;
+
+/* Endpoint Buffer */
+__attribute__ ((aligned(4))) uint8_t USBFS_EP0_Buf[ DEF_USBD_UEP0_SIZE ];
+__attribute__ ((aligned(4))) uint8_t USBFS_EP1_Buf[ DEF_USBD_ENDP1_SIZE ];
+__attribute__ ((aligned(4))) uint8_t USBFS_EP2_Buf[ DEF_USBD_ENDP2_SIZE ];
+__attribute__ ((aligned(4))) uint8_t USBFS_EP3_Buf[ DEF_USBD_ENDP3_SIZE ];
+
+/* USB IN Endpoint Busy Flag */
+volatile uint8_t  USBFS_Endp_Busy[ DEF_UEP_NUM ];
+
+/******************************************************************************/
+/* Interrupt Service Routine Declaration*/
+void USBHD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      USBFS_RCC_Init
+ *
+ * @brief   Initializes the usbotg clock configuration.
+ *
+ * @return  none
+ */
+void USBFS_RCC_Init( void )
+{
+    if( SystemCoreClock == 144000000 )
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div3 );
+    }
+    else if( SystemCoreClock == 96000000 )
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div2 );
+    }
+    else if( SystemCoreClock == 48000000 )
+    {
+        RCC_USBCLKConfig( RCC_USBCLKSource_PLLCLK_Div1 );
+    }
+    RCC_AHBPeriphClockCmd( RCC_AHBPeriph_OTG_FS, ENABLE );
+}
+
+/*********************************************************************
+ * @fn      USBFS_Device_Endp_Init
+ *
+ * @brief   Initializes USB device endpoints.
+ *
+ * @return  none
+ */
+void USBFS_Device_Endp_Init( void )
+{
+    uint8_t i;
+
+    USBOTG_FS->UEP4_1_MOD = USBFS_UEP1_TX_EN;
+    USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_RX_EN|USBFS_UEP3_TX_EN;
+
+    USBOTG_FS->UEP0_DMA = (uint32_t)USBFS_EP0_Buf;
+
+    USBOTG_FS->UEP1_DMA = (uint32_t)USBFS_EP1_Buf;
+    USBOTG_FS->UEP2_DMA = (uint32_t)UART2_Tx_Buf;
+    USBOTG_FS->UEP3_DMA = (uint32_t)USBFS_EP3_Buf;
+
+    USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK;
+    USBOTG_FS->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK;
+
+    USBOTG_FS->UEP1_TX_LEN = 0;
+    USBOTG_FS->UEP3_TX_LEN = 0;
+
+    USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK;
+    USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
+    USBOTG_FS->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
+
+    /* Clear End-points Busy Status */
+    for( i=0; i<DEF_UEP_NUM; i++ )
+    {
+        USBFS_Endp_Busy[ i ] = 0;
+    }
+}
+
+/*********************************************************************
+ * @fn      USBFS_Device_Init
+ *
+ * @brief   Initializes USB device.
+ *
+ * @return  none
+ */
+void USBFS_Device_Init( FunctionalState sta )
+{
+    if( sta )
+    {
+        USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
+        Delay_Us( 10 );
+        USBOTG_H_FS->BASE_CTRL = 0x00;
+        USBOTG_FS->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER;
+        USBOTG_FS->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
+        USBFS_Device_Endp_Init( );
+        USBOTG_FS->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN;
+        NVIC_EnableIRQ( USBHD_IRQn );
+    }
+    else
+    {
+        USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
+        Delay_Us( 10 );
+        USBOTG_FS->BASE_CTRL = 0x00;
+        NVIC_DisableIRQ( USBHD_IRQn );
+    }
+}
+
+/*********************************************************************
+ * @fn      DevEP2_OUT_Deal
+ *
+ * @brief   �˵�2���ݴ���
+ *
+ * @return  none
+ */
+void DevEP2_OUT_Deal( uint8_t l )
+{ /* �û����Զ��� */
+    uint8_t i;
+
+    for(i = 0; i < l; i++)
+    {
+        simple_buf_add_u8(usb_buf, UART2_Tx_Buf[i]);
+    }
+    atomic_set(&usb_flag, USB_STATUS_RCV_END);
+}
+
+/*********************************************************************
+ * @fn      USBSendData
+ *
+ * @brief   �������ݸ�����
+ *
+ * @return  none
+ */
+uint8_t USBSendData(uint8_t *buf, uint16_t len)
+{
+
+    USBFS_Endp_DataUp(DEF_UEP3, buf, len, DEF_UEP_CPY_LOAD);
+
+    return 0;
+}
+
+/*********************************************************************
+ * @fn      USBFS_Endp_DataUp
+ *
+ * @brief   USBFS device data upload
+ *
+ * @return  none
+ */
+uint8_t USBFS_Endp_DataUp(uint8_t endp, uint8_t *pbuf, uint16_t len, uint8_t mod)
+{
+    uint8_t endp_mode;
+    uint8_t buf_load_offset;
+
+    /* DMA config, endp_ctrl config, endp_len config */
+    if( (endp>=DEF_UEP1) && (endp<=DEF_UEP7) )
+    {
+        if( USBFS_Endp_Busy[ endp ] == 0 )
+        {
+            if( (endp == DEF_UEP1) || (endp == DEF_UEP4) )
+            {
+                /* endp1/endp4 */
+                endp_mode = USBFSD_UEP_MOD(0);
+                if( endp == DEF_UEP1 )
+                {
+                    endp_mode = (uint8_t)(endp_mode>>4);
+                }
+            }
+            else if( (endp == DEF_UEP2) || (endp == DEF_UEP3) )
+            {
+                /* endp2/endp3 */
+                endp_mode = USBFSD_UEP_MOD(1);
+                if( endp == DEF_UEP3 )
+                {
+                    endp_mode = (uint8_t)(endp_mode>>4);
+                }
+            }
+            else if( (endp == DEF_UEP5) || (endp == DEF_UEP6) )
+            {
+                /* endp5/endp6 */
+                endp_mode = USBFSD_UEP_MOD(2);
+                if( endp == DEF_UEP6 )
+                {
+                    endp_mode = (uint8_t)(endp_mode>>4);
+                }
+            }
+            else
+            {
+                /* endp7 */
+                endp_mode = USBFSD_UEP_MOD(3);
+            }
+
+            if( endp_mode & USBFSD_UEP_TX_EN )
+            {
+                if( endp_mode & USBFSD_UEP_RX_EN )
+                {
+                    buf_load_offset = 64;
+                }
+                else
+                {
+                    buf_load_offset = 0;
+                }
+
+                if( buf_load_offset == 0 )
+                {
+                    if( mod == DEF_UEP_DMA_LOAD )
+                    {
+                        /* DMA mode */
+                        USBFSD_UEP_DMA(endp) = (uint16_t)(uint32_t)pbuf;
+                    }
+                    else
+                    {
+                        /* copy mode */
+                        memcpy( USBFSD_UEP_BUF(endp), pbuf, len );
+                    }
+                }
+                else
+                {
+                    memcpy( USBFSD_UEP_BUF(endp)+buf_load_offset, pbuf, len );
+                }
+                /* Set end-point busy */
+                USBFS_Endp_Busy[ endp ] = 0x01;
+                /* tx length */
+                USBFSD_UEP_TLEN(endp) = len;
+                /* response ack */
+                USBFSD_UEP_CTRL(endp) = (USBFSD_UEP_CTRL(endp) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK;
+            }
+        }
+        else
+        {
+            return 1;
+        }
+    }
+    else
+    {
+        return 1;
+    }
+    return 0;
+}
+
+
+/*********************************************************************
+ * @fn      USBHD_IRQHandler
+ *
+ * @brief   This function handles HD-FS exception.
+ *
+ * @return  none
+ */
+void USBHD_IRQHandler( void )
+{
+    uint8_t  intflag, intst, errflag;
+    uint16_t len;
+    uint32_t baudrate;
+
+    intflag = USBOTG_FS->INT_FG;
+    intst   = USBOTG_FS->INT_ST;
+
+    if( intflag & USBFS_UIF_TRANSFER )
+    {
+        switch (intst & USBFS_UIS_TOKEN_MASK)
+        {
+            /* data-in stage processing */
+            case USBFS_UIS_TOKEN_IN:
+                switch ( intst & ( USBFS_UIS_TOKEN_MASK | USBFS_UIS_ENDP_MASK ) )
+                {
+                    /* end-point 0 data in interrupt */
+                    case USBFS_UIS_TOKEN_IN | DEF_UEP0:
+                        if( USBFS_SetupReqLen == 0 )
+                        {
+                            USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK;
+                        }
+                        if ( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD )
+                        {
+                            /* Non-standard request endpoint 0 Data upload */
+                        }
+                        else
+                        {
+                            /* Standard request endpoint 0 Data upload */
+                            switch( USBFS_SetupReqCode )
+                            {
+                                case USB_GET_DESCRIPTOR:
+                                        len = USBFS_SetupReqLen >= DEF_USBD_UEP0_SIZE ? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen;
+                                        memcpy( USBFS_EP0_Buf, pUSBFS_Descr, len );
+                                        USBFS_SetupReqLen -= len;
+                                        pUSBFS_Descr += len;
+                                        USBOTG_FS->UEP0_TX_LEN   = len;
+                                        USBOTG_FS->UEP0_TX_CTRL ^= USBFS_UEP_T_TOG;
+                                        break;
+
+                                case USB_SET_ADDRESS:
+                                        USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR & USBFS_UDA_GP_BIT) | USBFS_DevAddr;
+                                        break;
+
+                                default:
+                                        break;
+                            }
+                        }
+                        break;
+
+                    /* end-point 1 data in interrupt */
+                    case ( USBFS_UIS_TOKEN_IN | DEF_UEP1 ):
+                        USBOTG_FS->UEP1_TX_CTRL ^= USBFS_UEP_T_TOG;
+                        USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK;
+                        USBFS_Endp_Busy[ DEF_UEP1 ] = 0;
+                        break;
+
+                    /* end-point 3 data in interrupt */
+                    case ( USBFS_UIS_TOKEN_IN | DEF_UEP3 ):
+                        USBOTG_FS->UEP3_TX_CTRL ^= USBFS_UEP_T_TOG;
+                        USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK;
+                        USBFS_Endp_Busy[ DEF_UEP3 ] = 0;
+//                        Uart.USB_Up_IngFlag = 0x00;
+                        break;
+
+                    default :
+                        break;
+                }
+                break;
+
+            /* data-out stage processing */
+            case USBFS_UIS_TOKEN_OUT:
+                switch ( intst & ( USBFS_UIS_TOKEN_MASK | USBFS_UIS_ENDP_MASK ) )
+                {
+                    /* end-point 0 data out interrupt */
+                    case USBFS_UIS_TOKEN_OUT | DEF_UEP0:
+                        len = USBOTG_FS->RX_LEN;
+                        if ( intst & USBFS_UIS_TOG_OK )
+                        {
+                            if ( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD )
+                            {
+                                /* Non-standard request end-point 0 Data download */
+                                USBFS_SetupReqLen = 0;
+                                /* Non-standard request end-point 0 Data download */
+                                if( USBFS_SetupReqCode == CDC_SET_LINE_CODING )
+                                {
+
+                                }
+                            }
+                            else
+                            {
+                                /* Standard request end-point 0 Data download */
+                                /* Add your code here */
+                            }
+                            if( USBFS_SetupReqLen == 0 )
+                            {
+                                USBOTG_FS->UEP0_TX_LEN  = 0;
+                                USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK;
+                            }
+                        }
+                        break;
+
+                    /* end-point 1 data out interrupt */
+                    case USBFS_UIS_TOKEN_OUT | DEF_UEP2:
+                        USBOTG_FS->UEP2_RX_CTRL ^= USBFS_UEP_R_TOG;
+                        DevEP2_OUT_Deal(USBOTG_FS->RX_LEN);
+                        break;
+
+                    default:
+                        break;
+                }
+                break;
+
+            /* Setup stage processing */
+            case USBFS_UIS_TOKEN_SETUP:
+                USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_NAK;
+                USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_NAK;
+                /* Store All Setup Values */
+                USBFS_SetupReqType  = pUSBFS_SetupReqPak->bRequestType;
+                USBFS_SetupReqCode  = pUSBFS_SetupReqPak->bRequest;
+                USBFS_SetupReqLen   = pUSBFS_SetupReqPak->wLength;
+                USBFS_SetupReqValue = pUSBFS_SetupReqPak->wValue;
+                USBFS_SetupReqIndex = pUSBFS_SetupReqPak->wIndex;
+                len = 0;
+                errflag = 0;
+                if ( ( USBFS_SetupReqType & USB_REQ_TYP_MASK ) != USB_REQ_TYP_STANDARD )
+                {
+                    /* usb non-standard request processing */
+                    if( USBFS_SetupReqType & USB_REQ_TYP_CLASS )
+                    {
+                        /* Class requests */
+                        switch( USBFS_SetupReqCode )
+                        {
+                            case CDC_GET_LINE_CODING:
+                                break;
+
+                            case CDC_SET_LINE_CODING:
+                                break;
+
+                            case CDC_SET_LINE_CTLSTE:
+                                break;
+
+                            case CDC_SEND_BREAK:
+                                break;
+
+                            default:
+                                errflag = 0xff;
+                                break;
+                        }
+                    }
+                    else if( USBFS_SetupReqType & USB_REQ_TYP_VENDOR )
+                    {
+                        /* Manufacturer request */
+                    }
+                    else
+                    {
+                        errflag = 0xFF;
+                    }
+
+                    /* Copy Descriptors to Endp0 DMA buffer */
+                    len = (USBFS_SetupReqLen >= DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen;
+                    memcpy( USBFS_EP0_Buf, pUSBFS_Descr, len );
+                    pUSBFS_Descr += len;
+                }
+                else
+                {
+                    /* usb standard request processing */
+                    switch( USBFS_SetupReqCode )
+                    {
+                        /* get device/configuration/string/report/... descriptors */
+                        case USB_GET_DESCRIPTOR:
+                            switch( (uint8_t)( USBFS_SetupReqValue >> 8 ) )
+                            {
+                                /* get usb device descriptor */
+                                case USB_DESCR_TYP_DEVICE:
+                                    pUSBFS_Descr = MyDevDescr;
+                                    len = DEF_USBD_DEVICE_DESC_LEN;
+                                    break;
+
+                                /* get usb configuration descriptor */
+                                case USB_DESCR_TYP_CONFIG:
+                                    pUSBFS_Descr = MyCfgDescr;
+                                    len = DEF_USBD_CONFIG_DESC_LEN;
+                                    break;
+
+                                /* get usb string descriptor */
+                                case USB_DESCR_TYP_STRING:
+                                    switch( (uint8_t)( USBFS_SetupReqValue & 0xFF ) )
+                                    {
+                                        /* Descriptor 0, Language descriptor */
+                                        case DEF_STRING_DESC_LANG:
+                                            pUSBFS_Descr = MyLangDescr;
+                                            len = DEF_USBD_LANG_DESC_LEN;
+                                            break;
+
+                                        /* Descriptor 1, Manufacturers String descriptor */
+                                        case DEF_STRING_DESC_MANU:
+                                            pUSBFS_Descr = MyManuInfo;
+                                            len = DEF_USBD_MANU_DESC_LEN;
+                                            break;
+
+                                        /* Descriptor 2, Product String descriptor */
+                                        case DEF_STRING_DESC_PROD:
+                                            pUSBFS_Descr = MyProdInfo;
+                                            len = DEF_USBD_PROD_DESC_LEN;
+                                            break;
+
+                                        /* Descriptor 3, Serial-number String descriptor */
+                                        case DEF_STRING_DESC_SERN:
+                                            pUSBFS_Descr = MySerNumInfo;
+                                            len = DEF_USBD_SN_DESC_LEN;
+                                            break;
+
+                                        default:
+                                            errflag = 0xFF;
+                                            break;
+                                    }
+                                    break;
+
+                                default :
+                                    errflag = 0xFF;
+                                    break;
+                            }
+
+                            /* Copy Descriptors to Endp0 DMA buffer */
+                            if( USBFS_SetupReqLen>len )
+                            {
+                                USBFS_SetupReqLen = len;
+                            }
+                            len = (USBFS_SetupReqLen >= DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen;
+                            memcpy( USBFS_EP0_Buf, pUSBFS_Descr, len );
+                            pUSBFS_Descr += len;
+                            break;
+
+                        /* Set usb address */
+                        case USB_SET_ADDRESS:
+                            USBFS_DevAddr = (uint8_t)( USBFS_SetupReqValue & 0xFF );
+                            break;
+
+                        /* Get usb configuration now set */
+                        case USB_GET_CONFIGURATION:
+                            USBFS_EP0_Buf[0] = USBFS_DevConfig;
+                            if ( USBFS_SetupReqLen > 1 )
+                            {
+                                USBFS_SetupReqLen = 1;
+                            }
+                            break;
+
+                        /* Set usb configuration to use */
+                        case USB_SET_CONFIGURATION:
+                            USBFS_DevConfig = (uint8_t)( USBFS_SetupReqValue & 0xFF );
+                            USBFS_DevEnumStatus = 0x01;
+                            break;
+
+                        /* Clear or disable one usb feature */
+                        case USB_CLEAR_FEATURE:
+                            if ( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE )
+                            {
+                                /* clear one device feature */
+                                if( (uint8_t)( USBFS_SetupReqValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP )
+                                {
+                                    /* clear usb sleep status, device not prepare to sleep */
+                                    USBFS_DevSleepStatus &= ~0x01;
+                                }
+                            }
+                            else if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP )
+                            {
+                                /* Clear End-point Feature */
+                                if( (uint8_t)( USBFS_SetupReqValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT )
+                                {
+                                    switch( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) )
+                                    {
+                                        case ( DEF_UEP_IN | DEF_UEP1 ):
+                                            /* Set End-point 1 IN NAK */
+                                            USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
+                                            break;
+
+                                        case ( DEF_UEP_OUT | DEF_UEP2 ):
+                                            /* Set End-point 2 OUT ACK */
+                                            USBOTG_FS->UEP2_RX_CTRL = USBFS_UEP_R_RES_ACK;
+                                            break;
+
+                                        case ( DEF_UEP_IN | DEF_UEP3 ):
+                                            /* Set End-point 3 IN NAK */
+                                            USBOTG_FS->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
+                                            break;
+
+                                        default:
+                                            errflag = 0xFF;
+                                            break;
+                                    }
+                                }
+                                else
+                                {
+                                    errflag = 0xFF;
+                                }
+                            }
+                            else
+                            {
+                                errflag = 0xFF;
+                            }
+                            break;
+
+                        /* set or enable one usb feature */
+                        case USB_SET_FEATURE:
+                            if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE )
+                            {
+                                /* Set Device Feature */
+                                if( (uint8_t)( USBFS_SetupReqValue & 0xFF ) == USB_REQ_FEAT_REMOTE_WAKEUP )
+                                {
+                                    if( MyCfgDescr[ 7 ] & 0x20 )
+                                    {
+                                        /* Set Wake-up flag, device prepare to sleep */
+                                        USBFS_DevSleepStatus |= 0x01;
+                                    }
+                                    else
+                                    {
+                                        errflag = 0xFF;
+                                    }
+                                }
+                                else
+                                {
+                                    errflag = 0xFF;
+                                }
+                            }
+                            else if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP )
+                            {
+                                /* Set End-point Feature */
+                                if( (uint8_t)( USBFS_SetupReqValue & 0xFF ) == USB_REQ_FEAT_ENDP_HALT )
+                                {
+                                    /* Set end-points status stall */
+                                    switch( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) )
+                                    {
+                                        case ( DEF_UEP_IN | DEF_UEP1 ):
+                                            /* Set End-point 1 IN STALL */
+                                            USBOTG_FS->UEP1_TX_CTRL = ( USBOTG_FS->UEP1_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
+                                            break;
+
+                                        case ( DEF_UEP_OUT | DEF_UEP2 ):
+                                            /* Set End-point 2 OUT STALL */
+                                            USBOTG_FS->UEP2_RX_CTRL = ( USBOTG_FS->UEP2_RX_CTRL & ~USBFS_UEP_R_RES_MASK ) | USBFS_UEP_R_RES_STALL;
+                                            break;
+
+                                        case ( DEF_UEP_IN | DEF_UEP3 ):
+                                            /* Set End-point 3 IN STALL */
+                                            USBOTG_FS->UEP3_TX_CTRL = ( USBOTG_FS->UEP3_TX_CTRL & ~USBFS_UEP_T_RES_MASK ) | USBFS_UEP_T_RES_STALL;
+                                            break;
+
+                                        default:
+                                            errflag = 0xFF;
+                                            break;
+                                    }
+                                }
+                                else
+                                {
+                                    errflag = 0xFF;
+                                }
+                            }
+                            else
+                            {
+                                errflag = 0xFF;
+                            }
+                            break;
+
+                        /* This request allows the host to select another setting for the specified interface  */
+                        case USB_GET_INTERFACE:
+                            USBFS_EP0_Buf[0] = 0x00;
+                            if ( USBFS_SetupReqLen > 1 )
+                            {
+                                USBFS_SetupReqLen = 1;
+                            }
+                            break;
+
+                        case USB_SET_INTERFACE:
+                            break;
+
+                        /* host get status of specified device/interface/end-points */
+                        case USB_GET_STATUS:
+                            USBFS_EP0_Buf[ 0 ] = 0x00;
+                            USBFS_EP0_Buf[ 1 ] = 0x00;
+                            if ( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_DEVICE )
+                            {
+                                if( USBFS_DevSleepStatus & 0x01 )
+                                {
+                                    USBFS_EP0_Buf[ 0 ] = 0x02;
+                                }
+                            }
+                            else if( ( USBFS_SetupReqType & USB_REQ_RECIP_MASK ) == USB_REQ_RECIP_ENDP )
+                            {
+                                switch( (uint8_t)( USBFS_SetupReqIndex & 0xFF ) )
+                                {
+                                    case ( DEF_UEP_IN | DEF_UEP1 ):
+                                        if( ( (USBOTG_FS->UEP1_TX_CTRL) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
+                                        {
+                                            USBFS_EP0_Buf[ 0 ] = 0x01;
+                                        }
+                                        break;
+
+                                    case ( DEF_UEP_OUT | DEF_UEP2 ):
+                                        if( ( (USBOTG_FS->UEP2_RX_CTRL) & USBFS_UEP_R_RES_MASK ) == USBFS_UEP_R_RES_STALL )
+                                        {
+                                            USBFS_EP0_Buf[ 0 ] = 0x01;
+                                        }
+                                        break;
+
+                                    case ( DEF_UEP_IN | DEF_UEP3 ):
+                                        if( ( (USBOTG_FS->UEP3_TX_CTRL) & USBFS_UEP_T_RES_MASK ) == USBFS_UEP_T_RES_STALL )
+                                        {
+                                            USBFS_EP0_Buf[ 0 ] = 0x01;
+                                        }
+                                        break;
+
+                                    default:
+                                        errflag = 0xFF;
+                                        break;
+                                }
+                            }
+                            else
+                            {
+                                errflag = 0xFF;
+                            }
+
+                            if( USBFS_SetupReqLen > 2 )
+                            {
+                                USBFS_SetupReqLen = 2;
+                            }
+
+                            break;
+
+                        default:
+                            errflag = 0xFF;
+                            break;
+                    }
+                }
+                /* errflag = 0xFF means a request not support or some errors occurred, else correct */
+                if( errflag == 0xff)
+                {
+                    /* if one request not support, return stall */
+                    USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_STALL;
+                    USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_STALL;
+                }
+                else
+                {
+                    /* end-point 0 data Tx/Rx */
+                    if( USBFS_SetupReqType & DEF_UEP_IN )
+                    {
+                        /* tx */
+                        len = (USBFS_SetupReqLen>DEF_USBD_UEP0_SIZE) ? DEF_USBD_UEP0_SIZE : USBFS_SetupReqLen;
+                        USBFS_SetupReqLen -= len;
+                        USBOTG_FS->UEP0_TX_LEN  = len;
+                        USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK;
+                    }
+                    else
+                    {
+                        /* rx */
+                        if( USBFS_SetupReqLen == 0 )
+                        {
+                            USBOTG_FS->UEP0_TX_LEN  = 0;
+                            USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_TOG|USBFS_UEP_T_RES_ACK;
+                        }
+                        else
+                        {
+                            USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_TOG|USBFS_UEP_R_RES_ACK;
+                        }
+                    }
+                }
+                break;
+
+            /* Sof pack processing */
+            case USBFS_UIS_TOKEN_SOF:
+                break;
+
+            default :
+                break;
+        }
+        USBOTG_FS->INT_FG = USBFS_UIF_TRANSFER;
+    }
+    else if( intflag & USBFS_UIF_BUS_RST )
+    {
+        /* usb reset interrupt processing */
+        USBOTG_FS->DEV_ADDR = 0;
+        USBFS_Device_Endp_Init( );
+        USBOTG_FS->INT_FG = USBFS_UIF_BUS_RST;
+    }
+    else if( intflag & USBFS_UIF_SUSPEND )
+    {
+        /* usb suspend interrupt processing */
+        if ( USBOTG_FS->MIS_ST & USBFS_UMS_SUSPEND )
+        {
+            USBFS_DevSleepStatus |= 0x02;
+            if( USBFS_DevSleepStatus == 0x03 )
+            {
+                /* Handling usb sleep here */
+            }
+        }
+        else
+        {
+            USBFS_DevSleepStatus &= ~0x02;
+        }
+        USBOTG_FS->INT_FG = USBFS_UIF_SUSPEND;
+    }
+    else
+    {
+        /* other interrupts */
+        USBOTG_FS->INT_FG = intflag;
+    }
+}
+
+/*********************************************************************
+ * @fn      USBFS_Send_Resume
+ *
+ * @brief   USBFS device sends wake-up signal to host
+ *
+ * @return  none
+ */
+void USBFS_Send_Resume(void)
+{
+
+}
+
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/hci_test.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/hci_test.c
index 7cbe8b4..0b3f545 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/hci_test.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/hci_test.c
@@ -12,6 +12,7 @@
 
 #include "hci_test.h"
 #include "config.h"
+#include "uart.h"
 
 static uint16_t _opcode;
 static uint8_t hci_pool[100];
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/buf.h b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/buf.h
index a0b0da9..9c60388 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/buf.h
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/buf.h
@@ -17,6 +17,8 @@
 #include <stddef.h>
 #include <string.h>
 
+
+
 struct simple_buf {
 	/** Pointer to the start of data in the buffer. */
 	uint8_t *data;
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usb.h b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/ch32v20x_usb.h
similarity index 100%
rename from EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usb.h
rename to EVT/EXAM/BLE/Direct_Test_Mode/APP/include/ch32v20x_usb.h
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/ch32v20x_usbfs_device.h b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/ch32v20x_usbfs_device.h
new file mode 100644
index 0000000..1a6ea49
--- /dev/null
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/ch32v20x_usbfs_device.h
@@ -0,0 +1,106 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v20x_usbfs_device.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2022/08/20
+* Description        : This file contains all the functions prototypes for the
+*                      USBOTG firmware library.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#ifndef __CH32V20X_USBFS_DEVICE_H_
+#define __CH32V20X_USBFS_DEVICE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "debug.h"
+#include "string.h"
+#include "usb_desc.h"
+#include "ch32v20x_usb.h"
+#include <UART.h>
+
+/******************************************************************************/
+/* Global Define */
+#ifndef __PACKED
+  #define __PACKED   __attribute__((packed))
+#endif
+
+/* end-point number */
+#define DEF_UEP_IN                    0x80
+#define DEF_UEP_OUT                   0x00
+#define DEF_UEP0                      0x00
+#define DEF_UEP1                      0x01
+#define DEF_UEP2                      0x02
+#define DEF_UEP3                      0x03
+#define DEF_UEP4                      0x04
+#define DEF_UEP5                      0x05
+#define DEF_UEP6                      0x06
+#define DEF_UEP7                      0x07
+#define DEF_UEP_NUM                   8
+
+#define USBFSD_UEP_MOD_BASE           0x5000000C
+#define USBFSD_UEP_DMA_BASE           0x50000010
+#define USBFSD_UEP_LEN_BASE           0x50000030
+#define USBFSD_UEP_CTL_BASE           0x50000032
+#define USBFSD_UEP_RX_EN              0x08
+#define USBFSD_UEP_TX_EN              0x04
+#define USBFSD_UEP_BUF_MOD            0x01
+#define DEF_UEP_DMA_LOAD              0 /* Direct the DMA address to the data to be processed */
+#define DEF_UEP_CPY_LOAD              1 /* Use memcpy to move data to a buffer */
+#define USBFSD_UEP_MOD(n)             (*((volatile uint8_t *)(USBFSD_UEP_MOD_BASE+n)))
+#define USBFSD_UEP_CTRL(n)            (*((volatile uint8_t *)(USBFSD_UEP_CTL_BASE+n*0x04)))
+#define USBFSD_UEP_DMA(n)             (*((volatile uint32_t *)(USBFSD_UEP_DMA_BASE+n*0x04)))
+#define USBFSD_UEP_BUF(n)             ((uint8_t *)(*((volatile uint32_t *)(USBFSD_UEP_DMA_BASE+n*0x04)))+0x20000000)
+#define USBFSD_UEP_TLEN(n)            (*((volatile uint16_t *)(USBFSD_UEP_LEN_BASE+n*0x04)))
+
+/* Setup Request Packets */
+#define pUSBFS_SetupReqPak                 ((PUSB_SETUP_REQ)USBFS_EP0_Buf)
+
+/*******************************************************************************/
+/* Variable Definition */
+/* Global */
+extern const    uint8_t  *pUSBFS_Descr;
+
+/* Setup Request */
+extern volatile uint8_t  USBFS_SetupReqCode;
+extern volatile uint8_t  USBFS_SetupReqType;
+extern volatile uint16_t USBFS_SetupReqValue;
+extern volatile uint16_t USBFS_SetupReqIndex;
+extern volatile uint16_t USBFS_SetupReqLen;
+
+/* USB Device Status */
+extern volatile uint8_t  USBFS_DevConfig;
+extern volatile uint8_t  USBFS_DevAddr;
+extern volatile uint8_t  USBFS_DevSleepStatus;
+extern volatile uint8_t  USBFS_DevEnumStatus;
+
+/* Endpoint Buffer */
+extern __attribute__ ((aligned(4))) uint8_t USBFS_EP0_Buf[ ];
+extern __attribute__ ((aligned(4))) uint8_t USBFS_EP1_Buf[ ];
+extern __attribute__ ((aligned(4))) uint8_t USBFS_EP2_Buf[ ];
+extern __attribute__ ((aligned(4))) uint8_t USBFS_EP3_Buf[ ];
+/* USB IN Endpoint Busy Flag */
+extern volatile uint8_t  USBFS_Endp_Busy[ ];
+
+/******************************************************************************/
+/* external functions */
+extern void USBFS_Device_Init( FunctionalState sta );
+extern void USBFS_Device_Endp_Init(void);
+extern void USBFS_RCC_Init(void);
+extern void USBFS_Send_Resume(void);
+extern void USBFS_Sleep_Wakeup_Operate(void);
+extern uint8_t USBSendData(uint8_t *buf, uint16_t len);
+extern uint8_t USBFS_Endp_DataUp(uint8_t endp, uint8_t *pbuf, uint16_t len, uint8_t mod);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USER_CH32V20X_USB_DEVICE_H_ */
+
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/uart.h b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/uart.h
index 44c2b8c..819e0d2 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/uart.h
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/uart.h
@@ -15,20 +15,63 @@
 
 #include "config.h"
 #include "buf.h"
+#include "atomic.h"
 
-#define UART_PROCESS_EVT                1
+#define   USB_UartEnable                1
+#define DEF_UARTx_RX_BUF_LEN       ( 4 * 512 )                                  /* Serial x receive buffer size */
+#define DEF_UARTx_TX_BUF_LEN       ( 2 * 512 )                                  /* Serial x transmit buffer size */
 
 /*process events*/
 #define UART_RECEIVE_POLL_EVT           (1<<0)
+#define USB_RECEIVE_POLL_EVT            (1<<1)
+
+#define   UART_PROCESS_EVT              1
+#define   USB_PROCESS_EVT               (1<<1)
+
+enum uart_status
+{
+    UART_STATUS_IDLE,
+    UART_STATUS_RCVING,
+    UART_STATUS_RCV_END,
+    UART_STATUS_SENDING,
+
+    UART_STATUS_NUM,
+};
+
+enum usb_status
+{
+    USB_STATUS_IDLE,
+    USB_STATUS_RCVING,
+    USB_STATUS_RCV_END,
+    USB_STATUS_SENDING,
+
+    USB_STATUS_NUM,
+};
 
 struct uart_process_msg {
     tmos_event_hdr_t hdr;
     uint8_t *data;
 };
 
+struct usb_process_msg {
+    tmos_event_hdr_t hdr;
+    uint8_t *data;
+};
 
+extern struct simple_buf *usb_buf;
+extern atomic_t uart_flag;
+extern atomic_t usb_flag;
+extern uint8_t  UART2_Tx_Buf[ DEF_UARTx_TX_BUF_LEN ];
+extern uint8_t  UART2_Rx_Buf[ DEF_UARTx_RX_BUF_LEN ];
+
+
+int usb_send(struct simple_buf *buf);
 int uart_send(struct simple_buf *buf);
 int uart_start_receiving(void);
+int usb_start_receiving(void);
 void uart_task_init(void);
+void USB_Task_Init(void);
+
+
 
 #endif /* BLE_DIRECTTEST_APP_INCLUDE_UART_H */
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/usb_desc.h b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/usb_desc.h
new file mode 100644
index 0000000..c9d7360
--- /dev/null
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/include/usb_desc.h
@@ -0,0 +1,67 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_desc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2022/08/20
+ * Description        : header file of usb_desc.c
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#ifndef USER_USB_DESC_H_
+#define USER_USB_DESC_H_
+
+#include "debug.h"
+
+/******************************************************************************/
+/* global define */
+/* file version */
+#define DEF_FILE_VERSION             0x01
+/* usb device info define  */
+#define DEF_USB_VID                  0x1A86
+#define DEF_USB_PID                  0xFE0C
+/* USB device descriptor, device serial number(bcdDevice) */
+#define DEF_IC_PRG_VER               DEF_FILE_VERSION
+
+/******************************************************************************/
+/* usb device endpoint size define */
+#define DEF_USBD_UEP0_SIZE           64     /* usb hs/fs device end-point 0 size */
+/* FS */
+#define DEF_USBD_FS_PACK_SIZE        64     /* usb fs device max bluk/int pack size */
+#define DEF_USBD_FS_ISO_PACK_SIZE    1023   /* usb fs device max iso pack size */
+/* LS */
+#define DEF_USBD_LS_UEP0_SIZE        8      /* usb ls device end-point 0 size */
+#define DEF_USBD_LS_PACK_SIZE        64     /* usb ls device max int pack size */
+
+/* Pack size */
+#define DEF_USBD_ENDP1_SIZE          DEF_USBD_FS_PACK_SIZE
+#define DEF_USBD_ENDP2_SIZE          DEF_USBD_FS_PACK_SIZE
+#define DEF_USBD_ENDP3_SIZE          DEF_USBD_FS_PACK_SIZE
+#define DEF_USBD_ENDP4_SIZE          DEF_USBD_FS_PACK_SIZE
+#define DEF_USBD_ENDP5_SIZE          DEF_USBD_FS_PACK_SIZE
+#define DEF_USBD_ENDP6_SIZE          DEF_USBD_FS_PACK_SIZE
+#define DEF_USBD_ENDP7_SIZE          DEF_USBD_FS_PACK_SIZE
+
+/******************************************************************************/
+/* usb device Descriptor length, length of usb descriptors, if one descriptor not
+ * exists , set the length to 0  */
+#define DEF_USBD_DEVICE_DESC_LEN     ((uint8_t)MyDevDescr[0])
+#define DEF_USBD_CONFIG_DESC_LEN     ((uint16_t)MyCfgDescr[2] + (uint16_t)(MyCfgDescr[3] << 8))
+#define DEF_USBD_REPORT_DESC_LEN     0
+#define DEF_USBD_LANG_DESC_LEN       ((uint16_t)MyLangDescr[0])
+#define DEF_USBD_MANU_DESC_LEN       ((uint16_t)MyManuInfo[0])
+#define DEF_USBD_PROD_DESC_LEN       ((uint16_t)MyProdInfo[0])
+#define DEF_USBD_SN_DESC_LEN         ((uint16_t)MySerNumInfo[0])
+
+/******************************************************************************/
+/* external variables */
+extern const uint8_t MyDevDescr[ ];
+extern const uint8_t MyCfgDescr[ ];
+extern const uint8_t MyLangDescr[ ];
+extern const uint8_t MyManuInfo[ ];
+extern const uint8_t MyProdInfo[ ];
+extern const uint8_t MySerNumInfo[ ];
+
+#endif /* USER_USB_DESC_H_ */
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/main.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/main.c
index 025a520..ac49f00 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/main.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/main.c
@@ -12,10 +12,12 @@
 
 /******************************************************************************/
 /* Header file contains */
+#include "debug.h"
 #include "CONFIG.h"
 #include "HAL.h"
 #include "test_dtm.h"
 #include "uart.h"
+#include "ch32v20x_usbfs_device.h"
 
 /*********************************************************************
  * GLOBAL TYPEDEFS
@@ -54,13 +56,19 @@ int main(void)
 {
     SystemCoreClockUpdate();
     Delay_Init();
-#ifdef DEBUG
+#ifdef DEBUG                         // Ĭ��Uart1��ӡ Uart2 Test
     USART_Printf_Init( 115200 );
 #endif
     PRINT("%s\n", VER_LIB);
     WCHBLE_Init();
     HAL_Init();
     uart_task_init();
+#if USB_UartEnable == 1              // Ĭ��ʹ��USBģ�⴮��
+    /* Usb Init */
+    USBFS_RCC_Init();
+    USBFS_Device_Init( ENABLE );
+    USB_Task_Init();
+#endif
     test_dtm_init();
     GAPRole_BroadcasterInit();
     Main_Circulation();
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/test_dtm.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/test_dtm.c
index a17c027..b0a3a01 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/test_dtm.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/test_dtm.c
@@ -10,9 +10,9 @@
  * microcontroller manufactured by Nanjing Qinheng Microelectronics.
  *******************************************************************************/
 
+#include "uart.h"
 #include "config.h"
 #include "test_dtm.h"
-#include "uart.h"
 
 tmosTaskID test_taskid = INVALID_TASK_ID;
 
@@ -37,10 +37,23 @@ static void test_dtm_process_msg(tmos_event_hdr_t *pMsg) {
         if(evt)
             uart_send(evt);
 
-        uart_start_receiving();
+            uart_start_receiving();
     }
         break;
 
+    case USB_PROCESS_EVT:{
+        struct simple_buf *evt = NULL;
+        struct usb_process_msg *msg = \
+            (struct usb_process_msg *)pMsg;
+
+        evt = hci_cmd_handle((struct simple_buf*)msg->data);
+
+        if(evt)
+            usb_send(evt);
+
+            usb_start_receiving();
+    }
+        break;
     default:
         break;
     }
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/uart.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/uart.c
index dfbe471..405890e 100644
--- a/EVT/EXAM/BLE/Direct_Test_Mode/APP/uart.c
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/uart.c
@@ -10,74 +10,56 @@
  * microcontroller manufactured by Nanjing Qinheng Microelectronics.
  *******************************************************************************/
 
-#include "config.h"
 #include "uart.h"
+#include "config.h"
 #include "atomic.h"
 #include "test_dtm.h"
+#include "ch32v20x_usbfs_device.h"
 
 static tmosTaskID uart_taskid;
+static tmosTaskID usb_taskid;
+
+__attribute__ ((aligned(4))) uint8_t  UART2_Tx_Buf[ DEF_UARTx_TX_BUF_LEN ];  /* Serial port 2 transmit data buffer */
+__attribute__ ((aligned(4))) uint8_t  UART2_Rx_Buf[ DEF_UARTx_RX_BUF_LEN ];  /* Serial port 2 receive data buffer */
 
 static uint8_t rx_buf[100];
 static struct simple_buf *uart_buf = NULL;
+struct simple_buf *usb_buf = NULL;
 static struct simple_buf uart_buffer;
-
-enum uart_status {
-    UART_STATUS_IDLE,
-    UART_STATUS_RCVING,
-    UART_STATUS_RCV_END,
-    UART_STATUS_SENDING,
-
-    UART_STATUS_NUM,
-};
+static uint8_t rx_ubuf[100];
+static struct simple_buf usb_buffer;
 
 atomic_t uart_flag;
+atomic_t usb_flag;
 
+/*********************************************************************
+ * @fn      uart_buffer_create
+ *
+ * @brief   Create a file called uart_buffer simple buffer of the buffer
+ *          and assign its address to the variable pointed to by the buffer pointer.
+ *
+ * @param   buf    -   a parameter buf pointing to a pointer.
+ *
+ * @return  none
+ */
 void uart_buffer_create(struct simple_buf **buf)
 {
     *buf = simple_buf_create(&uart_buffer, rx_buf, sizeof(rx_buf));
 }
 
-int uart_start_receiving(void)
+/*********************************************************************
+ * @fn      usb_buffer_create
+ *
+ * @brief   Create a file called usb_buffer simple buffer of the buffer
+ *          and assign its address to the variable pointed to by the buffer pointer.
+ *
+ * @param   buf    -   a parameter buf pointing to a pointer.
+ *
+ * @return  none
+ */
+void usb_buffer_create(struct simple_buf **buf)
 {
-    PRINT("uart2 reeciving\n");
-    atomic_set(&uart_flag, UART_STATUS_RCVING);
-    uart_buffer_create(&uart_buf);
-    USART_Cmd(USART2, ENABLE);
-
-    return 0;
-}
-
-void uart2_send_data(uint8_t *data, uint16_t len)
-{
-    for(int i = 0; i < len; i++) {
-        USART_SendData(USART2, data[i]);
-        while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET) {
-            /* waiting for sending finish */
-            ;
-        }
-    }
-}
-
-int uart_send(struct simple_buf *buf)
-{
-    atomic_set(&uart_flag, UART_STATUS_SENDING);
-
-    uint8_t *send_data;
-    uint16_t send_len;
-
-    send_len = buf->len;
-    send_data = simple_buf_pull(buf, buf->len);
-    uart2_send_data(send_data, send_len);
-    atomic_set(&uart_flag, UART_STATUS_IDLE);
-
-    PRINT("uart2 send %d bytes [", send_len);
-    for(int i = 0; i < send_len; i++){
-        if(i) PRINT(" ");
-        PRINT("%#x", send_data[i]);
-    }
-    PRINT("]\n");
-
-    return 0;
+    *buf = simple_buf_create(&usb_buffer, rx_ubuf, sizeof(rx_ubuf));
 }
 
 /*********************************************************************
@@ -108,7 +90,7 @@ tmosEvents uart_processevent(tmosTaskID task_id, tmosEvents events)
 
     if(events & UART_RECEIVE_POLL_EVT) {
         if(atomic_get(&uart_flag) == UART_STATUS_RCV_END) {
-            PRINT("uart2 recevied %d bytes [", uart_buf->len);
+            PRINT("uart recevied %d bytes [", uart_buf->len);
             for(int i = 0; i < uart_buf->len; i++) {
                 if(i) PRINT(" ");
                 PRINT("%#x", uart_buf->data[i]);
@@ -130,11 +112,119 @@ tmosEvents uart_processevent(tmosTaskID task_id, tmosEvents events)
 
         return (events ^ UART_RECEIVE_POLL_EVT);
     }
+    if(events & USB_RECEIVE_POLL_EVT)
+    {
+        if(atomic_get(&usb_flag) == USB_STATUS_RCV_END)
+        {
+            PRINT("usb recevied %d bytes [", usb_buf->len);
+            for(int i = 0; i < usb_buf->len; i++)
+            {
+                if(i)
+                   PRINT(" ");
+                   PRINT("%#x", usb_buf->data[i]);
+            }
+            PRINT("]\n");
+
+            struct usb_process_msg *usb_msg;
+
+            usb_msg = (struct usb_process_msg *)      \
+                tmos_msg_allocate(sizeof(struct usb_process_msg));
+
+            if(usb_msg)
+            {
+                usb_msg->hdr.event = USB_PROCESS_EVT;
+                usb_msg->hdr.status = true;
+                usb_msg->data = (uint8_t *)usb_buf;
+                tmos_msg_send(test_taskid, (uint8_t *)usb_msg );
+            }
+        }
+
+        return (events ^ USB_RECEIVE_POLL_EVT);
+    }
+    return 0;
+}
+
+#if(DEBUG == DEBUG_UART1)
+/*********************************************************************
+ * @fn      uart_start_receiving
+ *
+ * @brief   Serial port starts receiving.
+ *
+ * @param   none
+ *
+ * @return  none
+ */
+int uart_start_receiving(void)
+{
+    PRINT("uart2 receiving\n");
+    atomic_set(&uart_flag, UART_STATUS_RCVING);
+    uart_buffer_create(&uart_buf);
+    USART_Cmd(USART2, ENABLE);
 
     return 0;
 }
 
+/*********************************************************************
+ * @fn      uart2_send_data
+ *
+ * @brief   Serial port 2 sends data.
+ *
+ * @param   data  -  Data to be sent.
+ *          len   -  The length of data.
+ *
+ * @return  none
+ */
+void uart2_send_data(uint8_t *data, uint16_t len)
+{
+    for(int i = 0; i < len; i++) {
+        USART_SendData(USART2, data[i]);
+        while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET) {
+            /* waiting for sending finish */
+            ;
+        }
+    }
+}
 
+/*********************************************************************
+ * @fn      uart_send
+ *
+ * @brief   Serial port starts Sending.
+ *
+ * @param   buf    -   defined simple_buf structural object.
+ *
+ * @return  none
+ */
+int uart_send(struct simple_buf *buf)
+{
+    atomic_set(&uart_flag, UART_STATUS_SENDING);
+
+    uint8_t *send_data;
+    uint16_t send_len;
+
+    send_len = buf->len;
+    send_data = simple_buf_pull(buf, buf->len);
+    uart2_send_data(send_data, send_len);
+    atomic_set(&uart_flag, UART_STATUS_IDLE);
+
+    PRINT("uart2 send %d bytes [", send_len);
+    for(int i = 0; i < send_len; i++){
+        if(i) PRINT(" ");
+        PRINT("%#x", send_data[i]);
+    }
+    PRINT("]\n");
+
+    return 0;
+}
+
+/*********************************************************************
+ * @fn      uart_task_init
+ *
+ * @brief   Serial port initialization and task initialization.
+ *
+ * @param   none
+ *
+ * @return  none
+ */
 void uart_task_init(void)
 {
     uart_taskid = TMOS_ProcessEventRegister(uart_processevent);
@@ -172,12 +262,210 @@ void uart_task_init(void)
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
     NVIC_Init(&NVIC_InitStructure);
 
-    tmos_start_reload_task(uart_taskid, UART_RECEIVE_POLL_EVT, 
+    tmos_start_reload_task(uart_taskid, UART_RECEIVE_POLL_EVT,
         MS1_TO_SYSTEM_TIME(100));
 
     atomic_set(&uart_flag, UART_STATUS_IDLE);
     uart_start_receiving();
 }
+#endif
+
+#if(DEBUG == DEBUG_UART2)
+/*********************************************************************
+ * @fn      uart_start_receiving
+ *
+ * @brief   Serial port starts receiving.
+ *
+ * @param   none
+ *
+ * @return  none
+ */
+int uart_start_receiving(void)
+{
+    PRINT("uart1 receiving\n");
+    atomic_set(&uart_flag, UART_STATUS_RCVING);
+    uart_buffer_create(&uart_buf);
+    USART_Cmd(USART1, ENABLE);
+
+    return 0;
+}
+
+/*********************************************************************
+ * @fn      uart1_send_data
+ *
+ * @brief   Serial port 1 sends data.
+ *
+ * @param   data  -  Data to be sent.
+ *          len   -  The length of data.
+ *
+ * @return  none
+ */
+void uart1_send_data(uint8_t *data, uint16_t len)
+{
+    for(int i = 0; i < len; i++) {
+        USART_SendData(USART1, data[i]);
+        while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET) {
+            /* waiting for sending finish */
+            ;
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      uart_send
+ *
+ * @brief   Serial port starts Sending.
+ *
+ * @param   buf    -   defined simple_buf structural object.
+ *
+ * @return  none
+ */
+int uart_send(struct simple_buf *buf)
+{
+    atomic_set(&uart_flag, UART_STATUS_SENDING);
+
+    uint8_t *send_data;
+    uint16_t send_len;
+
+    send_len = buf->len;
+    send_data = simple_buf_pull(buf, buf->len);
+    uart1_send_data(send_data, send_len);
+    atomic_set(&uart_flag, UART_STATUS_IDLE);
+
+    PRINT("uart1 send %d bytes [", send_len);
+    for(int i = 0; i < send_len; i++){
+        if(i) PRINT(" ");
+        PRINT("%#x", send_data[i]);
+    }
+    PRINT("]\n");
+
+    return 0;
+}
+
+/*********************************************************************
+ * @fn      uart_task_init
+ *
+ * @brief   Serial port initialization and task initialization.
+ *
+ * @param   none
+ *
+ * @return  none
+ */
+void uart_task_init(void)
+{
+    uart_taskid = TMOS_ProcessEventRegister(uart_processevent);
+
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+    NVIC_InitTypeDef  NVIC_InitStructure = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    /* USART1 TX-->A.9   RX-->A.10 */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    USART_InitStructure.USART_BaudRate = 115200;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+
+    USART_Init(USART1, &USART_InitStructure);
+    USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
+    USART_ITConfig(USART1, USART_IT_IDLE, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    tmos_start_reload_task(uart_taskid, UART_RECEIVE_POLL_EVT,
+        MS1_TO_SYSTEM_TIME(100));
+
+    atomic_set(&uart_flag, UART_STATUS_IDLE);
+    uart_start_receiving();
+}
+#endif
+
+/*********************************************************************
+ * @fn      USB_Task_Init
+ *
+ * @brief   USB initialization and task initialization.
+ *
+ * @param   none
+ *
+ * @return  none
+ */
+void USB_Task_Init(void)
+{
+    usb_taskid = TMOS_ProcessEventRegister(uart_processevent);
+
+    tmos_start_reload_task(usb_taskid, USB_RECEIVE_POLL_EVT,
+        MS1_TO_SYSTEM_TIME(100));
+
+    atomic_set(&usb_flag, USB_STATUS_IDLE);
+    usb_start_receiving();
+}
+
+/*********************************************************************
+ * @fn      usb_start_receiving
+ *
+ * @brief   Usb starts receiving.
+ *
+ * @param   none
+ *
+ * @return  none
+ */
+int usb_start_receiving(void)
+{
+    PRINT("usb receiving\n");
+    atomic_set(&usb_flag, USB_STATUS_RCVING);
+    usb_buffer_create(&usb_buf);
+
+    return 0;
+}
+
+/*********************************************************************
+ * @fn      usb_send
+ *
+ * @brief   Usb starts Sending.
+ *
+ * @param   buf    -   defined simple_buf structural object.
+ *
+ * @return  none
+ */
+int usb_send(struct simple_buf *buf)
+{
+    atomic_set(&usb_flag, USB_STATUS_SENDING);
+
+    uint8_t *send_data;
+    uint16_t send_len;
+
+    send_len = buf->len;
+    send_data = simple_buf_pull(buf, buf->len);
+
+    USBSendData(send_data, send_len);          //�޸�ΪUSBSend
+    atomic_set(&usb_flag, UART_STATUS_IDLE);
+
+    PRINT("usb send %d bytes [", send_len);
+    for(int i = 0; i < send_len; i++)
+    {
+        if(i) PRINT(" ");
+        PRINT("%#x", send_data[i]);
+    }
+    PRINT("]\n");
+
+    return 0;
+}
 
 /*********************************************************************
  * @fn      USART2_IRQHandler
@@ -203,3 +491,26 @@ void USART2_IRQHandler(void)
     }
 }
 
+/*********************************************************************
+ * @fn      USART1_IRQHandler
+ *
+ * @brief   This function handles USART1 global interrupt request.
+ *
+ * @return  none
+ */
+__attribute__((interrupt("WCH-Interrupt-fast")))
+void USART1_IRQHandler(void)
+{
+    if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)
+    {
+        simple_buf_add_u8(uart_buf, USART_ReceiveData(USART1));
+    }
+
+    if(USART_GetITStatus(USART1, USART_IT_IDLE) != RESET)
+    {
+        atomic_set(&uart_flag, UART_STATUS_RCV_END);
+
+        /* clear IDLE flag */
+        (void)USART_ReceiveData(USART1);
+    }
+}
diff --git a/EVT/EXAM/BLE/Direct_Test_Mode/APP/usb_desc.c b/EVT/EXAM/BLE/Direct_Test_Mode/APP/usb_desc.c
new file mode 100644
index 0000000..5d940cb
--- /dev/null
+++ b/EVT/EXAM/BLE/Direct_Test_Mode/APP/usb_desc.c
@@ -0,0 +1,90 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : usb_desc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2022/08/20
+ * Description        : usb device descriptor,configuration descriptor,
+ *                      string descriptors and other descriptors.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#include "usb_desc.h"
+
+/* Device Descriptor */
+const uint8_t  MyDevDescr[] =
+{
+    0x12,       // bLength
+    0x01,       // bDescriptorType (Device)
+    0x10, 0x01, // bcdUSB 1.10
+    0x02,       // bDeviceClass
+    0x00,       // bDeviceSubClass
+    0x00,       // bDeviceProtocol
+    DEF_USBD_UEP0_SIZE,   // bMaxPacketSize0 64
+    (uint8_t)DEF_USB_VID, (uint8_t)(DEF_USB_VID >> 8),  // idVendor 0x1A86
+    (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8),  // idProduct 0x5537
+    DEF_IC_PRG_VER, 0x00, // bcdDevice 0.01
+    0x01,       // iManufacturer (String Index)
+    0x02,       // iProduct (String Index)
+    0x00,       // iSerialNumber (String Index)
+    0x01,       // bNumConfigurations 1
+};
+
+/* Configuration Descriptor */
+const uint8_t  MyCfgDescr[] =
+{
+    /* Configure descriptor */
+    0x09, 0x02, 0x43, 0x00, 0x02, 0x01, 0x00, 0x80, 0x32,
+
+    /* Interface 0 (CDC) descriptor */
+    0x09, 0x04, 0x00, 0x00, 0x01, 0x02, 0x02, 0x01,  0x00,
+
+    /* Functional Descriptors */
+    0x05, 0x24, 0x00, 0x10, 0x01,
+
+    /* Length/management descriptor (data class interface 1) */
+    0x05, 0x24, 0x01, 0x00, 0x01,
+    0x04, 0x24, 0x02, 0x02,
+    0x05, 0x24, 0x06, 0x00, 0x01,
+
+    /* Interrupt upload endpoint descriptor */
+    0x07, 0x05, 0x81, 0x03, (uint8_t)DEF_USBD_ENDP1_SIZE, (uint8_t)( DEF_USBD_ENDP1_SIZE >> 8 ), 0x01,
+
+    /* Interface 1 (data interface) descriptor */
+    0x09, 0x04, 0x01, 0x00, 0x02, 0x0A, 0x00, 0x00, 0x00,
+
+    /* Endpoint descriptor */
+    0x07, 0x05, 0x02, 0x02, (uint8_t)DEF_USBD_ENDP2_SIZE, (uint8_t)( DEF_USBD_ENDP2_SIZE >> 8 ), 0x00,
+
+    /* Endpoint descriptor */
+    0x07, 0x05, 0x83, 0x02, (uint8_t)DEF_USBD_ENDP3_SIZE, (uint8_t)( DEF_USBD_ENDP3_SIZE >> 8 ), 0x00,
+};
+
+/* Language Descriptor */
+const uint8_t  MyLangDescr[] =
+{
+    0x04, 0x03, 0x09, 0x04
+};
+
+/* Manufacturer Descriptor */
+const uint8_t  MyManuInfo[] =
+{
+    0x0E, 0x03, 'w', 0, 'c', 0, 'h', 0, '.', 0, 'c', 0, 'n', 0
+};
+
+/* Product Information */
+const uint8_t  MyProdInfo[] =
+{
+    0x16, 0x03, 'U', 0x00, 'S', 0x00, 'B', 0x00, ' ', 0x00, 'S', 0x00, 'e', 0x00,
+                    'r', 0x00, 'i', 0x00, 'a', 0x00, 'l', 0x00
+};
+
+/* Serial Number Information */
+const uint8_t  MySerNumInfo[] =
+{
+    0x16, 0x03, '0', 0, '1', 0, '2', 0, '3', 0, '4', 0, '5', 0
+              , '6', 0, '7', 0, '8', 0, '9', 0
+};
+
diff --git a/EVT/EXAM/BLE/HAL/RTC.c b/EVT/EXAM/BLE/HAL/RTC.c
index d069251..b251f04 100644
--- a/EVT/EXAM/BLE/HAL/RTC.c
+++ b/EVT/EXAM/BLE/HAL/RTC.c
@@ -56,7 +56,7 @@ void HAL_TimeInit(void)
 {
     uint16_t temp=0;
     uint8_t state=0;
-    bleClockConfig_t  conf;
+    bleClockConfig_t  conf={0};
 
     RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR|RCC_APB1Periph_BKP, ENABLE);
     PWR_BackupAccessCmd(ENABLE);
diff --git a/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Consumer/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Keyboard/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Mouse/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HID_Touch/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c b/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/HeartRate/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/LIB/libwchble.a b/EVT/EXAM/BLE/LIB/libwchble.a
index 00ce15574613ba7b0f0f35768ce358e1dba40990..4947cf0a720b94cae43414a51730f9cfbf3c145d 100644
GIT binary patch
delta 43009
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diff --git a/EVT/EXAM/BLE/LIB/wchble_rom.hex b/EVT/EXAM/BLE/LIB/wchble_rom.hex
index cee2a81..13202d1 100644
--- a/EVT/EXAM/BLE/LIB/wchble_rom.hex
+++ b/EVT/EXAM/BLE/LIB/wchble_rom.hex
@@ -1,75 +1,75 @@
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diff --git a/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c b/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/LWNS/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a b/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESH.a
index 4fb5078862492374e3615caf22fca27681cd9340..50817e9a5c5011743d76df8380a75455c7760c1a 100644
GIT binary patch
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diff --git a/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a b/EVT/EXAM/BLE/MESH/MESH_LIB/LIBMESHROM.a
index ab4333c1df1110b51faeceaea64eeee23aff0cf3..6c003ef4cd92ff04789319f0b7722aa345b7550a 100644
GIT binary patch
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diff --git a/EVT/EXAM/BLE/MESH/MESH_LIB/wchble_rom_mesh.hex b/EVT/EXAM/BLE/MESH/MESH_LIB/wchble_rom_mesh.hex
index fbc0ffc..843135b 100644
--- a/EVT/EXAM/BLE/MESH/MESH_LIB/wchble_rom_mesh.hex
+++ b/EVT/EXAM/BLE/MESH/MESH_LIB/wchble_rom_mesh.hex
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diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_lightness/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_add_windspeed/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_multi_element/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_ali_light_with_peripheral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/.cproject b/EVT/EXAM/BLE/MESH/adv_proxy/.cproject
index 252e441..62e0af6 100644
--- a/EVT/EXAM/BLE/MESH/adv_proxy/.cproject
+++ b/EVT/EXAM/BLE/MESH/adv_proxy/.cproject
@@ -159,5 +159,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope"/>
+	
 </cproject>
diff --git a/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_proxy/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_friend/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_low_power/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_IAP/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/adv_vendor_self_provision_with_peripheral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/self_provisioner_vendor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/self_provisioner_vendor/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/self_provisioner_vendor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/self_provisioner_vendor/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MESH/self_provisioner_vendor_with_peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MESH/self_provisioner_vendor_with_peripheral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MESH/self_provisioner_vendor_with_peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MESH/self_provisioner_vendor_with_peripheral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MultiCentPeri/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/MultiCentral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Observer/APP/observer.c b/EVT/EXAM/BLE/Observer/APP/observer.c
index d2da7df..0ae24f6 100644
--- a/EVT/EXAM/BLE/Observer/APP/observer.c
+++ b/EVT/EXAM/BLE/Observer/APP/observer.c
@@ -27,7 +27,7 @@
  */
 
 // Maximum number of scan responses
-#define DEFAULT_MAX_SCAN_RES             100
+#define DEFAULT_MAX_SCAN_RES             50
 
 // Scan duration in (625us)
 #define DEFAULT_SCAN_DURATION            4800
diff --git a/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Observer/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/OnlyUpdateApp_IAP/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/OnlyUpdateApp_Peripheral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/PAwR_ADV/.cproject b/EVT/EXAM/BLE/PAwR_ADV/.cproject
index 626c80b..2807b24 100644
--- a/EVT/EXAM/BLE/PAwR_ADV/.cproject
+++ b/EVT/EXAM/BLE/PAwR_ADV/.cproject
@@ -157,5 +157,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope"/>
+	
 </cproject>
diff --git a/EVT/EXAM/BLE/PAwR_ADV/APP/adv_periodic.c b/EVT/EXAM/BLE/PAwR_ADV/APP/adv_periodic.c
index 2c21ea3..fa15a67 100644
--- a/EVT/EXAM/BLE/PAwR_ADV/APP/adv_periodic.c
+++ b/EVT/EXAM/BLE/PAwR_ADV/APP/adv_periodic.c
@@ -101,8 +101,6 @@ void Periodic_Init(void)
         GAPRole_SetParameter(GAPROLE_ADV_EVENT_TYPE, sizeof(uint8_t), &advertise_event_type);
         GAPRole_SetParameter(GAPROLE_ADV_CHANNEL_MAP, sizeof(uint8_t), &map);
         GAPRole_SetParameter(GAPROLE_ADVERT_ENABLED, sizeof(uint8_t), &initial_advertising_enable);
-        // Set the GAP Role Parameters
-        GAPRole_SetParameter(GAPROLE_ADVERT_ENABLED, sizeof(uint8_t), &initial_advertising_enable);
     }
 
     {
diff --git a/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c b/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/PAwR_ADV/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c b/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/PAwR_RSP/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Peripheral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/Peripheral_ETH/APP/include/system_ch32v20x.h b/EVT/EXAM/BLE/Peripheral_ETH/APP/include/system_ch32v20x.h
index 51373e3..1090bb0 100644
--- a/EVT/EXAM/BLE/Peripheral_ETH/APP/include/system_ch32v20x.h
+++ b/EVT/EXAM/BLE/Peripheral_ETH/APP/include/system_ch32v20x.h
@@ -22,7 +22,7 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
 /* System_Exported_Functions */
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
+
 
 #ifdef __cplusplus
 }
diff --git a/EVT/EXAM/BLE/Peripheral_ETH/APP/peripheral.c b/EVT/EXAM/BLE/Peripheral_ETH/APP/peripheral.c
index 5321c7d..dba2bd1 100644
--- a/EVT/EXAM/BLE/Peripheral_ETH/APP/peripheral.c
+++ b/EVT/EXAM/BLE/Peripheral_ETH/APP/peripheral.c
@@ -179,7 +179,8 @@ static gapRolesBroadcasterCBs_t Broadcaster_BroadcasterCBs = {
 // GAP Bond Manager Callbacks
 static gapBondCBs_t Peripheral_BondMgrCBs = {
     NULL, // Passcode callback (not used by application)
-    NULL  // Pairing / Bonding state Callback (not used by application)
+    NULL, // Pairing / Bonding state Callback (not used by application)
+    NULL  // oob callback
 };
 
 // Simple GATT Profile Callbacks
@@ -223,7 +224,7 @@ void Peripheral_Init()
     }
 
     // Set the GAP Characteristics
-    GGS_SetParameter(GGS_DEVICE_NAME_ATT, GAP_DEVICE_NAME_LEN, attDeviceName);
+    GGS_SetParameter(GGS_DEVICE_NAME_ATT, sizeof(attDeviceName), attDeviceName);
 
     {
         uint16_t advInt = DEFAULT_ADVERTISING_INTERVAL;
@@ -478,7 +479,7 @@ static void Peripheral_LinkEstablished(gapRoleEvent_t *pEvent)
         peripheralConnList.connInterval = event->connInterval;
         peripheralConnList.connSlaveLatency = event->connLatency;
         peripheralConnList.connTimeout = event->connTimeout;
-
+        peripheralMTU = ATT_MTU_SIZE;
         // Set timer for periodic event
         tmos_start_task(Peripheral_TaskID, SBP_PERIODIC_EVT, SBP_PERIODIC_EVT_PERIOD);
 
diff --git a/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c b/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c
index acb5bf5..730825a 100644
--- a/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/Peripheral_ETH/APP/system_ch32v20x.c
@@ -2,84 +2,101 @@
  * File Name          : system_ch32v20x.c
  * Author             : WCH
  * Version            : V1.0.0
- * Date               : 2022/06/16
+ * Date               : 2021/06/06
  * Description        : CH32V20x Device Peripheral Access Layer System Source File.
- *                      For HSE = 32Mhz
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
  *********************************************************************************
  * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
  * Attention: This software (modified or not) and binary are used for 
  * microcontroller manufactured by Nanjing Qinheng Microelectronics.
  *******************************************************************************/
+#include "ch32v20x.h" 
 
-/*********************************************************************
- * INCLUDES
- */
-#include "ch32v20x.h"
-
-/*
- * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
- * reset the HSI is used as SYSCLK source).
- * If none of the define below is enabled, the HSI is used as System clock source.
- */
-//#define SYSCLK_FREQ_HSE       HSE_VALUE
-//#define SYSCLK_FREQ_24MHz     24000000
-//#define SYSCLK_FREQ_48MHz     48000000
-//#define SYSCLK_FREQ_56MHz     56000000
-//#define SYSCLK_FREQ_72MHz     72000000
-//#define SYSCLK_FREQ_96MHz     96000000
-#define SYSCLK_FREQ_120MHz    120000000
-//#define SYSCLK_FREQ_144MHz    144000000
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+//#define SYSCLK_FREQ_96MHz_HSE  96000000
+#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
 
 /* Clock Definitions */
 #ifdef SYSCLK_FREQ_HSE
-uint32_t      SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
 
-#elif defined SYSCLK_FREQ_96MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_96MHz; /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_120MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_120MHz; /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_144MHz
-uint32_t    SystemCoreClock = SYSCLK_FREQ_144MHz; /* System Clock Frequency (Core Clock) */
-
-#else /* HSI Selected as System Clock source */
-uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
 #endif
 
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
-/*********************************************************************
- * @fn      SetSysClock
- *
- * @brief   system_private_function_proto_types.
- *
- * @return  none
- */
-void SetSysClock(void);
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
 
 #ifdef SYSCLK_FREQ_HSE
-static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_48MHz
-static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
-static void SetSysClockTo72(void);
-#elif defined SYSCLK_FREQ_96MHz
-static void SetSysClockTo96(void);
-#elif defined SYSCLK_FREQ_120MHz
-static void SetSysClockTo120(void);
-#elif defined SYSCLK_FREQ_144MHz
-static void SetSysClockTo144(void);
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
 
 #endif
 
@@ -87,21 +104,22 @@ static void SetSysClockTo144(void);
  * @fn      SystemInit
  *
  * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
- *          the PLL and update the SystemCoreClock variable.
+ *        the PLL and update the SystemCoreClock variable.
  *
  * @return  none
  */
-void SystemInit(void)
+void SystemInit (void)
 {
-    RCC->CTLR |= (uint32_t)0x00000001;
-    RCC->CFGR0 &= (uint32_t)0xF8FF0000;
-    RCC->CTLR &= (uint32_t)0xFEF6FFFF;
-    RCC->CTLR &= (uint32_t)0xFFFBFFFF;
-    RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
-    RCC->INTR = 0x009F0000;
-    SetSysClock();
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
 }
 
+
 /*********************************************************************
  * @fn      SystemCoreClockUpdate
  *
@@ -109,55 +127,73 @@ void SystemInit(void)
  *
  * @return  none
  */
-void SystemCoreClockUpdate(void)
+void SystemCoreClockUpdate (void)
 {
-    uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
 
-    tmp = RCC->CFGR0 & RCC_SWS;
+  tmp = RCC->CFGR0 & RCC_SWS;
 
-    switch(tmp)
-    {
-        case 0x00:
-            SystemCoreClock = HSI_VALUE;
-            break;
-        case 0x04:
-            SystemCoreClock = HSE_VALUE;
-            break;
-        case 0x08:
-            pllmull = RCC->CFGR0 & RCC_PLLMULL;
-            pllsource = RCC->CFGR0 & RCC_PLLSRC;
-            pllmull = (pllmull >> 18) + 2;
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
 
-            if(pllmull == 17)
-                pllmull = 18;
+      if(pllmull == 17) pllmull = 18;
 
-            if(pllsource == 0x00)
-            {
-                SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-            }
-            else
-            {
-                if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
-                {
-                    SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-                }
-                else
-                {
-                    SystemCoreClock = HSE_VALUE * pllmull;
-                }
-            }
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
 
-            if(Pll_6_5 == 1)
-                SystemCoreClock = (SystemCoreClock / 2);
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
 
-            break;
-        default:
-            SystemCoreClock = HSI_VALUE;
-            break;
-    }
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
 
-    tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
-    SystemCoreClock >>= tmp;
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
 }
 
 /*********************************************************************
@@ -167,33 +203,44 @@ void SystemCoreClockUpdate(void)
  *
  * @return  none
  */
-void SetSysClock(void)
+static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-    SetSysClockTo24();
-#elif defined SYSCLK_FREQ_48MHz
-    SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-    SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
-    SetSysClockTo72();
-
-#elif defined SYSCLK_FREQ_96MHz
-    SetSysClockTo96();
-#elif defined SYSCLK_FREQ_120MHz
-    SetSysClockTo120();
-#elif defined SYSCLK_FREQ_144MHz
-    SetSysClockTo144();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
 
 #endif
-
-    /* If none of the define above is enabled, the HSI is used as System clock
-     * source (default after reset)
-     */
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
 }
 
+
 #ifdef SYSCLK_FREQ_HSE
 
 /*********************************************************************
@@ -205,401 +252,358 @@ void SetSysClock(void)
  */
 static void SetSysClockToHSE(void)
 {
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
 
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source 
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
     {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
-    {
-        HSEStatus = (uint32_t)0x01;
-    }
-    else
-    {
-        HSEStatus = (uint32_t)0x00;
-    }
-
-    if(HSEStatus == (uint32_t)0x01)
-    {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-
-        /* Select HSE as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
-
-        /* Wait till HSE is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
-        {
-        }
-    }
-    else
-    {
-        /* If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
-         */
     }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
 }
 
-#elif defined SYSCLK_FREQ_24MHz
+#elif defined SYSCLK_FREQ_48MHz_HSE
 
 /*********************************************************************
- * @fn      SetSysClockTo24
- *
- * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo24(void)
-{
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
-    {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
-    {
-        HSEStatus = (uint32_t)0x01;
-    }
-    else
-    {
-        HSEStatus = (uint32_t)0x00;
-    }
-    if(HSEStatus == (uint32_t)0x01)
-    {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
-        /* If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
-         */
-    }
-}
-
-#elif defined SYSCLK_FREQ_48MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo48
+ * @fn      SetSysClockTo48_HSE
  *
  * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
  *
  * @return  none
  */
-static void SetSysClockTo48(void)
+static void SetSysClockTo48_HSE(void)
 {
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
-    {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
 
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
     {
-        HSEStatus = (uint32_t)0x01;
     }
-    else
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
-        HSEStatus = (uint32_t)0x00;
-    }
-
-    if(HSEStatus == (uint32_t)0x01)
-    {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-        /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
-
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
-         */
     }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
 }
 
-#elif defined SYSCLK_FREQ_56MHz
+#elif defined SYSCLK_FREQ_56MHz_HSE
 
 /*********************************************************************
- * @fn      SetSysClockTo56
+ * @fn      SetSysClockTo56_HSE
  *
  * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
  *
  * @return  none
  */
-static void SetSysClockTo56(void)
+static void SetSysClockTo56_HSE(void)
 {
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
 
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
-    {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
 
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
     {
-        HSEStatus = (uint32_t)0x01;
-    }
-    else
-    {
-        HSEStatus = (uint32_t)0x00;
     }
 
-    if(HSEStatus == (uint32_t)0x01)
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-        /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
-
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
-         */
     }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
 }
 
-#elif defined SYSCLK_FREQ_72MHz
+#elif defined SYSCLK_FREQ_72MHz_HSE
 
 /*********************************************************************
- * @fn      SetSysClockTo72
+ * @fn      SetSysClockTo72_HSE
  *
  * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
  *
  * @return  none
  */
-static void SetSysClockTo72(void)
+static void SetSysClockTo72_HSE(void)
 {
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
 
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
     {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
-        HSEStatus = (uint32_t)0x01;
-    }
-    else
-    {
-        HSEStatus = (uint32_t)0x00;
-    }
-
-    if(HSEStatus == (uint32_t)0x01)
-    {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                              RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
-
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
-         */
     }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
 }
 
-#elif defined SYSCLK_FREQ_96MHz
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
 
 /*********************************************************************
- * @fn      SetSysClockTo96
+ * @fn      SetSysClockTo96_HSE
  *
  * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
  *
  * @return  none
  */
-static void SetSysClockTo96(void)
+static void SetSysClockTo96_HSE(void)
 {
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
 
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
     {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
-    {
-        HSEStatus = (uint32_t)0x01;
     }
-    else
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
-        HSEStatus = (uint32_t)0x00;
     }
-
-    if(HSEStatus == (uint32_t)0x01)
-    {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-        /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                              RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
-
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
+  }
+  else
+  {
         /*
          * If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
+     * configuration. User can add here some code to deal with this error
          */
-    }
+  }
 }
 
-#elif defined SYSCLK_FREQ_120MHz
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
 
 /*********************************************************************
- * @fn      SetSysClockTo120
+ * @fn      SetSysClockTo120_HSE
  *
  * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
  *
  * @return  none
  */
-static void SetSysClockTo120(void)
+static void SetSysClockTo120_HSE(void)
 {
     __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 
@@ -623,14 +627,23 @@ static void SetSysClockTo120(void)
 
     if(HSEStatus == (uint32_t)0x01)
     {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
         /* HCLK = SYSCLK */
         RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
         /* PCLK2 = HCLK */
         RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
         /* PCLK1 = HCLK */
         RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-        /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
         RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
                                               RCC_PLLMULL));
 
@@ -658,74 +671,320 @@ static void SetSysClockTo120(void)
          */
     }
 }
-
-#elif defined SYSCLK_FREQ_144MHz
+#elif defined SYSCLK_FREQ_144MHz_HSE
 
 /*********************************************************************
- * @fn      SetSysClockTo144
+ * @fn      SetSysClockTo144_HSE
  *
  * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
  *
  * @return  none
  */
-static void SetSysClockTo144(void)
+static void SetSysClockTo144_HSE(void)
 {
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
 
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
     {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
-    {
-        HSEStatus = (uint32_t)0x01;
     }
-    else
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
-        HSEStatus = (uint32_t)0x00;
     }
-
-    if(HSEStatus == (uint32_t)0x01)
-    {
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-        /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                              RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
-
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
+  }
+  else
+  {
         /*
          * If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
+     * configuration. User can add here some code to deal with this error
          */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
     }
 }
 
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
 #endif
diff --git a/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RF_PHY/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RF_PHY_Auto/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RF_PHY_Hop/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c b/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/RunningSensor/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SYNC_ADV/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/SYNC_SCAN/APP/observer.c b/EVT/EXAM/BLE/SYNC_SCAN/APP/observer.c
index e9a9557..09f83ad 100644
--- a/EVT/EXAM/BLE/SYNC_SCAN/APP/observer.c
+++ b/EVT/EXAM/BLE/SYNC_SCAN/APP/observer.c
@@ -224,7 +224,7 @@ static void ObserverEventCB(gapRoleEvent_t *pEvent)
 
         case GAP_DEVICE_INFO_EVENT:
         {
-//            ObserverAddDeviceInfo(pEvent->deviceInfo.addr, pEvent->deviceInfo.addrType);
+            ObserverAddDeviceInfo(pEvent->deviceInfo.addr, pEvent->deviceInfo.addrType);
         }
         break;
 
diff --git a/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SYNC_SCAN/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/SpeedTest_Central/.cproject b/EVT/EXAM/BLE/SpeedTest_Central/.cproject
index 6a3ada4..d20a094 100644
--- a/EVT/EXAM/BLE/SpeedTest_Central/.cproject
+++ b/EVT/EXAM/BLE/SpeedTest_Central/.cproject
@@ -69,8 +69,8 @@
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs.177116515" name="Defined symbols (-D)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="BLE_MEMHEAP_SIZE=10240"/>
 									<listOptionValue builtIn="false" value="CH32V20x_D8W"/>
-									<listOptionValue builtIn="false" value="BLE_TX_NUM_EVENT=5"/>
-									<listOptionValue builtIn="false" value="BLE_BUFF_NUM=10"/>
+									<listOptionValue builtIn="false" value="BLE_TX_NUM_EVENT=9"/>
+									<listOptionValue builtIn="false" value="BLE_BUFF_NUM=20"/>
 									<listOptionValue builtIn="false" value="CLK_OSC32K=0"/>
 									<listOptionValue builtIn="false" value="BLE_BUFF_MAX_LEN=247"/>
 								</option>
diff --git a/EVT/EXAM/BLE/SpeedTest_Central/APP/central.c b/EVT/EXAM/BLE/SpeedTest_Central/APP/central.c
index 80649fc..2bc9bc0 100644
--- a/EVT/EXAM/BLE/SpeedTest_Central/APP/central.c
+++ b/EVT/EXAM/BLE/SpeedTest_Central/APP/central.c
@@ -38,11 +38,27 @@
 // Scan duration in 0.625ms
 #define DEFAULT_SCAN_DURATION               2400
 
+/*  1M Parameter    same as peripheral
+ *  BLE_BUFF_NUM:20
+ *  BLE_TX_NUM_EVENT:6
+ *  CONNECTION_INTERVAL:13
+ */
+//// Connection min interval in 1.25ms
+//#define DEFAULT_MIN_CONNECTION_INTERVAL     13
+//
+//// Connection max interval in 1.25ms
+//#define DEFAULT_MAX_CONNECTION_INTERVAL     13
+
+/*  2M Parameter    same as peripheral
+ *  BLE_BUFF_NUM:20
+ *  BLE_TX_NUM_EVENT:9
+ *  CONNECTION_INTERVAL:12
+ */
 // Connection min interval in 1.25ms
-#define DEFAULT_MIN_CONNECTION_INTERVAL     11
+#define DEFAULT_MIN_CONNECTION_INTERVAL     12
 
 // Connection max interval in 1.25ms
-#define DEFAULT_MAX_CONNECTION_INTERVAL     11
+#define DEFAULT_MAX_CONNECTION_INTERVAL     12
 
 // Connection supervision timeout in 10ms
 #define DEFAULT_CONNECTION_TIMEOUT          100
diff --git a/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SpeedTest_Central/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/SpeedTest_Peripheral/.cproject b/EVT/EXAM/BLE/SpeedTest_Peripheral/.cproject
index 04aa7af..4515dcf 100644
--- a/EVT/EXAM/BLE/SpeedTest_Peripheral/.cproject
+++ b/EVT/EXAM/BLE/SpeedTest_Peripheral/.cproject
@@ -71,8 +71,8 @@
 									<listOptionValue builtIn="false" value="CH32V20x_D8W"/>
 									<listOptionValue builtIn="false" value="CLK_OSC32K=0"/>
 									<listOptionValue builtIn="false" value="BLE_MAC=1"/>
-									<listOptionValue builtIn="false" value="BLE_TX_NUM_EVENT=5"/>
-									<listOptionValue builtIn="false" value="BLE_BUFF_NUM=10"/>
+									<listOptionValue builtIn="false" value="BLE_TX_NUM_EVENT=9"/>
+									<listOptionValue builtIn="false" value="BLE_BUFF_NUM=20"/>
 									<listOptionValue builtIn="false" value="BLE_BUFF_MAX_LEN=247"/>
 								</option>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.files.288896968" name="Include files (-include)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles"/>
diff --git a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/SpeedTest_Peripheral/APP/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c b/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c
index f4110b2..8a8fa40 100644
--- a/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c
+++ b/EVT/EXAM/BLE/peripheral_ancs_client/app/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c b/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c
+++ b/EVT/EXAM/CAN/Networking/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c b/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c
+++ b/EVT/EXAM/CAN/TestMode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c b/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c
+++ b/EVT/EXAM/CAN/Time-triggered/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c b/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c
+++ b/EVT/EXAM/CRC/CRC_Calculation/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/.settings/language.settings.xml b/EVT/EXAM/DMA/DMA_MEM2MEM/.settings/language.settings.xml
deleted file mode 100644
index 11fded0..0000000
--- a/EVT/EXAM/DMA/DMA_MEM2MEM/.settings/language.settings.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="840048624785371720" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-</project>
diff --git a/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c b/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c
+++ b/EVT/EXAM/DMA/DMA_MEM2MEM/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/ETH/DHCP/.cproject b/EVT/EXAM/ETH/DHCP/.cproject
index 8d514ae..e2d5e95 100644
--- a/EVT/EXAM/ETH/DHCP/.cproject
+++ b/EVT/EXAM/ETH/DHCP/.cproject
@@ -242,5 +242,4 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	
 </cproject>
diff --git a/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c b/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/DHCP/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c b/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/DNS/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/ETH_CFG/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/ETH_IAP/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c b/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/ETH_UART/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c b/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/IPRaw_PING/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/MAC_RAW/.cproject b/EVT/EXAM/ETH/MAC_RAW/.cproject
index 7fa67d0..3395801 100644
--- a/EVT/EXAM/ETH/MAC_RAW/.cproject
+++ b/EVT/EXAM/ETH/MAC_RAW/.cproject
@@ -235,5 +235,5 @@
 			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
 	</storageModule>
-	
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c b/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
index d0e29f5..74d5065 100644
--- a/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
+++ b/EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
@@ -460,6 +460,8 @@ void ETH_Configuration( uint8_t *macAddr )
     R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN;                             //Hardware padded CRC
     R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN;                             //Jumbo frames are not received
     R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
+    R8_ETH_ECON2 &= ~(0x07 << 1);
+    R8_ETH_ECON2 |= 5 << 1;
 
     EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
 }
diff --git a/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c b/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c b/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/MQTT/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c b/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/Mail/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/NetLib/eth_driver.c b/EVT/EXAM/ETH/NetLib/eth_driver.c
index cebd4d3..4a16469 100644
--- a/EVT/EXAM/ETH/NetLib/eth_driver.c
+++ b/EVT/EXAM/ETH/NetLib/eth_driver.c
@@ -507,6 +507,8 @@ void ETH_Configuration( uint8_t *macAddr )
     R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN;                             //Hardware padded CRC
     R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN;                             //Jumbo frames are not received
     R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
+    R8_ETH_ECON2 &= ~(0x07 << 1);
+    R8_ETH_ECON2 |= 5 << 1;
 
     EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
 }
diff --git a/EVT/EXAM/ETH/NetLib/libwchnet.a b/EVT/EXAM/ETH/NetLib/libwchnet.a
index ccab70a976a8c84755fd698ba1e6887114da34f2..151c5eb9595e13121987089b3377cab333a4af90 100644
GIT binary patch
delta 14283
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diff --git a/EVT/EXAM/ETH/NetLib/wchnet.h b/EVT/EXAM/ETH/NetLib/wchnet.h
index 25b2e3c..0e2764a 100644
--- a/EVT/EXAM/ETH/NetLib/wchnet.h
+++ b/EVT/EXAM/ETH/NetLib/wchnet.h
@@ -1,7 +1,7 @@
 /********************************** (C) COPYRIGHT *******************************
  * File Name          : wchnet.h
  * Author             : WCH
- * Version            : V1.80
+ * Version            : V1.90
  * Date               : 2023/05/12
  * Description        : This file contains the headers of 
 *                    the Ethernet protocol stack library.
@@ -21,7 +21,7 @@
 extern "C" {
 #endif
 
-#define WCHNET_LIB_VER                  0x18              //the library version number
+#define WCHNET_LIB_VER                  0x19              //the library version number
 #define WCHNET_CFG_VALID                0x12345678        //Configuration value valid flag
 
 /* LED state @LED_STAT */
diff --git a/EVT/EXAM/ETH/TcpClient/.cproject b/EVT/EXAM/ETH/TcpClient/.cproject
index 6369868..97a5e3f 100644
--- a/EVT/EXAM/ETH/TcpClient/.cproject
+++ b/EVT/EXAM/ETH/TcpClient/.cproject
@@ -244,5 +244,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c b/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/TcpClient/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/TcpServer/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c b/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/UdpClient/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/UdpServer/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/ETH/WCHNET Protocol Stack Library Application Note.PDF b/EVT/EXAM/ETH/WCHNET Protocol Stack Library Application Note.PDF
index 7f028b5e863df12178c815816b051069c581c484..998b4bd2dfbe07405f1abe68252a55dcf8fb1f84 100644
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diff --git a/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c b/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
index 7834d54..563fb0f 100644
--- a/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
+++ b/EVT/EXAM/ETH/WebServer/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
     
-    /* Select HSE as system clock source 
+    /* Select HSE as system clock source
      *  CH32V20x_D6 (HSE=8MHZ)
      *  CH32V20x_D8 (HSE=32MHZ)
      *  CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
   
-
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
  
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
-    
     /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
      *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
      *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
diff --git a/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c b/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c
+++ b/EVT/EXAM/EXTI/EXTI0/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/FLASH/FLASH_Program/User/main.c b/EVT/EXAM/FLASH/FLASH_Program/User/main.c
index 95a83b5..039c031 100644
--- a/EVT/EXAM/FLASH/FLASH_Program/User/main.c
+++ b/EVT/EXAM/FLASH/FLASH_Program/User/main.c
@@ -56,7 +56,10 @@ uint32_t NbrOfPage;
 volatile FLASH_Status FLASHStatus = FLASH_COMPLETE;
 volatile TestStatus MemoryProgramStatus = PASSED;
 volatile TestStatus MemoryEraseStatus = PASSED;
-u32 buf[64];
+
+#define Fadr    (0x08020000)
+#define Fsize   ((((256*4))>>2))
+u32 buf[Fsize];
 
 /*********************************************************************
  * @fn      Flash_Test
@@ -116,9 +119,7 @@ void Flash_Test(void)
        printf("Memory Program PASS!\r\n");
     }
 
-
-     FLASH_Lock();
-
+    FLASH_Lock();
 }
 
 /*********************************************************************
@@ -130,71 +131,59 @@ void Flash_Test(void)
  */
 void Flash_Test_Fast(void)
 {
-	u16 i,j,flag;
+    u32 i;
+    u8 Verify_Flag = 0;
+    FLASH_Status s;
 
-    for(i=0; i<64; i++){
+    for(i = 0; i < Fsize; i++){
         buf[i] = i;
     }
 
-    printf("FLASH Fast Mode Test\n");
+    printf("Read flash\r\n");
+    for(i=0; i<Fsize; i++){
+        printf("adr-%08x v-%08x\r\n", Fadr +4*i, *(u32*)(Fadr +4*i));
+    }
 
-	FLASH_Unlock_Fast();
+    s = FLASH_ROM_ERASE(Fadr, Fsize*4);
+    if(s != FLASH_COMPLETE)
+    {
+        printf("check FLASH_ADR_RANGE_ERROR FLASH_ALIGN_ERROR or FLASH_OP_RANGE_ERROR\r\n");
+        return;
+    }
 
-	FLASH_EraseBlock_32K_Fast(FAST_FLASH_PROGRAM_START_ADDR);
+    printf("Erase flash\r\n");
+    for(i=0; i<Fsize; i++){
+        printf("adr-%08x v-%08x\r\n", Fadr +4*i, *(u32*)(Fadr +4*i));
+    }
 
-	printf("Program 32KByte start\n");
-	for(i=0; i<128; i++){
-	    FLASH_ProgramPage_Fast(FAST_FLASH_PROGRAM_START_ADDR + 256*i, buf);
-	}
+    s = FLASH_ROM_WRITE(Fadr,  buf, Fsize*4);
+    if(s != FLASH_COMPLETE)
+    {
+        printf("check FLASH_ADR_RANGE_ERROR FLASH_ALIGN_ERROR or FLASH_OP_RANGE_ERROR\r\n");
+        return;
+    }
 
-	for(i=0; i<128; i++){
-	    for(j=0; j<64; j++){
-	        if(*(u32*)(FAST_FLASH_PROGRAM_START_ADDR+256*i+4*j) != j){
-	            flag = 0;
-	            break;
-	        }
-	        else{
-	            flag = 1;
-	        }
-	    }
+    printf("Write flash\r\n");
+    for(i=0; i<Fsize; i++){
+        printf("adr-%08x v-%08x\r\n", Fadr +4*i, *(u32*)(Fadr +4*i));
+    }
 
-	}
+    for(i = 0; i < Fsize; i++){
+        if(buf[i] == *(u32 *)(Fadr + 4 * i))
+        {
+            Verify_Flag = 0;
+        }
+        else
+        {
+            Verify_Flag = 1;
+            break;
+        }
+    }
 
-	if(flag){
-	    printf("Program 32KByte suc\n");
-	}
-	else printf("Program fail\n");
-
-	printf("Erase 256Byte...\n");
-	FLASH_ErasePage_Fast(FAST_FLASH_PROGRAM_START_ADDR);
-
-	printf("Read 4KByte...\n");
-	for(i=0;i<1024; i++){
-      printf("%08x ",*(u32*)(FAST_FLASH_PROGRAM_START_ADDR+4*i));
-
-	}printf("\n");
-
-    printf("Erase 4KByte...\n");
-    FLASH_ErasePage(FAST_FLASH_PROGRAM_START_ADDR);
-
-    printf("Read 8KByte...\n");
-    for(i=0;i<2048; i++){
-      printf("%08x ",*(u32*)(FAST_FLASH_PROGRAM_START_ADDR+4*i));
-
-    }printf("\n");
-
-    printf("Erase 32KByte...\n");
-    FLASH_EraseBlock_32K_Fast(FAST_FLASH_PROGRAM_START_ADDR);
-
-    printf("Read 32KByte...\n");
-    for(i=0;i<(1024*9); i++){
-      printf("%08x ",*(u32*)(FAST_FLASH_PROGRAM_START_ADDR+4*i));
-
-    }printf("\n");
-
-
-    FLASH_Lock_Fast();
-    FLASH_Lock();
+    if(Verify_Flag)
+        printf("%d Byte Verify Fail\r\n", (Fsize*4));
+    else
+        printf("%d Byte Verify Suc\r\n", (Fsize*4));
 }
 
 /*********************************************************************
diff --git a/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c b/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c
+++ b/EVT/EXAM/FLASH/FLASH_Program/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.cproject b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.cproject
index e6e7863..b0dd128 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.cproject
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.cproject
@@ -1,157 +1,157 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
-<?fileVersion 4.0.0?>
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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-    <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
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-        <externalSettings />
-        <extensions>
-          <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" />
-          <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
-          <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
-          <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
-          <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" />
-          <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
-        </extensions>
-      </storageModule>
-      <storageModule moduleId="cdtBuildSystem" version="4.0.0">
-        <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
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+								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.1610882921" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.1620074387" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections.194760422" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.2057340378" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1390103472" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Ld/Link.ld}&quot;"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.913830613" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.239404511" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnosys.351964161" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnosys" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs.16994550" name="Other objects" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs" useByScannerDiscovery="false" valueType="userObjs"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags.1125808200" name="Linker flags (-Xlinker [option])" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags" useByScannerDiscovery="false" valueType="stringList"/>
+								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1859223768" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1947503520" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1689063433" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths.1029177148" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;../LD&quot;"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile.1751226764" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="Link.ld"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.1540675679" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1298918921" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="Core|Debug|FreeRTOS/portable/Common/mpu_wrappers.c|SRC|LiteOS/components/cppsupport|User/task_sample.c|LiteOS/kal|Peripheral|LiteOS/third_party/cmsis/CMSIS/Core|LiteOS/components/exchook|LiteOS/third_party/cmsis|Ld|User/task_sample.h|LiteOS/components/net|LiteOS/testsuits|Startup|LiteOS/components/fs" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry excluding="startup_ch32v20x_D8W.S|startup_ch32v20x_D8.S|startup_ch32v20x.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.project b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.project
index 759d26e..ae8017e 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.project
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/.project
@@ -1,18 +1,18 @@
-<?xml version="1.0" encoding="UTF-8" ?> 
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <projectDescription>
   <name>FreeRTOS</name>
-  <comment />
-  <projects />
+  <comment/>
+  <projects/>
   <buildSpec>
     <buildCommand>
       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
       <triggers>clean,full,incremental,</triggers>
-      <arguments />
+      <arguments/>
     </buildCommand>
     <buildCommand>
       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
       <triggers>full,incremental,</triggers>
-      <arguments />
+      <arguments/>
     </buildCommand>
   </buildSpec>
   <natures>
@@ -40,7 +40,7 @@
   <filteredResources>
     <filter>
       <id>1595986042669</id>
-      <name />
+      <name/>
       <type>22</type>
       <matcher>
         <id>org.eclipse.ui.ide.multiFilter</id>
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S
index c5f7079..5b20961 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D6.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D6.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/13
 ;* Description        :  CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -99,7 +87,6 @@ _vector_base:
     .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -156,60 +143,62 @@ _vector_base:
     .weak   UART4_IRQHandler           /* UART4 */
     .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -222,7 +211,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -234,7 +223,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -243,17 +232,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested  */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x2
 	csrw 0x804, t0
-
-    /* Enable interrupt */
-   	li t0, 0x1800
-   	csrs mstatus, t0
-
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S
new file mode 100644
index 0000000..6d0188e
--- /dev/null
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8.S
@@ -0,0 +1,269 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V203RB
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   0                          /* BLE BB */
+    .word   0                          /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+TIM5_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S
new file mode 100644
index 0000000..dad9c92
--- /dev/null
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/Startup/startup_ch32v20x_D8W.S
@@ -0,0 +1,275 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8W.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V208x
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   BB_IRQHandler              /* BLE BB */
+    .word   LLE_IRQHandler             /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   BB_IRQHandler              /* BLE BB */
+    .weak   LLE_IRQHandler             /* BLE LLE */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+BB_IRQHandler:
+LLE_IRQHandler:
+TIM5_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
+
+
diff --git a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c
+++ b/EVT/EXAM/FreeRTOS/FreeRTOS_Core/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c b/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c
+++ b/EVT/EXAM/GPIO/GPIO_Toggle/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/.cproject b/EVT/EXAM/HarmonyOS/LiteOS_m/.cproject
index 71aa401..4d0a750 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/.cproject
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/.cproject
@@ -1,262 +1,262 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
-<?fileVersion 4.0.0?>
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-  <storageModule moduleId="org.eclipse.cdt.core.settings">
-    <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
-      <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
-        <externalSettings />
-        <extensions>
-          <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" />
-          <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
-          <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
-          <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
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+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.1796908532" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.1610882921"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.2119140349" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.1620074387"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.957422234" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1947503520"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.940539115" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1092495852" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1656640092" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.110026313" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="Startup/startup_ch32v20x_D8W.S|Startup/startup_ch32v20x_D8.S|Core|Ld|Startup/startup_ch32v20x.S|LiteOS/components/cppsupport|User/task_sample.c|LiteOS/kal|Peripheral|LiteOS/third_party/cmsis/CMSIS/Core|LiteOS/components/exchook|LiteOS/third_party/cmsis|User/task_sample.h|LiteOS/components/net|Debug|LiteOS/testsuits|LiteOS/components/fs" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/.project b/EVT/EXAM/HarmonyOS/LiteOS_m/.project
index be5dc64..e0e6276 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/.project
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/.project
@@ -1,18 +1,18 @@
-<?xml version="1.0" encoding="UTF-8" ?> 
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <projectDescription>
   <name>LiteOS_m</name>
-  <comment />
-  <projects />
+  <comment/>
+  <projects/>
   <buildSpec>
     <buildCommand>
       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
       <triggers>clean,full,incremental,</triggers>
-      <arguments />
+      <arguments/>
     </buildCommand>
     <buildCommand>
       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
       <triggers>full,incremental,</triggers>
-      <arguments />
+      <arguments/>
     </buildCommand>
   </buildSpec>
   <natures>
@@ -23,7 +23,7 @@
   <filteredResources>
     <filter>
       <id>1595986042669</id>
-      <name />
+      <name/>
       <type>22</type>
       <matcher>
         <id>org.eclipse.ui.ide.multiFilter</id>
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S
index c5f7079..ce1ea08 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D6.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D6.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/11
 ;* Description        :  CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -99,7 +87,6 @@ _vector_base:
     .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -156,60 +143,62 @@ _vector_base:
     .weak   UART4_IRQHandler           /* UART4 */
     .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -222,7 +211,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -234,7 +223,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -243,17 +232,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested  */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x2
 	csrw 0x804, t0
-
-    /* Enable interrupt */
-   	li t0, 0x1800
-   	csrs mstatus, t0
-
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S
new file mode 100644
index 0000000..6d0188e
--- /dev/null
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8.S
@@ -0,0 +1,269 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V203RB
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   0                          /* BLE BB */
+    .word   0                          /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+TIM5_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S
new file mode 100644
index 0000000..dad9c92
--- /dev/null
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/Startup/startup_ch32v20x_D8W.S
@@ -0,0 +1,275 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8W.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V208x
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   BB_IRQHandler              /* BLE BB */
+    .word   LLE_IRQHandler             /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   BB_IRQHandler              /* BLE BB */
+    .weak   LLE_IRQHandler             /* BLE LLE */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+BB_IRQHandler:
+LLE_IRQHandler:
+TIM5_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
+
+
diff --git a/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c b/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c
index b630619..22541b1 100644
--- a/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c
+++ b/EVT/EXAM/HarmonyOS/LiteOS_m/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_10bit_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/BKP/.cproject b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.cproject
similarity index 97%
rename from EVT/EXAM/BKP/.cproject
rename to EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.cproject
index 4e7274b..696ddf7 100644
--- a/EVT/EXAM/BKP/.cproject
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.cproject
@@ -45,11 +45,11 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.2088748096" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1007480977" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.784581895" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.489065469" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.1603017616" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1488947117" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/BKP}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/I2C_PEC}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
 							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1244756189" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.project b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.project
new file mode 100644
index 0000000..9b615c7
--- /dev/null
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.project
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<projectDescription>
+  <name>I2C_7bit_Interrupt_Mode</name>
+  <comment/>
+  <projects/>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <filteredResources>
+    <filter>
+      <id>1595986042669</id>
+      <name/>
+      <type>22</type>
+      <matcher>
+        <id>org.eclipse.ui.ide.multiFilter</id>
+        <arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+      </matcher>
+    </filter>
+  </filteredResources>
+  <linkedResources>
+    <link>
+      <name>Core</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
+    </link>
+    <link>
+      <name>Debug</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
+    </link>
+    <link>
+      <name>Ld</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
+    </link>
+    <link>
+      <name>Peripheral</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
+    </link>
+    <link>
+      <name>Startup</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
+    </link>
+  </linkedResources>
+</projectDescription>
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template
new file mode 100644
index 0000000..d207ca4
--- /dev/null
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\I2C_7bit_Interrupt_Mode.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/RTC/RTC.wvproj b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/I2C_7bit_Interrupt_Mode.wvproj
similarity index 100%
rename from EVT/EXAM/RTC/RTC.wvproj
rename to EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/I2C_7bit_Interrupt_Mode.wvproj
diff --git a/EVT/EXAM/WWDG/User/ch32v20x_conf.h b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_conf.h
similarity index 100%
rename from EVT/EXAM/WWDG/User/ch32v20x_conf.h
rename to EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_conf.h
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c
new file mode 100644
index 0000000..3efbd54
--- /dev/null
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.c
@@ -0,0 +1,59 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main Interrupt Service Routines.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void I2C1_ER_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+/*********************************************************************
+ * @fn      I2C1_ER_IRQHandler
+ *
+ * @brief   This function IIC PEC error exception.
+ *
+ * @return  none
+ */
+void I2C1_ER_IRQHandler(void )
+{
+	if( I2C_GetITStatus( I2C1, I2C_IT_PECERR ) != RESET )
+	{
+		printf( "PECEER\r\n" );
+		I2C_ClearITPendingBit( I2C1, I2C_IT_PECERR );
+	}
+}
+
+
diff --git a/EVT/EXAM/TOUCHKEY/User/ch32v20x_it.h b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.h
similarity index 100%
rename from EVT/EXAM/TOUCHKEY/User/ch32v20x_it.h
rename to EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/ch32v20x_it.h
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c
new file mode 100644
index 0000000..b7da4d4
--- /dev/null
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/main.c
@@ -0,0 +1,204 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : main.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main program body.
+ *********************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * Attention: This software (modified or not) and binary are used for 
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
+ *******************************************************************************/
+
+/*
+ *@Note
+ *PEC error check, master/slave mode transceiver routine:
+ *I2C1_SCL(PB8)\I2C1_SDA(PB9).
+ *This example demonstrates that the Master sends with PEC error checking, and the
+ *Slave receives. If a transmission error occurs, an error interrupt is triggered.
+ *Note: The two boards download the Master and Slave programs respectively,
+ *and power on at the same time.
+ *    Hardware connection:PB8 -- PB8
+ *                        PB9 -- PB9
+ *
+ */
+
+#include "debug.h"
+
+/* I2C Mode Definition */
+#define HOST_MODE     0
+#define SLAVE_MODE    1
+
+/* I2C Communication Mode Selection */
+//#define I2C_MODE   HOST_MODE
+#define I2C_MODE      SLAVE_MODE
+
+/* Global define */
+#define Size          7
+#define RXAdderss     0x02
+#define TxAdderss     0x02
+
+/* Global Variable */
+u8 TxData[Size] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06};
+u8 RxData[Size];
+
+/*********************************************************************
+ * @fn      IIC_Init
+ *
+ * @brief   Initializes the IIC peripheral.
+ *
+ * @return  none
+ */
+void IIC_Init(u32 bound, u16 address)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+    I2C_InitTypeDef  I2C_InitTSturcture = {0};
+    NVIC_InitTypeDef NVIC_InitStructure = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
+    GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    I2C_InitTSturcture.I2C_ClockSpeed = bound;
+    I2C_InitTSturcture.I2C_Mode = I2C_Mode_I2C;
+    I2C_InitTSturcture.I2C_DutyCycle = I2C_DutyCycle_16_9;
+    I2C_InitTSturcture.I2C_OwnAddress1 = address;
+    I2C_InitTSturcture.I2C_Ack = I2C_Ack_Enable;
+    I2C_InitTSturcture.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+    I2C_Init(I2C1, &I2C_InitTSturcture);
+
+#if(I2C_MODE == SLAVE_MODE)
+    NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE);
+
+#endif
+
+    I2C_Cmd(I2C1, ENABLE);
+    I2C_CalculatePEC(I2C1, ENABLE);
+
+#if(I2C_MODE == HOST_MODE)
+    I2C_AcknowledgeConfig(I2C1, ENABLE);
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    u8 i = 0;
+    u8 pecValue;
+
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
+    SystemCoreClockUpdate();
+    Delay_Init();
+    USART_Printf_Init(460800);
+    printf("SystemClk:%d\r\n", SystemCoreClock);
+    printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() );
+
+#if(I2C_MODE == HOST_MODE)
+    printf("IIC Host mode\r\n");
+    IIC_Init(80000, TxAdderss);
+
+    while(I2C_GetFlagStatus(I2C1, I2C_FLAG_BUSY) != RESET);
+    I2C_GenerateSTART(I2C1, ENABLE);
+
+    while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT));
+    I2C_Send7bitAddress(I2C1, 0x02, I2C_Direction_Transmitter);
+
+    while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
+
+    while(i < 7)
+    {
+        if(i < 6)
+        {
+            if(I2C_GetFlagStatus(I2C1, I2C_FLAG_TXE) != RESET)
+            {
+                I2C_SendData(I2C1, TxData[i]);
+                i++;
+            }
+        }
+
+        if(i == 6)
+        {
+            if(I2C_GetFlagStatus(I2C1, I2C_FLAG_TXE) != RESET)
+            {
+                I2C_TransmitPEC(I2C1, ENABLE);
+                i++;
+            }
+        }
+    }
+
+    while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
+    I2C_GenerateSTOP(I2C1, ENABLE);
+
+#elif(I2C_MODE == SLAVE_MODE)
+    printf("IIC Slave mode\r\n");
+    IIC_Init(80000, RXAdderss);
+
+    while(!I2C_CheckEvent(I2C1, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED));
+
+    while(i < 7)
+    {
+        if(i < 5)
+        {
+            if(I2C_GetFlagStatus(I2C1, I2C_FLAG_RXNE) != RESET)
+            {
+                RxData[i] = I2C_ReceiveData(I2C1);
+                i++;
+            }
+        }
+
+        if(i == 5)
+        {
+            pecValue = I2C_GetPEC(I2C1);
+            if(I2C_GetFlagStatus(I2C1, I2C_FLAG_RXNE) != RESET)
+            {
+                RxData[i] = I2C_ReceiveData(I2C1);
+                i++;
+            }
+        }
+
+        if(i == 6)
+        {
+            I2C_TransmitPEC(I2C1, ENABLE);
+            if(I2C_GetFlagStatus(I2C1, I2C_FLAG_RXNE) != RESET)
+            {
+                RxData[i] = I2C_ReceiveData(I2C1);
+                i++;
+            }
+        }
+    }
+
+    printf("pecValue:%02x\r\n", pecValue);
+    printf("RxData:\r\n");
+
+    for(i = 0; i < 7; i++)
+    {
+        printf("%02x\r\n", RxData[i]);
+    }
+
+#endif
+
+    while(1);
+}
diff --git a/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c
new file mode 100644
index 0000000..8d3a568
--- /dev/null
+++ b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.c
@@ -0,0 +1,987 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+  //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/EVT/EXAM/RTC/User/system_ch32v20x.h b/EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.h
similarity index 100%
rename from EVT/EXAM/RTC/User/system_ch32v20x.h
rename to EVT/EXAM/I2C/I2C_7bit_Interrupt_Mode/User/system_ch32v20x.h
diff --git a/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_7bit_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_DMA/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_EEPROM/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c b/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c
+++ b/EVT/EXAM/I2C/I2C_PEC/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c
+++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_APP/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c
index 0ede7da..1c72e34 100644
--- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c
+++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/iap.c
@@ -104,6 +104,8 @@ u8 RecData_Deal(void)
          Verity_addr = FLASH_Base;
 
          s = ERR_End;
+         FLASH->CTLR |= ((uint32_t)0x00008000);
+         FLASH->CTLR |= ((uint32_t)0x00000080);
          break;
 
      default:
diff --git a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c
+++ b/EVT/EXAM/IAP/USB_UART/CH32V20x_IAP/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c b/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c
+++ b/EVT/EXAM/INT/Interrupt_VTF/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/IWDG/.cproject b/EVT/EXAM/IWDG/IWDG/.cproject
similarity index 97%
rename from EVT/EXAM/IWDG/.cproject
rename to EVT/EXAM/IWDG/IWDG/.cproject
index ab5eec5..93c33ac 100644
--- a/EVT/EXAM/IWDG/.cproject
+++ b/EVT/EXAM/IWDG/IWDG/.cproject
@@ -45,11 +45,11 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.2015854272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.362653280" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.1799394235" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.2003631682" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.1819910041" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1179366128" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/IWDG}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/GPIO_Toggle}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
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 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
diff --git a/EVT/EXAM/IWDG/.project b/EVT/EXAM/IWDG/IWDG/.project
similarity index 83%
rename from EVT/EXAM/IWDG/.project
rename to EVT/EXAM/IWDG/IWDG/.project
index 5198022..c712f38 100644
--- a/EVT/EXAM/IWDG/.project
+++ b/EVT/EXAM/IWDG/IWDG/.project
@@ -35,27 +35,27 @@
     <link>
       <name>Core</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Core</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
     </link>
     <link>
       <name>Debug</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Debug</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
     </link>
     <link>
       <name>Ld</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Ld</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
     </link>
     <link>
       <name>Peripheral</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Peripheral</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
     </link>
     <link>
       <name>Startup</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Startup</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
     </link>
   </linkedResources>
 </projectDescription>
diff --git a/EVT/EXAM/OPA/.template b/EVT/EXAM/IWDG/IWDG/.template
similarity index 94%
rename from EVT/EXAM/OPA/.template
rename to EVT/EXAM/IWDG/IWDG/.template
index 7fd3109..abca0d4 100644
--- a/EVT/EXAM/OPA/.template
+++ b/EVT/EXAM/IWDG/IWDG/.template
@@ -1,6 +1,6 @@
 Mcu Type=CH32V20x
 Address=0x08000000
-Target Path=obj/OPA.hex
+Target Path=obj\IWDG.hex
 Erase All=true
 Program=true
 Verify=true
@@ -14,3 +14,4 @@ Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH
 
 PeripheralVersion=1.0
 MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/TOUCHKEY/TOUCHKEY.wvproj b/EVT/EXAM/IWDG/IWDG/IWDG.wvproj
similarity index 100%
rename from EVT/EXAM/TOUCHKEY/TOUCHKEY.wvproj
rename to EVT/EXAM/IWDG/IWDG/IWDG.wvproj
diff --git a/EVT/EXAM/IWDG/IWDG/User/ch32v20x_conf.h b/EVT/EXAM/IWDG/IWDG/User/ch32v20x_conf.h
new file mode 100644
index 0000000..d1eeb38
--- /dev/null
+++ b/EVT/EXAM/IWDG/IWDG/User/ch32v20x_conf.h
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+	
+	
+	
diff --git a/EVT/EXAM/TOUCHKEY/User/ch32v20x_it.c b/EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.c
similarity index 100%
rename from EVT/EXAM/TOUCHKEY/User/ch32v20x_it.c
rename to EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.c
diff --git a/EVT/EXAM/WWDG/User/ch32v20x_it.h b/EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.h
similarity index 100%
rename from EVT/EXAM/WWDG/User/ch32v20x_it.h
rename to EVT/EXAM/IWDG/IWDG/User/ch32v20x_it.h
diff --git a/EVT/EXAM/IWDG/User/main.c b/EVT/EXAM/IWDG/IWDG/User/main.c
similarity index 100%
rename from EVT/EXAM/IWDG/User/main.c
rename to EVT/EXAM/IWDG/IWDG/User/main.c
diff --git a/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c b/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c
new file mode 100644
index 0000000..8d3a568
--- /dev/null
+++ b/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.c
@@ -0,0 +1,987 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+  //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/EVT/EXAM/TOUCHKEY/User/system_ch32v20x.h b/EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.h
similarity index 100%
rename from EVT/EXAM/TOUCHKEY/User/system_ch32v20x.h
rename to EVT/EXAM/IWDG/IWDG/User/system_ch32v20x.h
diff --git a/EVT/EXAM/RTC/.cproject b/EVT/EXAM/OPA/OPA_Voltage_Follower/.cproject
similarity index 97%
rename from EVT/EXAM/RTC/.cproject
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/.cproject
index a68e62f..93c33ac 100644
--- a/EVT/EXAM/RTC/.cproject
+++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/.cproject
@@ -45,11 +45,11 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.2081060699" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.276642505" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.2003631682" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.1819910041" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1179366128" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/RTC}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/GPIO_Toggle}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
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 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
diff --git a/EVT/EXAM/OPA/OPA_Voltage_Follower/.project b/EVT/EXAM/OPA/OPA_Voltage_Follower/.project
new file mode 100644
index 0000000..85df6d6
--- /dev/null
+++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/.project
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<projectDescription>
+  <name>OPA_Voltage_Follower</name>
+  <comment/>
+  <projects/>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <filteredResources>
+    <filter>
+      <id>1595986042669</id>
+      <name/>
+      <type>22</type>
+      <matcher>
+        <id>org.eclipse.ui.ide.multiFilter</id>
+        <arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+      </matcher>
+    </filter>
+  </filteredResources>
+  <linkedResources>
+    <link>
+      <name>Core</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
+    </link>
+    <link>
+      <name>Debug</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
+    </link>
+    <link>
+      <name>Ld</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
+    </link>
+    <link>
+      <name>Peripheral</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
+    </link>
+    <link>
+      <name>Startup</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
+    </link>
+  </linkedResources>
+</projectDescription>
diff --git a/EVT/EXAM/OPA/OPA_Voltage_Follower/.template b/EVT/EXAM/OPA/OPA_Voltage_Follower/.template
new file mode 100644
index 0000000..a742393
--- /dev/null
+++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\OPA_Voltage_Follower.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/WWDG/WWDG.wvproj b/EVT/EXAM/OPA/OPA_Voltage_Follower/OPA_Voltage_Follower.wvproj
similarity index 100%
rename from EVT/EXAM/WWDG/WWDG.wvproj
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/OPA_Voltage_Follower.wvproj
diff --git a/EVT/EXAM/OPA/User/ch32v20x_conf.h b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_conf.h
similarity index 100%
rename from EVT/EXAM/OPA/User/ch32v20x_conf.h
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_conf.h
diff --git a/EVT/EXAM/OPA/User/ch32v20x_it.c b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.c
similarity index 100%
rename from EVT/EXAM/OPA/User/ch32v20x_it.c
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.c
diff --git a/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.h b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.h
new file mode 100644
index 0000000..f68b203
--- /dev/null
+++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/ch32v20x_it.h
@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/EVT/EXAM/OPA/User/main.c b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/main.c
similarity index 100%
rename from EVT/EXAM/OPA/User/main.c
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/User/main.c
diff --git a/EVT/EXAM/OPA/User/system_ch32v20x.c b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c
similarity index 99%
rename from EVT/EXAM/OPA/User/system_ch32v20x.c
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c
index 78a0ac4..71e9451 100644
--- a/EVT/EXAM/OPA/User/system_ch32v20x.c
+++ b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/WWDG/User/system_ch32v20x.h b/EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.h
similarity index 100%
rename from EVT/EXAM/WWDG/User/system_ch32v20x.h
rename to EVT/EXAM/OPA/OPA_Voltage_Follower/User/system_ch32v20x.h
diff --git a/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/PWR/Sleep_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/PWR/Standby_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/PWR/Standby_RAM_LV_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/PWR/Standby_RAM_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c b/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/PWR/Stop_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c b/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c
index 61e5167..b1cc5f1 100644
--- a/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c
+++ b/EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c
@@ -161,6 +161,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
   SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz
diff --git a/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c b/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c
index be62c28..bd55d61 100644
--- a/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c
+++ b/EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c
@@ -149,6 +149,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_24MHz
   SetSysClockTo24();
 #elif defined SYSCLK_FREQ_48MHz
diff --git a/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c b/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c
+++ b/EVT/EXAM/RCC/MCO/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/RT-Thread/rt-thread/.cproject b/EVT/EXAM/RT-Thread/rt-thread/.cproject
index 4e0530f..430765f 100644
--- a/EVT/EXAM/RT-Thread/rt-thread/.cproject
+++ b/EVT/EXAM/RT-Thread/rt-thread/.cproject
@@ -1,171 +1,171 @@
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+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/libcpu/risc-v}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/libcpu/risc-v/common}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/libcpu/risc-v/SW_Handler}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/src}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/components/drivers/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/components/drivers/misc}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/components/drivers/serial}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtthread/components/finsh}&quot;"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std.2020844713" name="Language standard" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std.gnu99" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs.177116515" name="Defined symbols (-D)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols"/>
+								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.1610882921" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.1620074387" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections.194760422" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.2057340378" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1390103472" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Ld/Link.ld}&quot;"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.913830613" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.239404511" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnosys.351964161" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnosys" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs.16994550" name="Other objects" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs" useByScannerDiscovery="false" valueType="userObjs"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags.1125808200" name="Linker flags (-Xlinker [option])" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags" useByScannerDiscovery="false" valueType="stringList"/>
+								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1859223768" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1947503520" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1689063433" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths.1029177148" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;../LD&quot;"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile.1751226764" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="Link.ld"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.1540675679" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1298918921" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry excluding="startup_ch32v20x_D8.S|startup_ch32v20x_D8W.S|startup_ch32v30x.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/RT-Thread/rt-thread/.project b/EVT/EXAM/RT-Thread/rt-thread/.project
index dfe4ae1..139651e 100644
--- a/EVT/EXAM/RT-Thread/rt-thread/.project
+++ b/EVT/EXAM/RT-Thread/rt-thread/.project
@@ -1,7 +1,7 @@
-<?xml version="1.0" encoding="UTF-8"?>
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <projectDescription>
 	<name>rt-thread</name>
-	<comment></comment>
+	<comment/>
 	<projects>
 	</projects>
 	<buildSpec>
@@ -43,7 +43,7 @@
 	<filteredResources>
 		<filter>
 			<id>1595986042669</id>
-			<name></name>
+			<name/>
 			<type>22</type>
 			<matcher>
 				<id>org.eclipse.ui.ide.multiFilter</id>
diff --git a/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S
index d83bc58..568cbcf 100644
--- a/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D6.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D6.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/11
 ;* Description        :  CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -99,7 +87,6 @@ _vector_base:
     .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -156,60 +143,62 @@ _vector_base:
     .weak   UART4_IRQHandler           /* UART4 */
     .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -222,7 +211,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -234,7 +223,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -243,17 +232,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested  */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x2
 	csrw 0x804, t0
-
-    /* Enable interrupt */
-   	li t0, 0x1800
-   	csrs mstatus, t0
-
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8.S
new file mode 100644
index 0000000..3536868
--- /dev/null
+++ b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8.S
@@ -0,0 +1,269 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V203RB
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   0                          /* BLE BB */
+    .word   0                          /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+TIM5_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, entry
+	csrw mepc, t0
+	mret
diff --git a/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8W.S
new file mode 100644
index 0000000..d965230
--- /dev/null
+++ b/EVT/EXAM/RT-Thread/rt-thread/Startup/startup_ch32v20x_D8W.S
@@ -0,0 +1,275 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8W.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V208x
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   BB_IRQHandler              /* BLE BB */
+    .word   LLE_IRQHandler             /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   BB_IRQHandler              /* BLE BB */
+    .weak   LLE_IRQHandler             /* BLE LLE */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+BB_IRQHandler:
+LLE_IRQHandler:
+TIM5_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, entry
+	csrw mepc, t0
+	mret
+
+
diff --git a/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c b/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c
index e7fdf15..dc3ddad 100644
--- a/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c
+++ b/EVT/EXAM/RT-Thread/rt-thread/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/RTC/RTC_Calendar/.cproject b/EVT/EXAM/RTC/RTC_Calendar/.cproject
new file mode 100644
index 0000000..93c33ac
--- /dev/null
+++ b/EVT/EXAM/RTC/RTC_Calendar/.cproject
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	
+</cproject>
diff --git a/EVT/EXAM/RTC/RTC_Calendar/.project b/EVT/EXAM/RTC/RTC_Calendar/.project
new file mode 100644
index 0000000..f8d21da
--- /dev/null
+++ b/EVT/EXAM/RTC/RTC_Calendar/.project
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<projectDescription>
+  <name>RTC_Calendar</name>
+  <comment/>
+  <projects/>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <filteredResources>
+    <filter>
+      <id>1595986042669</id>
+      <name/>
+      <type>22</type>
+      <matcher>
+        <id>org.eclipse.ui.ide.multiFilter</id>
+        <arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+      </matcher>
+    </filter>
+  </filteredResources>
+  <linkedResources>
+    <link>
+      <name>Core</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
+    </link>
+    <link>
+      <name>Debug</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
+    </link>
+    <link>
+      <name>Ld</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
+    </link>
+    <link>
+      <name>Peripheral</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
+    </link>
+    <link>
+      <name>Startup</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
+    </link>
+  </linkedResources>
+</projectDescription>
diff --git a/EVT/EXAM/RTC/RTC_Calendar/.template b/EVT/EXAM/RTC/RTC_Calendar/.template
new file mode 100644
index 0000000..7de4dfd
--- /dev/null
+++ b/EVT/EXAM/RTC/RTC_Calendar/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\RTC_Calendar.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/RTC/RTC_Calendar/RTC_Calendar.wvproj b/EVT/EXAM/RTC/RTC_Calendar/RTC_Calendar.wvproj
new file mode 100644
index 0000000..2cd99d9
--- /dev/null
+++ b/EVT/EXAM/RTC/RTC_Calendar/RTC_Calendar.wvproj
@@ -0,0 +1,2 @@
+�i�CZ	?"ǁ�r��
F<Fy8E9Y���%Pa�D�La�%�'y��]�;���S)1�1+R4><�.��ſ��?/�XO�ĿChQN$*���E
�Bk�!
2t�+buh�nUb]xl�l|
++"�<��AH42}z8p;m�u1�-�eh�Od��w��7x{5�CqEx�=;��e���2��	��*BPM�"
\ No newline at end of file
diff --git a/EVT/EXAM/RTC/User/ch32v20x_conf.h b/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_conf.h
similarity index 100%
rename from EVT/EXAM/RTC/User/ch32v20x_conf.h
rename to EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_conf.h
diff --git a/EVT/EXAM/RTC/User/ch32v20x_it.c b/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.c
similarity index 100%
rename from EVT/EXAM/RTC/User/ch32v20x_it.c
rename to EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.c
diff --git a/EVT/EXAM/RTC/User/ch32v20x_it.h b/EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.h
similarity index 100%
rename from EVT/EXAM/RTC/User/ch32v20x_it.h
rename to EVT/EXAM/RTC/RTC_Calendar/User/ch32v20x_it.h
diff --git a/EVT/EXAM/RTC/User/main.c b/EVT/EXAM/RTC/RTC_Calendar/User/main.c
similarity index 100%
rename from EVT/EXAM/RTC/User/main.c
rename to EVT/EXAM/RTC/RTC_Calendar/User/main.c
diff --git a/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c b/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c
new file mode 100644
index 0000000..8d3a568
--- /dev/null
+++ b/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.c
@@ -0,0 +1,987 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+  //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.h b/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.h
new file mode 100644
index 0000000..9c8a3f7
--- /dev/null
+++ b/EVT/EXAM/RTC/RTC_Calendar/User/system_ch32v20x.h
@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H 
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/.cproject b/EVT/EXAM/SDI_Printf/SDI_Printf/.cproject
index c19e840..23bc92b 100644
--- a/EVT/EXAM/SDI_Printf/SDI_Printf/.cproject
+++ b/EVT/EXAM/SDI_Printf/SDI_Printf/.cproject
@@ -1,142 +1,142 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+    <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+      <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+    </scannerConfigBuildInfo>
+    <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+      <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+    </scannerConfigBuildInfo>
+  </storageModule>
+  <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+  <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
 </cproject>
diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/.project b/EVT/EXAM/SDI_Printf/SDI_Printf/.project
index 9621c91..5f0f51d 100644
--- a/EVT/EXAM/SDI_Printf/SDI_Printf/.project
+++ b/EVT/EXAM/SDI_Printf/SDI_Printf/.project
@@ -1,59 +1,61 @@
-<?xml version="1.0" encoding="UTF-8"?>
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <projectDescription>
-	<name>SDI_Printf</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<triggers>full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>Core</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/SRC/Core</locationURI>
-		</link>
-		<link>
-			<name>Ld</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/SRC/Ld</locationURI>
-		</link>
-		<link>
-			<name>Peripheral</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/SRC/Peripheral</locationURI>
-		</link>
-		<link>
-			<name>Startup</name>
-			<type>2</type>
-			<locationURI>PARENT-2-PROJECT_LOC/SRC/Startup</locationURI>
-		</link>
-	</linkedResources>
-	<filteredResources>
-		<filter>
-			<id>1595986042669</id>
-			<name></name>
-			<type>22</type>
-			<matcher>
-				<id>org.eclipse.ui.ide.multiFilter</id>
-				<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
-			</matcher>
-		</filter>
-	</filteredResources>
+  <name>SDI_Printf</name>
+  <comment/>
+  <projects/>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>Core</name>
+      <type>2</type>
+      <locationURI>PARENT-2-PROJECT_LOC/SRC/Core</locationURI>
+    </link>
+    <link>
+      <name>Ld</name>
+      <type>2</type>
+      <locationURI>PARENT-2-PROJECT_LOC/SRC/Ld</locationURI>
+    </link>
+    <link>
+      <name>Peripheral</name>
+      <type>2</type>
+      <locationURI>PARENT-2-PROJECT_LOC/SRC/Peripheral</locationURI>
+    </link>
+    <link>
+      <name>Startup</name>
+      <type>2</type>
+      <locationURI>PARENT-2-PROJECT_LOC/SRC/Startup</locationURI>
+    </link>
+    <link>
+      <name>Debug</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
+    </link>
+  </linkedResources>
+  <filteredResources>
+    <filter>
+      <id>1595986042669</id>
+      <name/>
+      <type>22</type>
+      <matcher>
+        <id>org.eclipse.ui.ide.multiFilter</id>
+        <arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+      </matcher>
+    </filter>
+  </filteredResources>
 </projectDescription>
diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.c b/EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.c
deleted file mode 100644
index 311b8d4..0000000
--- a/EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
- * File Name          : debug.c
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2021/06/06
- * Description        : This file contains all the functions prototypes for UART
- *                      Printf , Delay functions.
- *********************************************************************************
- * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * Attention: This software (modified or not) and binary are used for 
- * microcontroller manufactured by Nanjing Qinheng Microelectronics.
- *******************************************************************************/
-#include "debug.h"
-
-static uint8_t  p_us = 0;
-static uint16_t p_ms = 0;
-
-#define DEBUG_DATA0_ADDRESS  ((volatile uint32_t*)0xE0000380)
-#define DEBUG_DATA1_ADDRESS  ((volatile uint32_t*)0xE0000384)
-
-/*********************************************************************
- * @fn      Delay_Init
- *
- * @brief   Initializes Delay Funcation.
- *
- * @return  none
- */
-void Delay_Init(void)
-{
-    p_us = SystemCoreClock / 8000000;
-    p_ms = (uint16_t)p_us * 1000;
-}
-
-/*********************************************************************
- * @fn      Delay_Us
- *
- * @brief   Microsecond Delay Time.
- *
- * @param   n - Microsecond number.
- *
- * @return  None
- */
-void Delay_Us(uint32_t n)
-{
-    uint32_t i;
-
-    SysTick->SR &= ~(1 << 0);
-    i = (uint32_t)n * p_us;
-
-    SysTick->CMP = i;
-    SysTick->CTLR |= (1 << 4);
-    SysTick->CTLR |= (1 << 5) | (1 << 0);
-
-    while((SysTick->SR & (1 << 0)) != (1 << 0));
-    SysTick->CTLR &= ~(1 << 0);
-}
-
-/*********************************************************************
- * @fn      Delay_Ms
- *
- * @brief   Millisecond Delay Time.
- *
- * @param   n - Millisecond number.
- *
- * @return  None
- */
-void Delay_Ms(uint32_t n)
-{
-    uint32_t i;
-
-    SysTick->SR &= ~(1 << 0);
-    i = (uint32_t)n * p_ms;
-
-    SysTick->CMP = i;
-    SysTick->CTLR |= (1 << 4);
-    SysTick->CTLR |= (1 << 5) | (1 << 0);
-
-    while((SysTick->SR & (1 << 0)) != (1 << 0));
-    SysTick->CTLR &= ~(1 << 0);
-}
-
-/*********************************************************************
- * @fn      USART_Printf_Init
- *
- * @brief   Initializes the USARTx peripheral.
- *
- * @param   baudrate - USART communication baud rate.
- *
- * @return  None
- */
-void USART_Printf_Init(uint32_t baudrate)
-{
-    GPIO_InitTypeDef  GPIO_InitStructure;
-    USART_InitTypeDef USART_InitStructure;
-
-#if(DEBUG == DEBUG_UART1)
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
-
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-    GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-#elif(DEBUG == DEBUG_UART2)
-    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
-
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-    GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-#elif(DEBUG == DEBUG_UART3)
-    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
-
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-    GPIO_Init(GPIOB, &GPIO_InitStructure);
-
-#endif
-
-    USART_InitStructure.USART_BaudRate = baudrate;
-    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-    USART_InitStructure.USART_StopBits = USART_StopBits_1;
-    USART_InitStructure.USART_Parity = USART_Parity_No;
-    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-    USART_InitStructure.USART_Mode = USART_Mode_Tx;
-
-#if(DEBUG == DEBUG_UART1)
-    USART_Init(USART1, &USART_InitStructure);
-    USART_Cmd(USART1, ENABLE);
-
-#elif(DEBUG == DEBUG_UART2)
-    USART_Init(USART2, &USART_InitStructure);
-    USART_Cmd(USART2, ENABLE);
-
-#elif(DEBUG == DEBUG_UART3)
-    USART_Init(USART3, &USART_InitStructure);
-    USART_Cmd(USART3, ENABLE);
-
-#endif
-}
-
-/*********************************************************************
- * @fn      SDI_Printf_Enable
- *
- * @brief   Initializes the SDI printf Function.
- *
- * @param   None
- *
- * @return  None
- */
-void SDI_Printf_Enable(void)
-{
-    *(DEBUG_DATA0_ADDRESS) = 0;
-    Delay_Init();
-    Delay_Ms(1);
-}
-
-/*********************************************************************
- * @fn      _write
- *
- * @brief   Support Printf Function
- *
- * @param   *buf - UART send Data.
- *          size - Data length
- *
- * @return  size: Data length
- */
-__attribute__((used))
-int _write(int fd, char *buf, int size)
-{
-    int i = 0;
-
-#if (SDI_PRINT == SDI_PR_OPEN)
-    int writeSize = size;
-
-    do
-    {
-
-        /**
-         * data0  data1 8 byte
-         * data0 The storage length of the lowest byte, with a maximum of 7 bytes.
-         */
-
-        while( (*(DEBUG_DATA0_ADDRESS) != 0u))
-        {
-
-        }
-
-        if(writeSize>7)
-        {
-            *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
-            *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
-
-            i += 7;
-            writeSize -= 7;
-        }
-        else
-        {
-            *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
-            *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
-
-            writeSize = 0;
-        }
-
-    } while (writeSize);
-
-
-#else
-    for(i = 0; i < size; i++){
-#if(DEBUG == DEBUG_UART1)
-        while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
-        USART_SendData(USART1, *buf++);
-#elif(DEBUG == DEBUG_UART2)
-        while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
-        USART_SendData(USART2, *buf++);
-#elif(DEBUG == DEBUG_UART3)
-        while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
-        USART_SendData(USART3, *buf++);
-#endif
-    }
-#endif
-    return size;
-}
-
-/*********************************************************************
- * @fn      _sbrk
- *
- * @brief   Change the spatial position of data segment.
- *
- * @return  size: Data length
- */
-__attribute__((used))
-void *_sbrk(ptrdiff_t incr)
-{
-    extern char _end[];
-    extern char _heap_end[];
-    static char *curbrk = _end;
-
-    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
-    return NULL - 1;
-
-    curbrk += incr;
-    return curbrk - incr;
-}
diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.h b/EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.h
deleted file mode 100644
index 9b40839..0000000
--- a/EVT/EXAM/SDI_Printf/SDI_Printf/Debug/debug.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
- * File Name          : debug.h
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2021/06/06
- * Description        : This file contains all the functions prototypes for UART
- *                      Printf , Delay functions.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __DEBUG_H
-#define __DEBUG_H
-
-#include "stdio.h"
-#include "ch32v20x.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* UART Printf Definition */
-#define DEBUG_UART1    1
-#define DEBUG_UART2    2
-#define DEBUG_UART3    3
-
-/* DEBUG UATR Definition */
-#ifndef DEBUG
-#define DEBUG   DEBUG_UART1
-#endif
-
-/* SDI Printf Definition */
-#define SDI_PR_CLOSE   0
-#define SDI_PR_OPEN    1
-
-#ifndef SDI_PRINT
-#define SDI_PRINT   SDI_PR_OPEN
-#endif
-
-
-void Delay_Init(void);
-void Delay_Us(uint32_t n);
-void Delay_Ms(uint32_t n);
-void USART_Printf_Init(uint32_t baudrate);
-void SDI_Printf_Enable(void);
-
-#if(DEBUG)
-  #define PRINT(format, ...)    printf(format, ##__VA_ARGS__)
-#else
-  #define PRINT(X...)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c b/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c
+++ b/EVT/EXAM/SDI_Printf/SDI_Printf/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c b/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c
+++ b/EVT/EXAM/SPI/1Lines_half-duplex/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c b/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c
+++ b/EVT/EXAM/SPI/2Lines_FullDuplex/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c b/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c
+++ b/EVT/EXAM/SPI/FullDuplex_HardNSS/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c
+++ b/EVT/EXAM/SPI/SPI_CRC/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/SPI/SPI_DMA/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c
+++ b/EVT/EXAM/SPI/SPI_FLASH/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/SPI/SPI_LCD/.cproject b/EVT/EXAM/SPI/SPI_LCD/.cproject
new file mode 100644
index 0000000..36d7ebb
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/.cproject
@@ -0,0 +1,144 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
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diff --git a/EVT/EXAM/RTC/.project b/EVT/EXAM/SPI/SPI_LCD/.project
similarity index 81%
rename from EVT/EXAM/RTC/.project
rename to EVT/EXAM/SPI/SPI_LCD/.project
index 8bcee71..13330b4 100644
--- a/EVT/EXAM/RTC/.project
+++ b/EVT/EXAM/SPI/SPI_LCD/.project
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <projectDescription>
-  <name>RTC</name>
+  <name>SPI_LCD</name>
   <comment/>
   <projects/>
   <buildSpec>
@@ -35,27 +35,27 @@
     <link>
       <name>Core</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Core</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
     </link>
     <link>
       <name>Debug</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Debug</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
     </link>
     <link>
       <name>Ld</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Ld</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
     </link>
     <link>
       <name>Peripheral</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Peripheral</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
     </link>
     <link>
       <name>Startup</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Startup</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
     </link>
   </linkedResources>
 </projectDescription>
diff --git a/EVT/EXAM/RTC/.template b/EVT/EXAM/SPI/SPI_LCD/.template
similarity index 93%
rename from EVT/EXAM/RTC/.template
rename to EVT/EXAM/SPI/SPI_LCD/.template
index cc28038..417830a 100644
--- a/EVT/EXAM/RTC/.template
+++ b/EVT/EXAM/SPI/SPI_LCD/.template
@@ -1,6 +1,6 @@
 Mcu Type=CH32V20x
 Address=0x08000000
-Target Path=obj/RTC.hex
+Target Path=obj\SPI_LCD.hex
 Erase All=true
 Program=true
 Verify=true
@@ -14,3 +14,4 @@ Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH
 
 PeripheralVersion=1.0
 MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/config.h b/EVT/EXAM/SPI/SPI_LCD/LCD/config.h
new file mode 100644
index 0000000..096b43e
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/config.h
@@ -0,0 +1,51 @@
+/*********************************************************************
+ * File Name          : config.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for Config.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* LCD Screen Definition */
+#define USE_HORIZONTAL    2
+#define LCD_W             (240u)
+#define LCD_H             (320u)
+
+/* Buffer Definition */
+#define COLOR_BYTE        (2u)
+#define FILL_BUFFER_COUNT (256u * 1u)
+#define FILL_BUFFER_SIZE  (FILL_BUFFER_COUNT * COLOR_BYTE)
+
+/* SPI Flash Speed Definition */
+#define SPI_NORMAL_MODE   1
+#define SPI_FAST_MODE     2
+#define SPI_SPEED_MODE    SPI_NORMAL_MODE
+
+/* SPI FLASH and LCD_SCREEN GPIO Definition */
+#define FLASH_CS_PORT     GPIOA
+#define FLASH_CS_RCC      RCC_APB2Periph_GPIOA
+#define FLASH_CS_PIN      (GPIO_Pin_2)
+
+#define LCD_LED_RCC       RCC_APB2Periph_GPIOB
+#define LCD_LED_PORT      GPIOB
+#define LCD_LED_PIN       (GPIO_Pin_9)
+
+#define LCD_DC_RCC        RCC_APB2Periph_GPIOB
+#define LCD_DC_PORT       GPIOB
+#define LCD_DC_PIN        (GPIO_Pin_10)
+
+#define LCD_RST_RCC       RCC_APB2Periph_GPIOB
+#define LCD_RST_PORT      GPIOB
+#define LCD_RST_PIN       (GPIO_Pin_11)
+
+#define LCD_CS_RCC        RCC_APB2Periph_GPIOB
+#define LCD_CS_PORT       GPIOB
+#define LCD_CS_PIN        (GPIO_Pin_12)
+
+#endif
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/flash.c b/EVT/EXAM/SPI/SPI_LCD/LCD/flash.c
new file mode 100644
index 0000000..f758179
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/flash.c
@@ -0,0 +1,462 @@
+/*********************************************************************
+ * File Name          : flash.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for spi flash.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "flash.h"
+#include "spi.h"
+
+static uint8_t FLASH_readWrite(uint8_t TxData)
+{
+    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET)
+        ;
+    SPI_I2S_SendData(SPI1, TxData);
+
+    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET)
+        ;
+
+    return SPI_I2S_ReceiveData(SPI1);
+}
+
+/*********************************************************************
+ * @fn      cs_pin_init
+ *
+ * @brief   gpio cs pin init
+ *
+ * @return  none
+ */
+static void cs_pin_init()
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    RCC_APB2PeriphClockCmd(FLASH_CS_RCC, ENABLE);
+    GPIO_InitStructure.GPIO_Pin   = FLASH_CS_PIN;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_Init(FLASH_CS_PORT, &GPIO_InitStructure);
+}
+
+/*********************************************************************
+ * @fn      SPI_FLASH_Init
+ *
+ * @brief   SPI FLASH Init
+ *
+ * @return  none
+ */
+void SPI_FLASH_Init(void)
+{
+    SPI1_Init();
+    SPI1_Read_DMA_Init();
+    cs_pin_init();
+    FLASH_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_ReadSR
+ *
+ * @brief   Read W25Qxx status register. 
+ *        ！！BIT7  6   5   4   3   2   1   0
+ *        ！！SPR   RV  TB  BP2 BP1 BP0 WEL BUSY
+ *
+ * @return  byte - status register value.
+ */
+uint8_t SPI_Flash_ReadSR(void)
+{
+    uint8_t byte = 0;
+
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_ReadStatusReg);
+    byte = FLASH_readWrite(0Xff);
+    FLASH_CS_SET;
+
+    return byte;
+}
+
+/*********************************************************************
+ * @fn      SPI_FLASH_Write_SR
+ *
+ * @brief   Write W25Qxx status register.
+ *
+ * @param   sr - status register value.
+ *
+ * @return  none
+ */
+void SPI_FLASH_Write_SR(uint8_t sr)
+{
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_WriteStatusReg);
+    FLASH_readWrite(sr);
+    FLASH_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Wait_Busy
+ *
+ * @brief   Wait flash free.
+ *
+ * @return  none
+ */
+void SPI_Flash_Wait_Busy(void)
+{
+    while ((SPI_Flash_ReadSR() & 0x01) == 0x01)
+        ;
+}
+
+/*********************************************************************
+ * @fn      SPI_FLASH_Write_Enable
+ *
+ * @brief   Enable flash write.
+ *
+ * @return  none
+ */
+void SPI_FLASH_Write_Enable(void)
+{
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_WriteEnable);
+    FLASH_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      SPI_FLASH_Write_Disable
+ *
+ * @brief   Disable flash write.
+ *
+ * @return  none
+ */
+void SPI_FLASH_Write_Disable(void)
+{
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_WriteDisable);
+    FLASH_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_ReadID
+ *
+ * @brief   Read flash ID.
+ *
+ * @return  Temp - FLASH ID.
+ */
+uint16_t SPI_Flash_ReadID(void)
+{
+    uint16_t Temp = 0;
+
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_ManufactDeviceID);
+    FLASH_readWrite(0x00);
+    FLASH_readWrite(0x00);
+    FLASH_readWrite(0x00);
+    Temp |= FLASH_readWrite(0xFF) << 8;
+    Temp |= FLASH_readWrite(0xFF);
+    FLASH_CS_SET;
+
+    return Temp;
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_ReadJedecDeviceID
+ *
+ * @brief   Read JedecDevice ID.
+ *
+ * @return  JedecDevice ID.
+ */
+uint32_t SPI_Flash_ReadJedecDeviceID(void)
+{
+    uint32_t Temp = 0;
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_JedecDeviceID);
+    Temp |= FLASH_readWrite(0xFF) << 16;
+    Temp |= FLASH_readWrite(0xFF) << 8;
+    Temp |= FLASH_readWrite(0xFF);
+    FLASH_CS_SET;
+    return Temp;
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Erase_Sector
+ *
+ * @brief   Erase one sector(4Kbyte).
+ *
+ * @param   Dst_Addr - 0 ！！ 2047
+ *
+ * @return  none
+ */
+void SPI_Flash_Erase_Sector(uint32_t Dst_Addr)
+{
+    Dst_Addr *= 4096;
+    SPI_FLASH_Write_Enable();
+    SPI_Flash_Wait_Busy();
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_SectorErase);
+    FLASH_readWrite((uint8_t)((Dst_Addr) >> 16));
+    FLASH_readWrite((uint8_t)((Dst_Addr) >> 8));
+    FLASH_readWrite((uint8_t)Dst_Addr);
+    FLASH_CS_SET;
+    SPI_Flash_Wait_Busy();
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Read
+ *
+ * @brief   Read data from flash.
+ *
+ * @param   pBuffer -
+ *          ReadAddr -Initial address(24bit).
+ *          size - Data length.
+ *
+ * @return  none
+ */
+void SPI_Flash_Read(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t size)
+{
+    uint16_t i;
+
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_ReadData);
+    FLASH_readWrite((uint8_t)((ReadAddr) >> 16));
+    FLASH_readWrite((uint8_t)((ReadAddr) >> 8));
+    FLASH_readWrite((uint8_t)ReadAddr);
+
+    for (i = 0; i < size; i++)
+    {
+        pBuffer[i] = FLASH_readWrite(0XFF);
+    }
+
+    FLASH_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Write_Page
+ *
+ * @brief   Write data by one page.
+ *
+ * @param   pBuffer -
+ *          WriteAddr - Initial address(24bit).
+ *          size - Data length.
+ *
+ * @return  none
+ */
+void SPI_Flash_Write_Page(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size)
+{
+    uint16_t i;
+
+    SPI_FLASH_Write_Enable();
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_PageProgram);
+    FLASH_readWrite((uint8_t)((WriteAddr) >> 16));
+    FLASH_readWrite((uint8_t)((WriteAddr) >> 8));
+    FLASH_readWrite((uint8_t)WriteAddr);
+
+    for (i = 0; i < size; i++)
+    {
+        FLASH_readWrite(pBuffer[i]);
+    }
+
+    FLASH_CS_SET;
+    SPI_Flash_Wait_Busy();
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Write_NoCheck
+ *
+ * @brief   Write data to flash.(need Erase)
+ *          All data in address rang is 0xFF.
+ *
+ * @param   pBuffer -
+ *          WriteAddr - Initial address(24bit).
+ *          size - Data length.
+ *
+ * @return  none
+ */
+void SPI_Flash_Write_NoCheck(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size)
+{
+    uint16_t pageremain;
+
+    pageremain = 256 - WriteAddr % 256;
+
+    if (size <= pageremain)
+        pageremain = size;
+
+    while (1)
+    {
+        SPI_Flash_Write_Page(pBuffer, WriteAddr, pageremain);
+
+        if (size == pageremain)
+        {
+            break;
+        }
+        else
+        {
+            pBuffer += pageremain;
+            WriteAddr += pageremain;
+            size -= pageremain;
+
+            if (size > 256)
+                pageremain = 256;
+            else
+                pageremain = size;
+        }
+    }
+}
+
+static uint8_t W25QXX_BUFFER[4096];
+/*********************************************************************
+ * @fn      SPI_Flash_Write
+ *
+ * @brief   Write data to flash.(no need Erase)
+ *
+ * @param   pBuffer -
+ *          WriteAddr - Initial address(24bit).
+ *          size - Data length.
+ *
+ * @return  none
+ */
+void SPI_Flash_Write(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size)
+{
+    uint32_t secpos;
+    uint16_t secoff;
+    uint16_t secremain;
+    uint16_t i;
+
+    secpos    = WriteAddr / 4096;
+    secoff    = WriteAddr % 4096;
+    secremain = 4096 - secoff;
+
+    if (size <= secremain)
+        secremain = size;
+
+    while (1)
+    {
+        SPI_Flash_Read(W25QXX_BUFFER, secpos * 4096, 4096);
+
+        for (i = 0; i < secremain; i++)
+        {
+            if (W25QXX_BUFFER[secoff + i] != 0XFF)
+                break;
+        }
+
+        if (i < secremain)
+        {
+            SPI_Flash_Erase_Sector(secpos);
+
+            for (i = 0; i < secremain; i++)
+            {
+                W25QXX_BUFFER[i + secoff] = pBuffer[i];
+            }
+
+            SPI_Flash_Write_NoCheck(W25QXX_BUFFER, secpos * 4096, 4096);
+        }
+        else
+        {
+            SPI_Flash_Write_NoCheck(pBuffer, WriteAddr, secremain);
+        }
+
+        if (size == secremain)
+        {
+            break;
+        }
+        else
+        {
+            secpos++;
+            secoff = 0;
+
+            pBuffer += secremain;
+            WriteAddr += secremain;
+            size -= secremain;
+
+            if (size > 4096)
+            {
+                secremain = 4096;
+            }
+            else
+            {
+                secremain = size;
+            }
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Erase_Chip
+ *
+ * @brief   Erase all FLASH pages.
+ *
+ *
+ * @return  none
+ */
+void SPI_Flash_Erase_Chip(void)
+{
+    SPI_FLASH_Write_Enable();
+    SPI_Flash_Wait_Busy();
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_ChipErase);
+    FLASH_CS_SET;
+    SPI_Flash_Wait_Busy();
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_PowerDown
+ *
+ * @brief   Enter power down mode.
+ *
+ * @return  none
+ */
+void SPI_Flash_PowerDown(void)
+{
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_PowerDown);
+    FLASH_CS_SET;
+    Delay_Us(3);
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_WAKEUP
+ *
+ * @brief   Power down wake up.
+ *
+ * @return  none
+ */
+void SPI_Flash_WAKEUP(void)
+{
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_ReleasePowerDown);
+    FLASH_CS_SET;
+    Delay_Us(3);
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Read_dma_start
+ *
+ * @brief   enable spi dma and set read address
+ *   
+ * @param    ReadAddr - the address in spi flash
+ *
+ * @return  none
+ */
+void SPI_Flash_Read_dma_start(uint32_t ReadAddr)
+{
+    FLASH_CS_CLR;
+    FLASH_readWrite(W25X_FastReadData);
+    FLASH_readWrite((uint8_t)((ReadAddr) >> 16));
+    FLASH_readWrite((uint8_t)((ReadAddr) >> 8));
+    FLASH_readWrite((uint8_t)ReadAddr);
+    FLASH_readWrite(0xFF);
+    SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
+}
+
+/*********************************************************************
+ * @fn      SPI_Flash_Read_dma_end
+ *
+ * @brief   disable spi dma
+ *
+ * @return  none
+ */
+void SPI_Flash_Read_dma_end(void)
+{
+    FLASH_CS_SET;
+    SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, DISABLE);
+}
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/flash.h b/EVT/EXAM/SPI/SPI_LCD/LCD/flash.h
new file mode 100644
index 0000000..9bc606c
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/flash.h
@@ -0,0 +1,57 @@
+/*********************************************************************
+ * File Name          : flash.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for spi flash.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SPI_FLASH_H
+#define __SPI_FLASH_H
+#include "debug.h"
+#include "spi.h"
+#include "config.h"
+
+#define W25X_WriteEnable      0x06
+#define W25X_WriteDisable     0x04
+#define W25X_ReadStatusReg    0x05
+#define W25X_WriteStatusReg   0x01
+#define W25X_ReadData         0x03
+#define W25X_FastReadData     0x0B
+#define W25X_FastReadDual     0x3B
+#define W25X_PageProgram      0x02
+#define W25X_BlockErase       0xD8
+#define W25X_SectorErase      0x20
+#define W25X_ChipErase        0xC7
+#define W25X_PowerDown        0xB9
+#define W25X_ReleasePowerDown 0xAB
+#define W25X_DeviceID         0xAB
+#define W25X_ManufactDeviceID 0x90
+#define W25X_JedecDeviceID    0x9F
+
+#define FLASH_CS_SET          (FLASH_CS_PORT->BSHR = FLASH_CS_PIN)
+#define FLASH_CS_CLR          (FLASH_CS_PORT->BCR = FLASH_CS_PIN)
+
+void SPI_FLASH_Init(void);
+uint8_t SPI_Flash_ReadSR(void);
+void SPI_FLASH_Write_SR(uint8_t sr);
+void SPI_Flash_Wait_Busy(void);
+void SPI_FLASH_Write_Enable(void);
+void SPI_FLASH_Write_Disable(void);
+uint16_t SPI_Flash_ReadID(void);
+uint32_t SPI_Flash_ReadJedecDeviceID(void);
+void SPI_Flash_Erase_Sector(uint32_t Dst_Addr);
+void SPI_Flash_Read(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t size);
+void SPI_Flash_Write_Page(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
+void SPI_Flash_Write_NoCheck(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
+void SPI_Flash_Write(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
+void SPI_Flash_Erase_Chip(void);
+void SPI_Flash_PowerDown(void);
+void SPI_Flash_WAKEUP(void);
+void SPI_Flash_Read_dma_start(uint32_t ReadAddr);
+void SPI_Flash_Read_dma_end(void);
+
+#endif
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/lcd.c b/EVT/EXAM/SPI/SPI_LCD/LCD/lcd.c
new file mode 100644
index 0000000..0185b5e
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/lcd.c
@@ -0,0 +1,407 @@
+/*********************************************************************
+ * File Name          : lcd.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for lcd screen.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#include "lcd.h"
+#include "debug.h"
+
+static uint16_t width;
+static uint16_t height;
+
+#define LCD_SOFT_RESET          (0x01)
+#define LCD_READ_ID             (0x04)
+#define LCD_READ_DISPLAY_STATUS (0x09)
+#define LCD_ON                  (0x28)
+#define LCD_OFF                 (0x29)
+
+#define LCD_SET_X               (0x2a)
+#define LCD_SET_Y               (0x2B)
+#define LCD_MEM_WRITE           (0x2C)
+#define LCD_MEM_READ            (0x2e)
+
+static uint16_t color_buffer[2][FILL_BUFFER_COUNT] = {0};
+
+/*********************************************************************
+ * @fn      LCD_WR_REG
+ *
+ * @brief   Write an 8-bit command to the LCD screen
+ * 
+ * @param   data - Command value to be written
+ *
+ * @return  none
+ */
+static void LCD_WR_REG(uint8_t data)
+{
+    LCD_CS_CLR;
+    LCD_DC_CLR;
+    SPI2_Write(data);
+    LCD_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      LCD_WR_DATA
+ *
+ * @brief   Write an 8-bit data to the LCD screen
+ * 
+ * @param   data - the data to write
+ * 
+ */
+static void LCD_WR_DATA(uint8_t data)
+{
+    LCD_CS_CLR;
+    LCD_DC_SET;
+    SPI2_Write(data);
+    LCD_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      LCD_WriteReg
+ * 
+ * @brief   write a data to the register
+ * 
+ * @param   LCD_Reg - register address
+ *          LCD_RegValue - the data to write
+ * 
+ * @return  none
+ */
+static void LCD_WriteReg(uint8_t LCD_Reg, uint8_t LCD_RegValue)
+{
+    LCD_WR_REG(LCD_Reg);
+    LCD_WR_DATA(LCD_RegValue);
+}
+
+/*********************************************************************
+ * @fn      Lcd_WriteData_16Bit
+ * 
+ * @brief   write two bytes to the lcd screen
+ * 
+ * @param   Data - the data to write
+ * 
+ * @return  none
+ */
+void Lcd_WriteData_16Bit(uint16_t Data)
+{
+    LCD_CS_CLR;
+    LCD_DC_SET;
+    SPI2_Write(Data >> 8);
+    SPI2_Write(Data);
+    LCD_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      LCD_GPIOInit
+ * 
+ * @brief   Configuring the control gpio for the lcd screen
+ * 
+ * @return  none
+ */
+void LCD_GPIOInit(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    RCC_APB2PeriphClockCmd(LCD_LED_RCC, ENABLE);
+    RCC_APB2PeriphClockCmd(LCD_DC_RCC, ENABLE);
+    RCC_APB2PeriphClockCmd(LCD_RST_RCC, ENABLE);
+    RCC_APB2PeriphClockCmd(LCD_CS_RCC, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin   = LCD_LED_PIN;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_Init(LCD_LED_PORT, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin   = LCD_DC_PIN;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_Init(LCD_DC_PORT, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin   = LCD_RST_PIN;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_Init(LCD_RST_PORT, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin   = LCD_CS_PIN;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_Init(LCD_CS_PORT, &GPIO_InitStructure);
+}
+
+/*********************************************************************
+ * @fn      LCD_RESET
+ * 
+ * @brief   reset the lcd screen by the rst pin
+ * 
+ * @return  none
+ */
+void LCD_RESET(void)
+{
+    LCD_RST_CLR;
+    Delay_Ms(100);
+    LCD_RST_SET;
+    Delay_Ms(50);
+}
+
+/*********************************************************************
+ * @fn      LCD_Init
+ * 
+ * @brief   Initialization LCD screen
+ * 
+ * @return  none
+ */
+void LCD_Init(void)
+{
+    SPI2_Init();
+    SPI2_DMA_Init();
+    LCD_GPIOInit();
+    LCD_RESET();
+    LCD_LED_SET;
+
+    LCD_WR_REG(0xCF);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0xC9);  //C1
+    LCD_WR_DATA(0X30);
+    LCD_WR_REG(0xED);
+    LCD_WR_DATA(0x64);
+    LCD_WR_DATA(0x03);
+    LCD_WR_DATA(0X12);
+    LCD_WR_DATA(0X81);
+    LCD_WR_REG(0xE8);
+    LCD_WR_DATA(0x85);
+    LCD_WR_DATA(0x10);
+    LCD_WR_DATA(0x7A);
+    LCD_WR_REG(0xCB);
+    LCD_WR_DATA(0x39);
+    LCD_WR_DATA(0x2C);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x34);
+    LCD_WR_DATA(0x02);
+    LCD_WR_REG(0xF7);
+    LCD_WR_DATA(0x20);
+    LCD_WR_REG(0xEA);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_REG(0xC0);   //Power control
+    LCD_WR_DATA(0x1B);  //VRH[5:0]
+    LCD_WR_REG(0xC1);   //Power control
+    LCD_WR_DATA(0x00);  //SAP[2:0];BT[3:0] 01
+    LCD_WR_REG(0xC5);   //VCM control
+    LCD_WR_DATA(0x30);  //3F
+    LCD_WR_DATA(0x30);  //3C
+    LCD_WR_REG(0xC7);   //VCM control2
+    LCD_WR_DATA(0XB7);
+    LCD_WR_REG(0x36);  // Memory Access Control
+    LCD_WR_DATA(0x08);
+    LCD_WR_REG(0x3A);
+    LCD_WR_DATA(0x55);
+    LCD_WR_REG(0xB1);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x1A);
+    LCD_WR_REG(0xB6);  // Display Function Control
+    LCD_WR_DATA(0x0A);
+    LCD_WR_DATA(0xA2);
+    LCD_WR_REG(0xF2);  // 3Gamma Function Disable
+    LCD_WR_DATA(0x00);
+    LCD_WR_REG(0x26);  //Gamma curve selected
+    LCD_WR_DATA(0x01);
+    LCD_WR_REG(0xE0);  //Set Gamma
+    LCD_WR_DATA(0x0F);
+    LCD_WR_DATA(0x2A);
+    LCD_WR_DATA(0x28);
+    LCD_WR_DATA(0x08);
+    LCD_WR_DATA(0x0E);
+    LCD_WR_DATA(0x08);
+    LCD_WR_DATA(0x54);
+    LCD_WR_DATA(0XA9);
+    LCD_WR_DATA(0x43);
+    LCD_WR_DATA(0x0A);
+    LCD_WR_DATA(0x0F);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_REG(0XE1);  //Set Gamma
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x15);
+    LCD_WR_DATA(0x17);
+    LCD_WR_DATA(0x07);
+    LCD_WR_DATA(0x11);
+    LCD_WR_DATA(0x06);
+    LCD_WR_DATA(0x2B);
+    LCD_WR_DATA(0x56);
+    LCD_WR_DATA(0x3C);
+    LCD_WR_DATA(0x05);
+    LCD_WR_DATA(0x10);
+    LCD_WR_DATA(0x0F);
+    LCD_WR_DATA(0x3F);
+    LCD_WR_DATA(0x3F);
+    LCD_WR_DATA(0x0F);
+    LCD_WR_REG(0x2B);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x01);
+    LCD_WR_DATA(0x3f);
+    LCD_WR_REG(0x2A);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0x00);
+    LCD_WR_DATA(0xef);
+    LCD_WR_REG(0x11);  //Exit Sleep
+    Delay_Ms(120);
+    LCD_WR_REG(0x29);  //display on
+
+    LCD_direction(USE_HORIZONTAL);  
+}
+
+/*********************************************************************
+ * @fn      LCD_SetWindows
+ * 
+ * @brief   Setting LCD display window
+ * 
+ * @param   xStar -  the bebinning x coordinate of the LCD display window
+ *          yStar -  the bebinning y coordinate of the LCD display window
+ *          xEnd -  the endning x coordinate of the LCD display window
+ *          yEnd -  the endning y coordinate of the LCD display window
+ * 
+ * @return  none
+ */
+void LCD_SetWindows(uint16_t xStar, uint16_t yStar, uint16_t xEnd, uint16_t yEnd)
+{
+    LCD_WR_REG(LCD_SET_X);
+    LCD_WR_DATA(xStar >> 8);
+    LCD_WR_DATA(0x00FF & xStar);
+    LCD_WR_DATA(xEnd >> 8);
+    LCD_WR_DATA(0x00FF & xEnd);
+
+    LCD_WR_REG(LCD_SET_Y);
+    LCD_WR_DATA(yStar >> 8);
+    LCD_WR_DATA(0x00FF & yStar);
+    LCD_WR_DATA(yEnd >> 8);
+    LCD_WR_DATA(0x00FF & yEnd);
+    LCD_WR_REG(LCD_MEM_WRITE);  
+}
+
+/*********************************************************************
+ * @fn      LCD_direction
+ * 
+ * @brief   Setting the display direction of LCD screen
+ * 
+ * @param   direction -   direction:0-0 degree  1-90 degree  2-180 degree  3-270 degree
+ * 
+ * @return  none
+ */
+void LCD_direction(uint8_t direction)
+{
+    switch (direction)
+    {
+        case 0:
+            width  = LCD_W;
+            height = LCD_H;
+            LCD_WriteReg(0x36, (1 << 3) | (0 << 6) | (0 << 7));  //BGR==1,MY==0,MX==0,MV==0
+            break;
+        case 1:
+            width  = LCD_H;
+            height = LCD_W;
+            LCD_WriteReg(0x36, (1 << 3) | (0 << 7) | (1 << 6) | (1 << 5));  //BGR==1,MY==1,MX==0,MV==1
+            break;
+        case 2:
+            width  = LCD_W;
+            height = LCD_H;
+            LCD_WriteReg(0x36, (1 << 3) | (1 << 6) | (1 << 7));  //BGR==1,MY==0,MX==0,MV==0
+            break;
+        case 3:
+            width  = LCD_H;
+            height = LCD_W;
+            LCD_WriteReg(0x36, (1 << 3) | (1 << 7) | (1 << 5));  //BGR==1,MY==1,MX==0,MV==1
+            break;
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      LCD_Clear
+ * 
+ * @brief   Full screen filled LCD screen
+ * 
+ * @param   Color -   Filled color
+ * 
+ * @return  none
+ */
+void LCD_Clear(uint16_t Color)
+{
+    unsigned int i, m;
+    LCD_SetWindows(0, 0, width - 1, height - 1);
+    LCD_CS_CLR;
+    LCD_DC_SET;
+    for (i = 0; i < height; i++)
+    {
+        for (m = 0; m < width; m++)
+        {
+            Lcd_WriteData_16Bit(Color);
+        }
+    }
+    LCD_CS_SET;
+}
+
+/*********************************************************************
+ * @fn      LCD_drawImageWithSize
+ * 
+ * @brief   read image from SPI Flash and display on the LCD screen
+ * 
+ * @param   x -  the x coordinate of the LCD screen
+ *          y - the y coordinate of the LCD screen
+ *          width -  the image width
+ *          height - the image height
+ *          addr - the image address in SPI flash
+ * 
+ * @return  none
+ */
+void LCD_drawImageWithSize(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint32_t addr)
+{
+    uint32_t m  = 0;
+    uint16_t x2 = (x + width) - 1;
+    uint16_t y2 = (y + height) - 1;
+    LCD_WR_REG(LCD_SET_X);
+    LCD_WR_DATA(x >> 8);
+    LCD_WR_DATA(0x00FF & x);
+    LCD_WR_DATA(x2 >> 8);
+    LCD_WR_DATA(0x00FF & x2);
+
+    LCD_WR_REG(LCD_SET_Y);
+    LCD_WR_DATA(y >> 8);
+    LCD_WR_DATA(0x00FF & y);
+    LCD_WR_DATA(y2 >> 8);
+    LCD_WR_DATA(0x00FF & y2);
+
+    LCD_WR_REG(LCD_MEM_WRITE);
+    LCD_CS_CLR;
+    LCD_DC_SET;
+
+    uint32_t count = width * height;
+
+    uint32_t fill_count = count / FILL_BUFFER_COUNT;
+    uint32_t else_count = count % FILL_BUFFER_COUNT;
+    SPI_Flash_Read_dma_start(addr);
+
+    SPI1_Read_DMA((uint8_t *)color_buffer[m], FILL_BUFFER_SIZE);
+
+    while (fill_count > 0)
+    {
+        while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET)
+            ;
+        fill_count--;
+        SPI2_Write_DMA((uint8_t *)color_buffer[m], FILL_BUFFER_SIZE);
+        m = !m;
+        SPI1_Read_DMA((uint8_t *)color_buffer[m], FILL_BUFFER_SIZE);
+    }
+    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET)
+        ;
+    SPI2_Write_DMA((uint8_t *)color_buffer[m], else_count * COLOR_BYTE);
+    SPI_Flash_Read_dma_end();
+}
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/lcd.h b/EVT/EXAM/SPI/SPI_LCD/LCD/lcd.h
new file mode 100644
index 0000000..588eb69
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/lcd.h
@@ -0,0 +1,57 @@
+/*********************************************************************
+ * File Name          : lcd.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for lcd screen.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+#ifndef __LCD_H
+#define __LCD_H
+#include "spi.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "flash.h"
+#include "config.h"
+
+// [15:11] 5bit red
+//  [10:5] 6bit green
+//   [4:0] 5bit blue
+#define LCD_WHITE    0xFFFF
+#define LCD_BLACK    0x0000
+#define LCD_BLUE     0x001F
+#define LCD_BRED     0XF81F
+#define LCD_GRED     0XFFE0
+#define LCD_GBLUE    0X07FF
+#define LCD_RED      0xF800
+#define LCD_MAGENTA  0xF81F
+#define LCD_GREEN    0x07E0
+#define LCD_CYAN     0x7FFF
+#define LCD_YELLOW   0xFFE0
+#define LCD_BROWN    0XBC40
+#define LCD_BRRED    0XFC07
+#define LCD_GRAY     0X8430
+
+#define LCD_LED_SET  (LCD_LED_PORT->BSHR = LCD_LED_PIN)
+#define LCD_CS_SET   (LCD_CS_PORT->BSHR = LCD_CS_PIN)
+#define LCD_DC_SET   (LCD_DC_PORT->BSHR = LCD_DC_PIN)
+#define LCD_RST_SET  (LCD_RST_PORT->BSHR = LCD_RST_PIN)
+
+#define LCD_LED_CLR  (LCD_LED_PORT->BCR = LCD_LED_PIN)
+#define LCD_CS_CLR   (LCD_CS_PORT->BCR = LCD_CS_PIN)
+#define LCD_DC_CLR   (LCD_DC_PORT->BCR = LCD_DC_PIN)
+#define LCD_RST_CLR  (LCD_RST_PORT->BCR = LCD_RST_PIN)
+
+void LCD_Init(void);
+void LCD_Clear(uint16_t Color);
+
+void Lcd_WriteData_16Bit(uint16_t Data);
+void LCD_direction(uint8_t direction);
+void LCD_SetWindows(uint16_t xStar, uint16_t yStar, uint16_t xEnd, uint16_t yEnd);
+
+void LCD_drawImageWithSize(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint32_t addr);
+#endif
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/spi.c b/EVT/EXAM/SPI/SPI_LCD/LCD/spi.c
new file mode 100644
index 0000000..1e94bde
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/spi.c
@@ -0,0 +1,253 @@
+/*********************************************************************
+ * File Name          : spi.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for spi.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "spi.h"
+
+/*********************************************************************
+ * @fn      SPI1_Init
+ * 
+ * @brief   Initialize SPI1 
+ * 
+ * @return  none
+ */
+void SPI1_Init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+    SPI_InitTypeDef  SPI_InitStructure  = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_5;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_6;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_7;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+    SPI_InitStructure.SPI_Mode      = SPI_Mode_Master;
+    SPI_InitStructure.SPI_DataSize  = SPI_DataSize_8b;
+    SPI_InitStructure.SPI_CPOL      = SPI_CPOL_Low;
+    SPI_InitStructure.SPI_CPHA      = SPI_CPHA_1Edge;
+    SPI_InitStructure.SPI_NSS       = SPI_NSS_Soft;
+#if SPI_SPEED_MODE == SPI_FAST_MODE
+    SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+#else
+    SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
+#endif
+
+    SPI_InitStructure.SPI_FirstBit      = SPI_FirstBit_MSB;
+    SPI_InitStructure.SPI_CRCPolynomial = 7;
+    SPI_Init(SPI1, &SPI_InitStructure);
+
+    SPI_Cmd(SPI1, ENABLE);
+
+#if SPI_SPEED_MODE == SPI_FAST_MODE
+    SPI1->HSCR = 1;
+#endif
+}
+
+/*********************************************************************
+ * @fn      SPI1_Read_DMA_Init
+ * 
+ * @brief   Initialize DMA for SPI1, In this condition every time send 0XFF to read data
+ * 
+ * @return  none
+ */
+void SPI1_Read_DMA_Init()
+{
+    static uint32_t DummyByte         = 0xff;
+    DMA_InitTypeDef DMA_InitStructure = {0};
+
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    // Tx
+    DMA_DeInit(SPI1_DMA_TX_CH);
+
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DATAR;
+    DMA_InitStructure.DMA_MemoryBaseAddr     = (uint32_t)&DummyByte;
+    DMA_InitStructure.DMA_DIR                = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize         = 0;
+    DMA_InitStructure.DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc          = DMA_MemoryInc_Disable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
+    DMA_InitStructure.DMA_Mode               = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority           = DMA_Priority_High;
+    DMA_InitStructure.DMA_M2M                = DMA_M2M_Disable;
+    DMA_Init(SPI1_DMA_TX_CH, &DMA_InitStructure);
+
+    // Rx
+    DMA_DeInit(SPI1_DMA_RX_CH);
+
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DATAR;
+    DMA_InitStructure.DMA_MemoryBaseAddr     = (uint32_t)NULL;
+    DMA_InitStructure.DMA_DIR                = DMA_DIR_PeripheralSRC;
+    DMA_InitStructure.DMA_BufferSize         = 0;
+    DMA_InitStructure.DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc          = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
+    DMA_InitStructure.DMA_Mode               = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority           = DMA_Priority_High;
+    DMA_InitStructure.DMA_M2M                = DMA_M2M_Disable;
+    DMA_Init(SPI1_DMA_RX_CH, &DMA_InitStructure);
+}
+
+/*********************************************************************
+ * @fn      SPI1_Read_DMA
+ * 
+ * @brief   read data from SPI1 via DMA
+ * 
+ * @param   data -  the data to recive
+ *          len -  read length
+ * 
+ * @return  none
+ */
+void SPI1_Read_DMA(uint8_t *data, uint16_t len)
+{
+    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET)
+        ;
+    DMA_Cmd(SPI1_DMA_TX_CH, DISABLE);
+    DMA_Cmd(SPI1_DMA_RX_CH, DISABLE);
+    DMA_ClearFlag(DMA1_FLAG_TC3);
+    DMA_ClearFlag(DMA1_FLAG_TC3);
+    SPI1_DMA_TX_CH->CNTR = len;
+
+    SPI1_DMA_RX_CH->MADDR = (uint32_t)data;
+    SPI1_DMA_RX_CH->CNTR  = len;
+
+    DMA_Cmd(SPI1_DMA_TX_CH, ENABLE);
+    DMA_Cmd(SPI1_DMA_RX_CH, ENABLE);
+}
+
+/*********************************************************************
+ * @fn      SPI2_Init
+ * 
+ * @brief   Initialize SPI2
+ * 
+ * @return  none
+ */
+void SPI2_Init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+    SPI_InitTypeDef  SPI_InitStructure  = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_13;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_14;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_15;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+    SPI_InitStructure.SPI_Direction         = SPI_Direction_1Line_Tx;
+    SPI_InitStructure.SPI_Mode              = SPI_Mode_Master;
+    SPI_InitStructure.SPI_DataSize          = SPI_DataSize_8b;
+    SPI_InitStructure.SPI_CPOL              = SPI_CPOL_Low;
+    SPI_InitStructure.SPI_CPHA              = SPI_CPHA_1Edge;
+    SPI_InitStructure.SPI_NSS               = SPI_NSS_Soft;
+    SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    SPI_InitStructure.SPI_FirstBit          = SPI_FirstBit_MSB;
+    SPI_InitStructure.SPI_CRCPolynomial     = 7;
+    SPI_Init(SPI2, &SPI_InitStructure);
+
+    SPI_Cmd(SPI2, ENABLE);
+}
+
+/*********************************************************************
+ * @fn      SPI2_DMA_Init
+ * 
+ * @brief   Initialize DMA for SPI2
+ * 
+ * @return  none
+ */
+void SPI2_DMA_Init()
+{
+    DMA_InitTypeDef DMA_InitStructure = {0};
+
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    DMA_DeInit(SPI2_DMA_TX_CH);
+
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DATAR;
+    DMA_InitStructure.DMA_MemoryBaseAddr     = (uint32_t)NULL;
+    DMA_InitStructure.DMA_DIR                = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize         = 0;
+    DMA_InitStructure.DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc          = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
+    DMA_InitStructure.DMA_Mode               = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority           = DMA_Priority_High;
+    DMA_InitStructure.DMA_M2M                = DMA_M2M_Disable;
+    DMA_Init(SPI2_DMA_TX_CH, &DMA_InitStructure);
+
+    SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
+}
+
+/*********************************************************************
+ * @fn      SPI2_Write
+ * 
+ * @brief   send one byte
+ * 
+ * @param   data -  the data to send
+ * 
+ * @return  none
+ */
+void SPI2_Write(uint8_t data)
+{
+    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET)
+        ;
+    SPI_I2S_SendData(SPI2, data);
+
+    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET)
+        ;
+}
+
+/*********************************************************************
+ * @fn      SPI2_Write_DMA
+ * 
+ * @brief   send a lot of data 
+ * 
+ * @param   data -  the data to be send 
+ *          len -  the length of data
+ * 
+ * @return  none
+ */
+void SPI2_Write_DMA(uint8_t *data, uint16_t len)
+{
+    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET)
+        ;
+
+    DMA_Cmd(SPI2_DMA_TX_CH, DISABLE);
+    DMA_ClearFlag(SPI2_DMA_TC_FLAG);
+    SPI2_DMA_TX_CH->MADDR = (uint32_t)data;
+    SPI2_DMA_TX_CH->CNTR  = len;
+
+    DMA_Cmd(SPI2_DMA_TX_CH, ENABLE);
+}
diff --git a/EVT/EXAM/SPI/SPI_LCD/LCD/spi.h b/EVT/EXAM/SPI/SPI_LCD/LCD/spi.h
new file mode 100644
index 0000000..1d2923b
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/LCD/spi.h
@@ -0,0 +1,39 @@
+/*********************************************************************
+ * File Name          : spi.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : file for spi.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#include "debug.h"
+#include "config.h"
+
+#define SPI1_DMA_RX_CH   DMA1_Channel2
+#define SPI1_DMA_TX_CH   DMA1_Channel3
+
+#define SPI1_DMA_TC_FLAG DMA1_FLAG_TC3
+#define SPI1_DMA_RC_FLAG DMA1_FLAG_TC2
+
+#define SPI2_DMA_RX_CH   DMA1_Channel4
+#define SPI2_DMA_TX_CH   DMA1_Channel5
+
+#define SPI2_DMA_TC_FLAG DMA1_FLAG_TC5
+#define SPI2_DMA_RC_FLAG DMA1_FLAG_TC4
+
+void SPI1_Init(void);
+void SPI1_Read_DMA_Init(void);
+void SPI1_Read_DMA(uint8_t *data, uint16_t len);
+
+void SPI2_Init(void);
+void SPI2_DMA_Init(void);
+void SPI2_Write(uint8_t data);
+void SPI2_Write_DMA(uint8_t *data, uint16_t len);
+
+#endif
diff --git a/EVT/EXAM/SPI/SPI_LCD/SPI_LCD.wvproj b/EVT/EXAM/SPI/SPI_LCD/SPI_LCD.wvproj
new file mode 100644
index 0000000..2cd99d9
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/SPI_LCD.wvproj
@@ -0,0 +1,2 @@
+�i�CZ	?"ǁ�r��
F<Fy8E9Y���%Pa�D�La�%�'y��]�;���S)1�1+R4><�.��ſ��?/�XO�ĿChQN$*���E
�Bk�!
2t�+buh�nUb]xl�l|
++"�<��AH42}z8p;m�u1�-�eh�Od��w��7x{5�CqEx�=;��e���2��	��*BPM�"
\ No newline at end of file
diff --git a/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_conf.h b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_conf.h
new file mode 100644
index 0000000..d1eeb38
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_conf.h
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+	
+	
+	
diff --git a/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c
new file mode 100644
index 0000000..94d1872
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.c
@@ -0,0 +1,40 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main Interrupt Service Routines.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
diff --git a/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.h b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.h
new file mode 100644
index 0000000..f68b203
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/User/ch32v20x_it.h
@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/EVT/EXAM/SPI/SPI_LCD/User/main.c b/EVT/EXAM/SPI/SPI_LCD/User/main.c
new file mode 100644
index 0000000..eafda1f
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/User/main.c
@@ -0,0 +1,80 @@
+/*********************************************************************
+ * File Name          : main.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2023/8/15
+ * Description        : Main program body.
+ *********************************************************************************
+* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+
+
+/*
+ *@Note
+ This example reads image data from SPI flash and displays it on the LCD screen.
+ You should first put your image in SPI flash, the image format is RGB 565 and big-endian byte order
+ Both types of hardware communicate using the SPI interface.
+ You can set the lcd screen size and buffer size in config.h
+  pins: 
+    FLASH_CS   -- PA2
+    FLASH_DO   -- PA6(SPI1_MISO)
+    FLASH_WP   -- 3.3V
+    FLASH_DI   -- PA7(SPI1_MOSI)
+    FLASH_CLK  -- PA5(SPI1_SCK)
+    FLASH_HOLD -- 3.3V
+    
+    LCD_LED    -- PB9
+    LCD_DC     -- PB10
+    LCD_RST    -- PB11
+    LCD_CS     -- PB12
+    LCD_SCK    -- PB13(SPI2_SCK)
+    LCD_MOSI   -- PB15(SPI2_MOSI)
+
+*/
+
+
+#include "debug.h"
+#include "string.h"
+#include "lcd.h"
+#include "flash.h"
+#include "config.h"
+
+/* Global define */
+
+
+/* Global Variable */
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    uint32_t addr = 0;
+    uint16_t i    = 0;
+
+    SystemCoreClockUpdate();
+    Delay_Init();
+    USART_Printf_Init(115200);
+    printf("SystemClk:%d\r\n", SystemCoreClock);
+    SPI_FLASH_Init();
+    LCD_Init();
+
+    while (1)
+    {
+        addr = 0;
+        i    = 0;
+        while (i < 11)
+        {
+            i++;
+            LCD_drawImageWithSize(0, 0, LCD_W, LCD_H, addr);
+            addr += (LCD_W * LCD_H * COLOR_BYTE);
+        }
+    }
+}
diff --git a/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c b/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c
new file mode 100644
index 0000000..9461630
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.c
@@ -0,0 +1,987 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+//#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+  //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.h b/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.h
new file mode 100644
index 0000000..9c8a3f7
--- /dev/null
+++ b/EVT/EXAM/SPI/SPI_LCD/User/system_ch32v20x.h
@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H 
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
diff --git a/EVT/EXAM/SRC/Core/core_riscv.c b/EVT/EXAM/SRC/Core/core_riscv.c
index 7e92363..0ebf2a4 100644
--- a/EVT/EXAM/SRC/Core/core_riscv.c
+++ b/EVT/EXAM/SRC/Core/core_riscv.c
@@ -1,9 +1,9 @@
 /********************************** (C) COPYRIGHT  *******************************
  * File Name          : core_riscv.c
  * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2021/06/06
- * Description        : RISC-V Core Peripheral Access Layer Source File
+ * Version            : V1.0.1
+ * Date               : 2023/11/11
+ * Description        : RISC-V V4 Core Peripheral Access Layer Source File for CH32V20x
 *********************************************************************************
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * Attention: This software (modified or not) and binary are used for 
diff --git a/EVT/EXAM/SRC/Core/core_riscv.h b/EVT/EXAM/SRC/Core/core_riscv.h
index 5680701..a4e9fed 100644
--- a/EVT/EXAM/SRC/Core/core_riscv.h
+++ b/EVT/EXAM/SRC/Core/core_riscv.h
@@ -1,9 +1,9 @@
 /********************************** (C) COPYRIGHT  *******************************
  * File Name          : core_riscv.h
  * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2021/06/06
- * Description        : RISC-V Core Peripheral Access Layer Header File for CH32V20x
+ * Version            : V1.0.1
+ * Date               : 2023/11/11
+ * Description        : RISC-V V4 Core Peripheral Access Layer Header File for CH32V20x
 *********************************************************************************
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * Attention: This software (modified or not) and binary are used for 
@@ -129,7 +129,7 @@ typedef struct
  */
 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
 {
-  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
+  __asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
 }
 
 /*********************************************************************
@@ -141,7 +141,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
  */
 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
 {
-  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
+  __asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
 }
 
 /*********************************************************************
@@ -159,7 +159,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
 /*********************************************************************
  * @fn      NVIC_EnableIRQ
  *
- * @brief   Disable Interrupt
+ * @brief   Enable Interrupt
  *
  * @param   IRQn - Interrupt Numbers
  *
@@ -263,9 +263,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn
  * @brief   Set Interrupt Priority
  *
  * @param   IRQn - Interrupt Numbers
- *          priority - bit7 - Pre-emption Priority
- *                     bit[6:5] - Subpriority
- *
+ *          interrupt nesting enable(CSR-0x804 bit1 = 1 bit[3:2] = 1)
+ *            priority - bit[7] - Preemption Priority
+ *                       bit[6:4] - Sub priority
+ *                       bit[3:0] - Reserve
+ *          interrupt nesting disable(CSR-0x804 bit1 = 0 bit[3:2] = 0)
+ *            priority - bit[7:4] - Sub priority
+ *                       bit[3:0] - Reserve
  * @return  none
  */
 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
@@ -295,11 +299,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
  */
 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
 {
-  uint32_t t;
-
-  t = NVIC->SCTLR;
-  NVIC->SCTLR |= (1<<3)|(1<<5);
-  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
+  NVIC->SCTLR |= (1<<5);
 }
 
 /*********************************************************************
@@ -311,8 +311,11 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
  */
 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
 {
-  NVIC->SCTLR |= (1<<3);
-  asm volatile ("wfi");
+    uint32_t tmp= NVIC->SCTLR;
+    tmp &= ~(1<<5);
+    tmp |= (1<<3);
+    NVIC->SCTLR = tmp;
+    asm volatile ("wfi");
 }
 
 /*********************************************************************
@@ -327,6 +330,10 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
   _SEV();
   _WFE();
   _WFE();
+  if(*(vu32*)(0x40023800) & (1<<6))
+  {
+    NVIC->SCTLR |= (1<<5);
+  }
 }
 
 /*********************************************************************
@@ -341,7 +348,8 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
  *
  * @return  none
  */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
+{
   if(num > 3)  return ;
 
   if (NewState != DISABLE)
@@ -349,7 +357,8 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr
       NVIC->VTFIDR[num] = IRQn;
       NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
   }
-  else{
+  else
+  {
       NVIC->VTFIDR[num] = IRQn;
       NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
   }
diff --git a/EVT/EXAM/SRC/Debug/debug.c b/EVT/EXAM/SRC/Debug/debug.c
index 66eaf7a..311b8d4 100644
--- a/EVT/EXAM/SRC/Debug/debug.c
+++ b/EVT/EXAM/SRC/Debug/debug.c
@@ -14,6 +14,10 @@
 
 static uint8_t  p_us = 0;
 static uint16_t p_ms = 0;
+
+#define DEBUG_DATA0_ADDRESS  ((volatile uint32_t*)0xE0000380)
+#define DEBUG_DATA1_ADDRESS  ((volatile uint32_t*)0xE0000384)
+
 /*********************************************************************
  * @fn      Delay_Init
  *
@@ -139,6 +143,22 @@ void USART_Printf_Init(uint32_t baudrate)
 #endif
 }
 
+/*********************************************************************
+ * @fn      SDI_Printf_Enable
+ *
+ * @brief   Initializes the SDI printf Function.
+ *
+ * @param   None
+ *
+ * @return  None
+ */
+void SDI_Printf_Enable(void)
+{
+    *(DEBUG_DATA0_ADDRESS) = 0;
+    Delay_Init();
+    Delay_Ms(1);
+}
+
 /*********************************************************************
  * @fn      _write
  *
@@ -152,8 +172,44 @@ void USART_Printf_Init(uint32_t baudrate)
 __attribute__((used))
 int _write(int fd, char *buf, int size)
 {
-    int i;
+    int i = 0;
 
+#if (SDI_PRINT == SDI_PR_OPEN)
+    int writeSize = size;
+
+    do
+    {
+
+        /**
+         * data0  data1 8 byte
+         * data0 The storage length of the lowest byte, with a maximum of 7 bytes.
+         */
+
+        while( (*(DEBUG_DATA0_ADDRESS) != 0u))
+        {
+
+        }
+
+        if(writeSize>7)
+        {
+            *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
+            *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
+
+            i += 7;
+            writeSize -= 7;
+        }
+        else
+        {
+            *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
+            *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
+
+            writeSize = 0;
+        }
+
+    } while (writeSize);
+
+
+#else
     for(i = 0; i < size; i++){
 #if(DEBUG == DEBUG_UART1)
         while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
@@ -166,7 +222,7 @@ int _write(int fd, char *buf, int size)
         USART_SendData(USART3, *buf++);
 #endif
     }
-
+#endif
     return size;
 }
 
diff --git a/EVT/EXAM/SRC/Debug/debug.h b/EVT/EXAM/SRC/Debug/debug.h
index 4aae8a3..fd60cd0 100644
--- a/EVT/EXAM/SRC/Debug/debug.h
+++ b/EVT/EXAM/SRC/Debug/debug.h
@@ -2,7 +2,7 @@
  * File Name          : debug.h
  * Author             : WCH
  * Version            : V1.0.0
- * Date               : 2021/06/06
+ * Date               : 2023/10/24
  * Description        : This file contains all the functions prototypes for UART
  *                      Printf , Delay functions.
 *********************************************************************************
@@ -30,10 +30,20 @@ extern "C" {
 #define DEBUG   DEBUG_UART1
 #endif
 
+/* SDI Printf Definition */
+#define SDI_PR_CLOSE   0
+#define SDI_PR_OPEN    1
+
+#ifndef SDI_PRINT
+#define SDI_PRINT   SDI_PR_CLOSE
+#endif
+
+
 void Delay_Init(void);
 void Delay_Us(uint32_t n);
 void Delay_Ms(uint32_t n);
 void USART_Printf_Init(uint32_t baudrate);
+void SDI_Printf_Enable(void);
 
 #if(DEBUG)
   #define PRINT(format, ...)    printf(format, ##__VA_ARGS__)
diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
index 8da69fc..b69c1cd 100644
--- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
@@ -39,7 +39,7 @@ extern "C" {
 
 /* CH32V20x Standard Peripheral Library version number */
 #define __CH32V20x_STDPERIPH_VERSION_MAIN   (0x01) /* [15:8] main version */
-#define __CH32V20x_STDPERIPH_VERSION_SUB    (0x08) /* [7:0] sub version */
+#define __CH32V20x_STDPERIPH_VERSION_SUB    (0x09) /* [7:0] sub version */
 #define __CH32V20x_STDPERIPH_VERSION        ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
                                              |(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
 
diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h
index e0d7e85..e92130d 100644
--- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h
+++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_flash.h
@@ -26,7 +26,10 @@ typedef enum
     FLASH_ERROR_PG,
     FLASH_ERROR_WRP,
     FLASH_COMPLETE,
-    FLASH_TIMEOUT
+    FLASH_TIMEOUT,
+    FLASH_OP_RANGE_ERROR = 0xFD,
+    FLASH_ALIGN_ERROR = 0xFE,
+    FLASH_ADR_RANGE_ERROR = 0xFF,
 } FLASH_Status;
 
 /* Write Protect */
@@ -136,6 +139,8 @@ void         FLASH_LockBank1(void);
 FLASH_Status FLASH_EraseAllBank1Pages(void);
 FLASH_Status FLASH_GetBank1Status(void);
 FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
+FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
 
 #ifdef __cplusplus
 }
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usb.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usb.h
similarity index 93%
rename from EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usb.h
rename to EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usb.h
index 5a17f26..1dfa7a5 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usb.h
+++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_usb.h
@@ -2,7 +2,7 @@
  * File Name          : ch32v20x_usb.h
  * Author             : WCH
  * Version            : V1.0.0
- * Date               : 2020/04/30
+ * Date               : 2023/10/24
  * Description        : This file contains all the functions prototypes for the USB
  *                      firmware library.
 *********************************************************************************
@@ -27,6 +27,12 @@ extern "C" {
 
 /*******************************************************************************/
 /* USB Communication Related Macro Definition */
+#ifndef DEFAULT_ENDP0_SIZE
+#define DEFAULT_ENDP0_SIZE          8          // default maximum packet size for endpoint 0
+#endif
+#ifndef MAX_PACKET_SIZE
+#define MAX_PACKET_SIZE             64         // maximum packet size
+#endif
 
 /* USB PID */
 #ifndef USB_PID_SETUP
@@ -132,6 +138,7 @@ extern "C" {
 #define USB_DEV_CLASS_MONITOR       0x04
 #define USB_DEV_CLASS_PHYSIC_IF     0x05
 #define USB_DEV_CLASS_POWER         0x06
+#define USB_DEV_CLASS_IMAGE         0x06
 #define USB_DEV_CLASS_PRINTER       0x07
 #define USB_DEV_CLASS_STORAGE       0x08
 #define USB_DEV_CLASS_HUB           0x09
@@ -298,22 +305,8 @@ extern "C" {
 #define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
 #define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
 #define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
 #define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
 #define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
 #define USBFS_UEP4_BUF_MOD          0x01
 
 /* R8_UEP2_3_MOD */
diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c
index 104fdd7..983e93d 100644
--- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c
+++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_can.c
@@ -231,7 +231,7 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
 				(0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
 	}
 
-#if defined (CH32V20x_D6)||defined (CH32V20x_D8)
+#if defined (CH32V20x_D6)
 	if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0)
 	{
 		uint32_t i;
@@ -244,6 +244,27 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
 
 #endif
 
+
+#if defined (CH32V20x_D8)
+	RCC->AHBPCENR |= (1<<17);
+	*(vu32*)0x400250A0 = 0x55aaaa55;
+
+	if(*(vu32*)0x400250A0 != 0x55aaaa55)
+	{
+        uint32_t i;
+
+        for(i = 0; i < 64; i++)
+        {
+            *(__IO uint16_t *)(0x40006000 + 512 + 4 * i) = *(__IO uint16_t *)(0x40006000 + 768 + 4 * i);
+        }
+	}
+
+	RCC->AHBPCENR &= ~(1<<17);
+
+#endif
+
+
+
 	if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
 	{
 		CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos;
diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c
index 1059c54..7895c16 100644
--- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c
+++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_flash.c
@@ -24,7 +24,7 @@
 #define CR_OPTER_Reset             ((uint32_t)0xFFFFFFDF)
 #define CR_STRT_Set                ((uint32_t)0x00000040)
 #define CR_LOCK_Set                ((uint32_t)0x00000080)
-#define CR_FAST_LOCK_Set           ((uint32_t)0x00008000)
+#define CR_FLOCK_Set               ((uint32_t)0x00008000)
 #define CR_PAGE_PG                 ((uint32_t)0x00010000)
 #define CR_PAGE_ER                 ((uint32_t)0x00020000)
 #define CR_BER32                   ((uint32_t)0x00040000)
@@ -60,6 +60,20 @@
 #define EraseTimeout               ((uint32_t)0x000B0000)
 #define ProgramTimeout             ((uint32_t)0x00005000)
 
+/* Flash Program Vaild Address */
+#define ValidAddrStart             (FLASH_BASE)
+
+#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
+#define ValidAddrEnd               (FLASH_BASE + 0x78000)
+#else
+#define ValidAddrEnd               (FLASH_BASE + 0x38000)
+#endif
+
+/* FLASH Size */
+#define Size_256B                  0x100
+#define Size_4KB                   0x1000
+#define Size_32KB                  0x8000
+
 /*********************************************************************
  * @fn      FLASH_Unlock
  *
@@ -807,7 +821,7 @@ void FLASH_Unlock_Fast(void)
  */
 void FLASH_Lock_Fast(void)
 {
-    FLASH->CTLR |= CR_FAST_LOCK_Set;
+    FLASH->CTLR |= CR_FLOCK_Set;
 }
 
 /*********************************************************************
@@ -965,3 +979,272 @@ void FLASH_GetMACAddress(uint8_t *Buffer)
     Buffer[4] = value & 0xFF;
     Buffer[5] = (value >> 8) & 0xFF;
 }
+
+/*********************************************************************
+ * @fn      ROM_ERASE
+ *
+ * @brief   Select erases a specified FLASH .
+ *
+ * @param   StartAddr - Erases Flash start address(StartAddr%256 == 0).
+ *          Cnt - Erases count.
+ *          Erase_Size - Erases size select.The returned value can be:
+ *          Size_32KB, Size_4KB, Size_256B.
+ *
+ * @return  none.
+ */
+static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size)
+{
+    do{
+        if(Erase_Size == Size_32KB)
+        {
+            FLASH->CTLR |= CR_BER32;
+        }
+        else if(Erase_Size == Size_4KB)
+        {
+            FLASH->CTLR |= CR_PER_Set;
+        }
+        else if(Erase_Size == Size_256B)
+        {
+            FLASH->CTLR |= CR_PAGE_ER;
+        }
+
+        FLASH->ADDR = StartAddr;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+
+        if(Erase_Size == Size_32KB)
+        {
+            FLASH->CTLR &= ~CR_BER32;
+            StartAddr += Size_32KB;
+        }
+        else if(Erase_Size == Size_4KB)
+        {
+            FLASH->CTLR &= ~CR_PER_Set;
+            StartAddr += Size_4KB;
+        }
+        else if(Erase_Size == Size_256B)
+        {
+            FLASH->CTLR &= ~CR_PAGE_ER;
+            StartAddr += Size_256B;
+        }
+    }while(--Cnt);
+}
+
+/*********************************************************************
+ * @fn      FLASH_ROM_ERASE
+ *
+ * @brief   Erases a specified FLASH .
+ *
+ * @param   StartAddr - Erases Flash start address(StartAddr%256 == 0).
+ *          Length - Erases Flash start Length(Length%256 == 0).
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR,
+ *        FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length)
+{
+    uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0;
+
+    FLASH_Status status = FLASH_COMPLETE;
+
+    if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd))
+    {
+        return FLASH_ADR_RANGE_ERROR;
+    }
+
+    if((StartAddr + Length) > ValidAddrEnd)
+    {
+        return FLASH_OP_RANGE_ERROR;
+    }
+
+    if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0))
+    {
+        return FLASH_ALIGN_ERROR;
+    }
+
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+
+    Addr0 = StartAddr;
+
+    if(Length >= Size_32KB)
+    {
+        Length0 = Size_32KB - (Addr0 & (Size_32KB - 1));
+        Addr1 = StartAddr + Length0;
+        Length1 = Length - Length0;
+    }
+    else if(Length >= Size_4KB)
+    {
+        Length0 = Size_4KB - (Addr0 & (Size_4KB - 1));
+        Addr1 = StartAddr + Length0;
+        Length1 = Length - Length0;
+    }
+    else if(Length >= Size_256B)
+    {
+        Length0 = Length;
+    }
+
+    /* Erase 32KB */
+    if(Length0 >= Size_32KB)//front
+    {
+        Length = Length0;
+        if(Addr0 & (Size_32KB - 1))
+        {
+            Length0 = Size_32KB - (Addr0 & (Size_32KB - 1));
+        }
+        else
+        {
+            Length0 = 0;
+        }
+
+        ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB);
+    }
+
+    if(Length1 >= Size_32KB)//back
+    {
+        StartAddr = Addr1;
+        Length = Length1;
+
+        if((Addr1 + Length1) & (Size_32KB - 1))
+        {
+            Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1)));
+            Length1 = (StartAddr + Length1) & (Size_32KB - 1);
+        }
+        else
+        {
+            Length1 = 0;
+        }
+
+        ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB);
+    }
+
+    /* Erase 4KB */
+    if(Length0 >= Size_4KB) //front
+    {
+        Length = Length0;
+        if(Addr0 & (Size_4KB - 1))
+        {
+            Length0 = Size_4KB - (Addr0 & (Size_4KB - 1));
+        }
+        else
+        {
+            Length0 = 0;
+        }
+
+        ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 12), Size_4KB);
+    }
+
+    if(Length1 >= Size_4KB) //back
+    {
+        StartAddr = Addr1;
+        Length = Length1;
+
+        if((Addr1 + Length1) & (Size_4KB - 1))
+        {
+            Addr1 = ((StartAddr + Length1) & (~(Size_4KB - 1)));
+            Length1 = (StartAddr + Length1) & (Size_4KB - 1);
+        }
+        else
+        {
+            Length1 = 0;
+        }
+
+        ROM_ERASE(StartAddr, ((Length - Length1) >> 12), Size_4KB);
+    }
+
+    /* Erase 256B */
+    if(Length0)//front
+    {
+        ROM_ERASE(Addr0, (Length0 >> 8), Size_256B);
+    }
+
+    if(Length1)//back
+    {
+        ROM_ERASE(Addr1, (Length1 >> 8), Size_256B);
+    }
+
+    FLASH->CTLR |= CR_FLOCK_Set;
+    FLASH->CTLR |= CR_LOCK_Set;
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ROM_WRITE
+ *
+ * @brief   Writes a specified FLASH .
+ *
+ * @param   StartAddr - Writes Flash start address(StartAddr%256 == 0).
+ *          Length - Writes Flash start Length(Length%256 == 0).
+ *          pbuf - Writes Flash value buffer.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR,
+ *        FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length)
+{
+    uint32_t i;
+    uint8_t size;
+
+    FLASH_Status status = FLASH_COMPLETE;
+
+    if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd))
+    {
+        return FLASH_ADR_RANGE_ERROR;
+    }
+
+    if((StartAddr + Length) > ValidAddrEnd)
+    {
+        return FLASH_OP_RANGE_ERROR;
+    }
+
+    if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0))
+    {
+        return FLASH_ALIGN_ERROR;
+    }
+
+    i = Length >> 8;
+
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast program mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+
+    do{
+        FLASH->CTLR |= CR_PAGE_PG;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        while(FLASH->STATR & SR_WR_BSY)
+            ;
+        size = 64;
+        while(size)
+        {
+            *(uint32_t *)StartAddr = *(uint32_t *)pbuf;
+            StartAddr += 4;
+            pbuf += 1;
+            size -= 1;
+            while(FLASH->STATR & SR_WR_BSY)
+                ;
+        }
+
+        FLASH->CTLR |= CR_PG_STRT;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_PAGE_PG;
+    }while(--i);
+
+    FLASH->CTLR |= CR_FLOCK_Set;
+    FLASH->CTLR |= CR_LOCK_Set;
+
+    return status;
+}
+
diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c
index 9ab01e4..3038063 100644
--- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c
+++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c
@@ -2,7 +2,7 @@
  * File Name          : ch32v20x_gpio.c
  * Author             : WCH
  * Version            : V1.0.0
- * Date               : 2021/06/06
+ * Date               : 2023/11/23
  * Description        : This file provides all the GPIO firmware functions.
  *********************************************************************************
  * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -556,12 +556,10 @@ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
     {
         tmpreg = AFIO->PCFR1;
 
-#if defined (CH32V20x_D6) || defined (CH32V20x_D8)
     if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0){
         tmpreg = ((tmpreg>>1)&0xFFFFE000)|(tmpreg&0x00001FFF);
     }
 
-#endif
     }
 
     tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
@@ -683,6 +681,7 @@ void GPIO_IPD_Unused(void)
     chip =  *( uint32_t * )0x1FFFF704 & (~0x000000F0);
     switch(chip)
     {
+#ifdef CH32V20x_D6
         case 0x20370500:     //CH32V203F6P6
         {
             GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
@@ -935,6 +934,7 @@ void GPIO_IPD_Unused(void)
             GPIO_Init(GPIOD, &GPIO_InitStructure);
             break;
         }
+#elif defined(CH32V20x_D8)
         case 0x2034050C:     //CH32V203RBT6
         {
             GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
@@ -943,6 +943,7 @@ void GPIO_IPD_Unused(void)
             GPIO_Init(GPIOD, &GPIO_InitStructure);
             break;
         }
+#elif defined(CH32V20x_D8W)
         case 0x2083050C:     //CH32V208GBU6
         {
             GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
@@ -998,11 +999,10 @@ void GPIO_IPD_Unused(void)
             GPIO_Init(GPIOD, &GPIO_InitStructure);
             break;
         }
+#endif
         default:
         {
             break;
         }
-
     }
-
-}
+}
\ No newline at end of file
diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rtc.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rtc.c
index 5a9a364..6291ca5 100644
--- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rtc.c
+++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_rtc.c
@@ -72,22 +72,36 @@ void RTC_ExitConfigMode(void)
  */
 uint32_t RTC_GetCounter(void)
 {
-    uint16_t high1 = 0, high2 = 0, low = 0;
+    uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
+    uint16_t low1 = 0, low2 = 0;
 
-    high1 = RTC->CNTH;
-    low = RTC->CNTL;
-    high2 = RTC->CNTH;
+    do{
+        high1a = RTC->CNTH;
+        high1b = RTC->CNTH;
+    }while( high1a != high1b );
 
-    if(high1 != high2)
+    do{
+        low1 = RTC->CNTL;
+        low2 = RTC->CNTL;
+    }while( low1 != low2 );
+
+    do{
+        high2a = RTC->CNTH;
+        high2b = RTC->CNTH;
+    }while( high2a != high2b );
+
+    if(high1b != high2b)
     {
-        return (((uint32_t)high2 << 16) | RTC->CNTL);
-    }
-    else
-    {
-        return (((uint32_t)high1 << 16) | low);
+        do{
+            low1 = RTC->CNTL;
+            low2 = RTC->CNTL;
+        }while( low1 != low2 );
     }
+
+    return (((uint32_t)high2b << 16) | low2);
 }
 
+
 /*********************************************************************
  * @fn      RTC_SetCounter
  *
@@ -148,10 +162,33 @@ void RTC_SetAlarm(uint32_t AlarmValue)
  */
 uint32_t RTC_GetDivider(void)
 {
-    uint32_t tmp = 0x00;
-    tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
-    tmp |= RTC->DIVL;
-    return tmp;
+    uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
+    uint16_t low1 = 0, low2 = 0;
+
+    do{
+        high1a = RTC->DIVH;
+        high1b = RTC->DIVH;
+    }while( high1a != high1b );
+
+    do{
+        low1 = RTC->DIVL;
+        low2 = RTC->DIVL;
+    }while( low1 != low2 );
+
+    do{
+        high2a = RTC->DIVH;
+        high2b = RTC->DIVH;
+    }while( high2a != high2b );
+
+    if(high1b != high2b)
+    {
+        do{
+            low1 = RTC->DIVL;
+            low2 = RTC->DIVL;
+        }while( low1 != low2 );
+    }
+
+    return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2);
 }
 
 /*********************************************************************
diff --git a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S
index 30b9fcd..385b830 100644
--- a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D6.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D6.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/11
 ;* Description        :  CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -99,7 +87,6 @@ _vector_base:
     .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -156,60 +143,62 @@ _vector_base:
     .weak   UART4_IRQHandler           /* UART4 */
     .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -222,7 +211,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -234,7 +223,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -243,17 +232,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested and hardware stack */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x3
 	csrw 0x804, t0
-
-    /* Enable interrupt */
+/* Enable global interrupt and configure privileged mode */
    	li t0, 0x88           
-   	csrs mstatus, t0
-
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S
index f2226eb..77cff42 100644
--- a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S
+++ b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D8.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/11
 ;* Description        : CH32V203RB
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -106,7 +94,6 @@ _vector_base:
     .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -168,65 +155,67 @@ _vector_base:
     .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
     .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-ETH_IRQHandler:  1:  j 1b
-ETHWakeUp_IRQHandler:  1:  j 1b
-TIM5_IRQHandler:  1:  j 1b
-OSC32KCal_IRQHandler:  1:  j 1b
-OSCWakeUp_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+TIM5_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -239,7 +228,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -251,7 +240,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -260,17 +249,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested and hardware stack */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x3
 	csrw 0x804, t0
-
-    /* Enable interrupt */
+/* Enable global interrupt and configure privileged mode */
    	li t0, 0x88           
-   	csrs mstatus, t0
-
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S
index 4c5af6d..5d1a200 100644
--- a/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S
+++ b/EVT/EXAM/SRC/Startup/startup_ch32v20x_D8W.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D8W.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/11
 ;* Description        : CH32V208x
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -106,7 +94,6 @@ _vector_base:
     .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -170,67 +157,69 @@ _vector_base:
     .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
     .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-ETH_IRQHandler:  1:  j 1b
-ETHWakeUp_IRQHandler:  1:  j 1b
-BB_IRQHandler:  1:  j 1b
-LLE_IRQHandler:  1:  j 1b
-TIM5_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
-OSC32KCal_IRQHandler:  1:  j 1b
-OSCWakeUp_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+BB_IRQHandler:
+LLE_IRQHandler:
+TIM5_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -243,7 +232,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -255,7 +244,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -264,17 +253,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested and hardware stack */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x3
 	csrw 0x804, t0
-
-    /* Enable interrupt */
+/* Enable global interrupt and configure privileged mode */
    	li t0, 0x88           
-   	csrs mstatus, t0
-
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c b/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c
+++ b/EVT/EXAM/SYSTICK/SYSTICK_Interrupt/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c b/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/Clock_Select/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c b/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/ComplementaryOutput_DeadTime/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c b/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/ExtTrigger_Start_Two_Timer/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c b/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c
index 5006644..7ae6a64 100644
--- a/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c
+++ b/EVT/EXAM/TIM/Input_Capture/User/ch32v20x_it.c
@@ -52,7 +52,6 @@ void TIM1_CC_IRQHandler(void)
 	if( TIM_GetITStatus( TIM1, TIM_IT_CC1 ) != RESET )
 	{
 		printf( "CH1_Val:%d\r\n", TIM_GetCapture1( TIM1 ) );
-		TIM_SetCounter( TIM1, 0 );
 	}
 
 	if( TIM_GetITStatus( TIM1, TIM_IT_CC2 ) != RESET )
diff --git a/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c b/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/Input_Capture/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c b/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/One_Pulse/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c b/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/Output_Compare_Mode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c b/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/PWM_Output/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c b/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/Synchro_ExtTrigger/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c b/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/Synchro_Timer/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c b/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/TIM/TIM_DMA/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/TOUCHKEY/.cproject b/EVT/EXAM/TOUCHKEY/.cproject
deleted file mode 100644
index 9c25db3..0000000
--- a/EVT/EXAM/TOUCHKEY/.cproject
+++ /dev/null
@@ -1,143 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
-					<folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074." name="/" resourcePath="">
-						<toolChain id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release.231146001" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release">
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diff --git a/EVT/EXAM/TOUCHKEY/.template b/EVT/EXAM/TOUCHKEY/.template
deleted file mode 100644
index f76503c..0000000
--- a/EVT/EXAM/TOUCHKEY/.template
+++ /dev/null
@@ -1,16 +0,0 @@
-Mcu Type=CH32V20x
-Address=0x08000000
-Target Path=obj/TOUCHKEY.hex
-Erase All=true
-Program=true
-Verify=true
-Reset=true
-
-Vendor=WCH
-Link=WCH-Link
-Toolchain=RISC-V
-Series=CH32V203
-Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
-
-PeripheralVersion=1.0
-MCU=CH32V203RBT6
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/.cproject b/EVT/EXAM/TOUCHKEY/TKEY/.cproject
new file mode 100644
index 0000000..93c33ac
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/.cproject
@@ -0,0 +1,143 @@
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+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
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+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry excluding="startup_ch32v20x_D8.S|startup_ch32v20x_D8W.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	
+</cproject>
diff --git a/EVT/EXAM/TOUCHKEY/.project b/EVT/EXAM/TOUCHKEY/TKEY/.project
similarity index 83%
rename from EVT/EXAM/TOUCHKEY/.project
rename to EVT/EXAM/TOUCHKEY/TKEY/.project
index 53d8642..bc50f79 100644
--- a/EVT/EXAM/TOUCHKEY/.project
+++ b/EVT/EXAM/TOUCHKEY/TKEY/.project
@@ -35,27 +35,27 @@
     <link>
       <name>Core</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Core</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
     </link>
     <link>
       <name>Debug</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Debug</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
     </link>
     <link>
       <name>Ld</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Ld</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
     </link>
     <link>
       <name>Peripheral</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Peripheral</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
     </link>
     <link>
       <name>Startup</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Startup</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
     </link>
   </linkedResources>
 </projectDescription>
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/.template b/EVT/EXAM/TOUCHKEY/TKEY/.template
new file mode 100644
index 0000000..1af66ef
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\TOUCHKEY.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/TOUCHKEY.wvproj b/EVT/EXAM/TOUCHKEY/TKEY/TOUCHKEY.wvproj
new file mode 100644
index 0000000..2cd99d9
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/TOUCHKEY.wvproj
@@ -0,0 +1,2 @@
+�i�CZ	?"ǁ�r��
F<Fy8E9Y���%Pa�D�La�%�'y��]�;���S)1�1+R4><�.��ſ��?/�XO�ĿChQN$*���E
�Bk�!
2t�+buh�nUb]xl�l|
++"�<��AH42}z8p;m�u1�-�eh�Od��w��7x{5�CqEx�=;��e���2��	��*BPM�"
\ No newline at end of file
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_conf.h b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_conf.h
new file mode 100644
index 0000000..d1eeb38
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_conf.h
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+	
+	
+	
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c
new file mode 100644
index 0000000..f2598c2
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.c
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main Interrupt Service Routines.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.h b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.h
new file mode 100644
index 0000000..f68b203
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/User/ch32v20x_it.h
@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/EVT/EXAM/TOUCHKEY/User/main.c b/EVT/EXAM/TOUCHKEY/TKEY/User/main.c
similarity index 100%
rename from EVT/EXAM/TOUCHKEY/User/main.c
rename to EVT/EXAM/TOUCHKEY/TKEY/User/main.c
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c b/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c
new file mode 100644
index 0000000..8d3a568
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.c
@@ -0,0 +1,987 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+  //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.h b/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.h
new file mode 100644
index 0000000..9c8a3f7
--- /dev/null
+++ b/EVT/EXAM/TOUCHKEY/TKEY/User/system_ch32v20x.h
@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H 
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
diff --git a/EVT/EXAM/TencentOS/TencentOS/.cproject b/EVT/EXAM/TencentOS/TencentOS/.cproject
index 75370f1..caf7323 100644
--- a/EVT/EXAM/TencentOS/TencentOS/.cproject
+++ b/EVT/EXAM/TencentOS/TencentOS/.cproject
@@ -141,7 +141,7 @@
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
-						<entry excluding="startup_ch32v20x_D8W.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+						<entry excluding="startup_ch32v20x_D8W.S|startup_ch32v20x_D8.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -163,5 +163,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S
index c5f7079..ce1ea08 100644
--- a/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S
+++ b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D6.S
@@ -1,8 +1,8 @@
 ;/********************************** (C) COPYRIGHT *******************************
 ;* File Name          : startup_ch32v20x_D6.s
 ;* Author             : WCH
-;* Version            : V1.0.0
-;* Date               : 2021/06/06
+;* Version            : V1.0.1
+;* Date               : 2023/11/11
 ;* Description        :  CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
 ;*                    vector table for eclipse toolchain.
 ;*********************************************************************************
@@ -16,19 +16,7 @@
 	.align	1
 _start:
 	j	handle_reset
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00000013
-	.word 0x00100073
+
     .section    .vector,"ax",@progbits
     .align  1
 _vector_base:
@@ -99,7 +87,6 @@ _vector_base:
     .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
     .option rvc;
-
     .section    .text.vector_handler, "ax", @progbits
     .weak   NMI_Handler                /* NMI */
     .weak   HardFault_Handler          /* Hard Fault */
@@ -156,60 +143,62 @@ _vector_base:
     .weak   UART4_IRQHandler           /* UART4 */
     .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
 
-NMI_Handler:  1:  j 1b
-HardFault_Handler:  1:  j 1b
-Ecall_M_Mode_Handler:  1:  j 1b
-Ecall_U_Mode_Handler:  1:  j 1b
-Break_Point_Handler:  1:  j 1b
-SysTick_Handler:  1:  j 1b
-SW_Handler:  1:  j 1b
-WWDG_IRQHandler:  1:  j 1b
-PVD_IRQHandler:  1:  j 1b
-TAMPER_IRQHandler:  1:  j 1b
-RTC_IRQHandler:  1:  j 1b
-FLASH_IRQHandler:  1:  j 1b
-RCC_IRQHandler:  1:  j 1b
-EXTI0_IRQHandler:  1:  j 1b
-EXTI1_IRQHandler:  1:  j 1b
-EXTI2_IRQHandler:  1:  j 1b
-EXTI3_IRQHandler:  1:  j 1b
-EXTI4_IRQHandler:  1:  j 1b
-DMA1_Channel1_IRQHandler:  1:  j 1b
-DMA1_Channel2_IRQHandler:  1:  j 1b
-DMA1_Channel3_IRQHandler:  1:  j 1b
-DMA1_Channel4_IRQHandler:  1:  j 1b
-DMA1_Channel5_IRQHandler:  1:  j 1b
-DMA1_Channel6_IRQHandler:  1:  j 1b
-DMA1_Channel7_IRQHandler:  1:  j 1b
-ADC1_2_IRQHandler:  1:  j 1b
-USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
-USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
-CAN1_RX1_IRQHandler:  1:  j 1b
-CAN1_SCE_IRQHandler:  1:  j 1b
-EXTI9_5_IRQHandler:  1:  j 1b
-TIM1_BRK_IRQHandler:  1:  j 1b
-TIM1_UP_IRQHandler:  1:  j 1b
-TIM1_TRG_COM_IRQHandler:  1:  j 1b
-TIM1_CC_IRQHandler:  1:  j 1b
-TIM2_IRQHandler:  1:  j 1b
-TIM3_IRQHandler:  1:  j 1b
-TIM4_IRQHandler:  1:  j 1b
-I2C1_EV_IRQHandler:  1:  j 1b
-I2C1_ER_IRQHandler:  1:  j 1b
-I2C2_EV_IRQHandler:  1:  j 1b
-I2C2_ER_IRQHandler:  1:  j 1b
-SPI1_IRQHandler:  1:  j 1b
-SPI2_IRQHandler:  1:  j 1b
-USART1_IRQHandler:  1:  j 1b
-USART2_IRQHandler:  1:  j 1b
-USART3_IRQHandler:  1:  j 1b
-EXTI15_10_IRQHandler:  1:  j 1b
-RTCAlarm_IRQHandler:  1:  j 1b
-USBWakeUp_IRQHandler:  1:  j 1b
-USBHD_IRQHandler:  1:  j 1b
-USBHDWakeUp_IRQHandler:  1:  j 1b
-UART4_IRQHandler:  1:  j 1b
-DMA1_Channel8_IRQHandler:  1:  j 1b
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
 
 	.section	.text.handle_reset,"ax",@progbits
 	.weak	handle_reset
@@ -222,7 +211,7 @@ handle_reset:
 1:
 	la sp, _eusrstack 
 2:
-	/* Load data section from flash to RAM */
+/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
@@ -234,7 +223,7 @@ handle_reset:
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
-	/* Clear bss section */
+/* Clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
@@ -243,17 +232,16 @@ handle_reset:
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
+/* Configure pipelining and instruction prediction */
     li t0, 0x1f
     csrw 0xbc0, t0
-
-    /* Enable nested  */
+/* Enable interrupt nesting and hardware stack */
 	li t0, 0x2
 	csrw 0x804, t0
-
-    /* Enable interrupt */
-   	li t0, 0x1800
-   	csrs mstatus, t0
-
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
diff --git a/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8.S b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8.S
new file mode 100644
index 0000000..6d0188e
--- /dev/null
+++ b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8.S
@@ -0,0 +1,269 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V203RB
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   0                          /* BLE BB */
+    .word   0                          /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+TIM5_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
diff --git a/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8W.S b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8W.S
new file mode 100644
index 0000000..dad9c92
--- /dev/null
+++ b/EVT/EXAM/TencentOS/TencentOS/Startup/startup_ch32v20x_D8W.S
@@ -0,0 +1,275 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v20x_D8W.s
+;* Author             : WCH
+;* Version            : V1.0.1
+;* Date               : 2023/11/20
+;* Description        : CH32V208x
+;*                    vector table for eclipse toolchain.
+;*********************************************************************************
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* Attention: This software (modified or not) and binary are used for 
+;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_Handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wake up from suspend */
+    .word   USBHD_IRQHandler           /* USBHD Break */
+    .word   USBHDWakeUp_IRQHandler     /* USBHD Wake up from suspend */
+    .word   ETH_IRQHandler             /* ETH global */
+    .word   ETHWakeUp_IRQHandler       /* ETH Wake up */
+    .word   BB_IRQHandler              /* BLE BB */
+    .word   LLE_IRQHandler             /* BLE LLE */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .word   OSC32KCal_IRQHandler       /* OSC32KCal */
+    .word   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+    .option rvc;
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_Handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   USBHD_IRQHandler           /* USBHD */
+    .weak   USBHDWakeUp_IRQHandler     /* USBHD Wake Up */
+    .weak   ETH_IRQHandler             /* ETH global */
+    .weak   ETHWakeUp_IRQHandler       /* ETHWakeUp */
+    .weak   BB_IRQHandler              /* BLE BB */
+    .weak   LLE_IRQHandler             /* BLE LLE */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   DMA1_Channel8_IRQHandler   /* DMA1 Channel8 */
+    .weak   OSC32KCal_IRQHandler       /* OSC32 KCal */
+    .weak   OSCWakeUp_IRQHandler       /* OSC Wake Up */
+
+NMI_Handler:
+HardFault_Handler:
+Ecall_M_Mode_Handler:
+Ecall_U_Mode_Handler:
+Break_Point_Handler:
+SysTick_Handler:
+SW_Handler:
+WWDG_IRQHandler:
+PVD_IRQHandler:
+TAMPER_IRQHandler:
+RTC_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Channel1_IRQHandler:
+DMA1_Channel2_IRQHandler:
+DMA1_Channel3_IRQHandler:
+DMA1_Channel4_IRQHandler:
+DMA1_Channel5_IRQHandler:
+DMA1_Channel6_IRQHandler:
+DMA1_Channel7_IRQHandler:
+ADC1_2_IRQHandler:
+USB_HP_CAN1_TX_IRQHandler:
+USB_LP_CAN1_RX0_IRQHandler:
+CAN1_RX1_IRQHandler:
+CAN1_SCE_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTCAlarm_IRQHandler:
+USBWakeUp_IRQHandler:
+USBHD_IRQHandler:
+USBHDWakeUp_IRQHandler:
+ETH_IRQHandler:
+ETHWakeUp_IRQHandler:
+BB_IRQHandler:
+LLE_IRQHandler:
+TIM5_IRQHandler:
+UART4_IRQHandler:
+DMA1_Channel8_IRQHandler:
+OSC32KCal_IRQHandler:
+OSCWakeUp_IRQHandler:
+1:
+	j 1b
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+/* Configure pipelining and instruction prediction */
+    li t0, 0x1f
+    csrw 0xbc0, t0
+/* Enable interrupt nesting and hardware stack */
+	li t0, 0x2
+	csrw 0x804, t0
+/* Enable global interrupt and configure privileged mode */
+   	li t0, 0x1800           
+   	csrw mstatus, t0
+/* Configure the interrupt vector table recognition mode and entry address mode */
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
+
+
diff --git a/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c b/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c
+++ b/EVT/EXAM/TencentOS/TencentOS/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_DMA/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_HalfDuplex/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_HardwareFlowControl/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/WWDG/.cproject b/EVT/EXAM/USART/USART_Idle_Recv/.cproject
similarity index 97%
rename from EVT/EXAM/WWDG/.cproject
rename to EVT/EXAM/USART/USART_Idle_Recv/.cproject
index 6284941..3b6b5bb 100644
--- a/EVT/EXAM/WWDG/.cproject
+++ b/EVT/EXAM/USART/USART_Idle_Recv/.cproject
@@ -45,11 +45,11 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.69403096" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1701516240" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.880205089" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.2137556538" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.2112033835" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.626052152" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/WWDG}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/USART_SynchronousMode}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
 							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1244756189" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/.project b/EVT/EXAM/USART/USART_Idle_Recv/.project
new file mode 100644
index 0000000..803cd7c
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/.project
@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<projectDescription>
+  <name>USART_Idle_Recv</name>
+  <comment/>
+  <projects/>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments/>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <filteredResources>
+    <filter>
+      <id>1595986042669</id>
+      <name/>
+      <type>22</type>
+      <matcher>
+        <id>org.eclipse.ui.ide.multiFilter</id>
+        <arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+      </matcher>
+    </filter>
+  </filteredResources>
+  <linkedResources>
+    <link>
+      <name>Core</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
+    </link>
+    <link>
+      <name>Debug</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
+    </link>
+    <link>
+      <name>Ld</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
+    </link>
+    <link>
+      <name>Peripheral</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
+    </link>
+    <link>
+      <name>Startup</name>
+      <type>2</type>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
+    </link>
+  </linkedResources>
+</projectDescription>
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/.template b/EVT/EXAM/USART/USART_Idle_Recv/.template
new file mode 100644
index 0000000..91b2236
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/.template
@@ -0,0 +1,17 @@
+Mcu Type=CH32V20x
+Address=0x08000000
+Target Path=obj\USART_Idle_Recv.hex
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=RISC-V
+Series=CH32V203
+Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
+
+PeripheralVersion=1.0
+MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/USART_Idle_Recv.wvproj b/EVT/EXAM/USART/USART_Idle_Recv/USART_Idle_Recv.wvproj
new file mode 100644
index 0000000..2cd99d9
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/USART_Idle_Recv.wvproj
@@ -0,0 +1,2 @@
+�i�CZ	?"ǁ�r��
F<Fy8E9Y���%Pa�D�La�%�'y��]�;���S)1�1+R4><�.��ſ��?/�XO�ĿChQN$*���E
�Bk�!
2t�+buh�nUb]xl�l|
++"�<��AH42}z8p;m�u1�-�eh�Od��w��7x{5�CqEx�=;��e���2��	��*BPM�"
\ No newline at end of file
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_conf.h b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_conf.h
new file mode 100644
index 0000000..d1eeb38
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_conf.h
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+	
+	
+	
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c
new file mode 100644
index 0000000..f2598c2
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.c
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main Interrupt Service Routines.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.h b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.h
new file mode 100644
index 0000000..f68b203
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/User/ch32v20x_it.h
@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/main.c b/EVT/EXAM/USART/USART_Idle_Recv/User/main.c
new file mode 100644
index 0000000..23a90f0
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/User/main.c
@@ -0,0 +1,277 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : main.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Main program body.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+
+/*
+ *@Note
+ This example demonstrates receiving indeterminate length data via USART's IDLE interrupt and DMA.
+ USART1_Tx(PA9), USART1_Rx(PA10).
+
+
+*/
+
+#include "debug.h"
+#include "string.h"
+
+void USART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+// ring buffer size
+#define RING_BUFFER_LEN     (1024u)
+
+// The length of a single buffer used by DMA
+#define RX_BUFFER_LEN       (128u)
+
+#define USART_RX_CH         DMA1_Channel5
+
+
+
+struct
+{
+    volatile uint8_t DMA_USE_BUFFER;
+    uint8_t          Rx_Buffer[2][RX_BUFFER_LEN];
+
+} USART_DMA_CTRL = {
+    .DMA_USE_BUFFER = 0,
+    .Rx_Buffer      = {0},
+};
+
+struct
+{
+    uint8_t           buffer[RING_BUFFER_LEN];
+    volatile uint16_t RecvPos;  //
+    volatile uint16_t SendPos;  //
+    volatile uint16_t RemainCount;
+
+} ring_buffer = {{0}, 0, 0, 0};
+
+/*********************************************************************
+ * @fn      USARTx_CFG
+ *
+ * @brief   Initializes the USART1 peripheral.
+ *
+ * @return  none
+ */
+void USARTx_CFG(uint32_t baudrate)
+{
+    GPIO_InitTypeDef  GPIO_InitStructure  = {0};
+    USART_InitTypeDef USART_InitStructure = {0};
+    NVIC_InitTypeDef  NVIC_InitStructure  = {0};
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB| RCC_APB2Periph_USART1, ENABLE);
+
+    /* USART1 TX-->A.9   RX-->A.10 */
+    GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    USART_InitStructure.USART_BaudRate            = baudrate;
+    USART_InitStructure.USART_WordLength          = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits            = USART_StopBits_1;
+    USART_InitStructure.USART_Parity              = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode                = USART_Mode_Tx | USART_Mode_Rx;
+
+    USART_Init(USART1, &USART_InitStructure);
+    USART_ITConfig(USART1, USART_IT_IDLE, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel                   = USART1_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority        = 1;
+    NVIC_InitStructure.NVIC_IRQChannelCmd                = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    USART_Cmd(USART1, ENABLE);
+}
+
+
+/*********************************************************************
+ * @fn      DMA_INIT
+ *
+ * @brief   Configures the DMA for USART1.
+ *
+ * @return  none
+ */
+void DMA_INIT(void)
+{
+    DMA_InitTypeDef  DMA_InitStructure  = {0};
+    NVIC_InitTypeDef NVIC_InitStructure = {0};
+
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+    DMA_DeInit(USART_RX_CH);
+    DMA_InitStructure.DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc          = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStructure.DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
+    DMA_InitStructure.DMA_Mode               = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority           = DMA_Priority_VeryHigh;
+    DMA_InitStructure.DMA_M2M                = DMA_M2M_Disable;
+
+    DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&USART1->DATAR);
+    DMA_InitStructure.DMA_MemoryBaseAddr     = (u32)USART_DMA_CTRL.Rx_Buffer[0];
+    DMA_InitStructure.DMA_DIR                = DMA_DIR_PeripheralSRC;
+    DMA_InitStructure.DMA_BufferSize         = RX_BUFFER_LEN;
+    DMA_Init(USART_RX_CH, &DMA_InitStructure);
+
+    DMA_ITConfig(USART_RX_CH, DMA_IT_TC, ENABLE);
+
+    NVIC_InitStructure.NVIC_IRQChannel                   = DMA1_Channel5_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority        = 1;
+    NVIC_InitStructure.NVIC_IRQChannelCmd                = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    DMA_Cmd(USART_RX_CH, ENABLE);
+    USART_DMACmd(USART1, USART_DMAReq_Rx, ENABLE);
+}
+
+
+/*********************************************************************
+ * @fn      ring_buffer_push_huge
+ *
+ * @brief   Put a large amount of data into the ring buffer.
+ *
+ * @return  none
+ */
+void ring_buffer_push_huge(uint8_t *buffer, uint16_t len)
+{
+    const uint16_t bufferRemainCount = RING_BUFFER_LEN - ring_buffer.RemainCount;
+    if (bufferRemainCount < len)
+    {
+        len = bufferRemainCount;
+    }
+
+    const uint16_t bufferSize = RING_BUFFER_LEN - ring_buffer.RecvPos;
+    if (bufferSize >= len)
+    {
+        memcpy(&(ring_buffer.buffer[ring_buffer.RecvPos]), buffer, len);
+        ring_buffer.RecvPos += len;
+    }
+    else
+    {
+        uint16_t otherSize = len - bufferSize;
+        memcpy(&(ring_buffer.buffer[ring_buffer.RecvPos]), buffer, bufferSize);
+        memcpy(ring_buffer.buffer, &(buffer[bufferSize]), otherSize);
+        ring_buffer.RecvPos = otherSize;
+    }
+    ring_buffer.RemainCount += len;
+}
+
+/*********************************************************************
+ * @fn      ring_buffer_pop
+ *
+ * @brief   Get a data from the ring buffer.
+ *
+ * @return  the Data
+ */
+uint8_t ring_buffer_pop()
+{
+    uint8_t data = ring_buffer.buffer[ring_buffer.SendPos];
+
+    ring_buffer.SendPos++;
+    if (ring_buffer.SendPos >= RING_BUFFER_LEN)
+    {
+        ring_buffer.SendPos = 0;
+    }
+    ring_buffer.RemainCount--;
+    return data;
+}
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+    Delay_Init();
+    USART_Printf_Init(115200);
+    USARTx_CFG(115200);
+    DMA_INIT();
+    printf("SystemClk:%d\r\n", SystemCoreClock);
+    printf("This is an example\r\n");
+
+    while (1)
+    {
+        if (ring_buffer.RemainCount > 0)
+        {
+            printf("recv %d >>>\n", ring_buffer.RemainCount);
+            while (ring_buffer.RemainCount > 0)
+            {
+                printf("%c", ring_buffer_pop());
+            }
+            printf("\n<<<\n");
+        }
+        Delay_Ms(1000);
+    }
+}
+
+/*********************************************************************
+ * @fn      USART1_IRQHandler
+ *
+ * @brief   This function handles USART1 global interrupt request.
+ *
+ * @return  none
+ */
+void USART1_IRQHandler(void)
+{
+    if (USART_GetITStatus(USART1, USART_IT_IDLE) != RESET)
+    {
+        // IDLE
+        uint16_t rxlen     = (RX_BUFFER_LEN - USART_RX_CH->CNTR);
+        uint8_t  oldbuffer = USART_DMA_CTRL.DMA_USE_BUFFER;
+
+        USART_DMA_CTRL.DMA_USE_BUFFER = !oldbuffer;
+
+        DMA_Cmd(USART_RX_CH, DISABLE);
+        DMA_SetCurrDataCounter(USART_RX_CH, RX_BUFFER_LEN);
+        // Switch buffer
+        USART_RX_CH->MADDR = (uint32_t)(USART_DMA_CTRL.Rx_Buffer[USART_DMA_CTRL.DMA_USE_BUFFER]);
+        DMA_Cmd(USART_RX_CH, ENABLE);
+
+        USART_ReceiveData(USART1); // clear IDLE flag
+        ring_buffer_push_huge(USART_DMA_CTRL.Rx_Buffer[oldbuffer], rxlen);
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA1_Channel5_IRQHandler
+ *
+ * @brief   This function handles DMA1 Channel 5 global interrupt request.
+ *
+ * @return  none
+ */
+void DMA1_Channel5_IRQHandler(void)
+{
+    uint16_t rxlen     = RX_BUFFER_LEN;
+    uint8_t  oldbuffer = USART_DMA_CTRL.DMA_USE_BUFFER;
+    // FULL
+
+    USART_DMA_CTRL.DMA_USE_BUFFER = !oldbuffer;
+
+    DMA_Cmd(USART_RX_CH, DISABLE);
+    DMA_SetCurrDataCounter(USART_RX_CH, RX_BUFFER_LEN);
+    // Switch buffer
+    USART_RX_CH->MADDR = (uint32_t)(USART_DMA_CTRL.Rx_Buffer[USART_DMA_CTRL.DMA_USE_BUFFER]);
+    DMA_Cmd(USART_RX_CH, ENABLE);
+
+    ring_buffer_push_huge(USART_DMA_CTRL.Rx_Buffer[oldbuffer], rxlen);
+
+    DMA_ClearITPendingBit(DMA1_IT_TC5);
+}
diff --git a/EVT/EXAM/TOUCHKEY/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c
similarity index 99%
rename from EVT/EXAM/TOUCHKEY/User/system_ch32v20x.c
rename to EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c
index 37730a5..02c783f 100644
--- a/EVT/EXAM/TOUCHKEY/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+ //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.h b/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.h
new file mode 100644
index 0000000..9c8a3f7
--- /dev/null
+++ b/EVT/EXAM/USART/USART_Idle_Recv/User/system_ch32v20x.h
@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H 
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
diff --git a/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_Interrupt/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_MultiProcessorCommunication/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_Polling/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_Printf/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c
index 37730a5..8d3a568 100644
--- a/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c
+++ b/EVT/EXAM/USART/USART_SynchronousMode/User/system_ch32v20x.c
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
  */
 static void SetSysClock(void)
 {
+  //GPIO_IPD_Unused();
 #ifdef SYSCLK_FREQ_HSE
     SetSysClockToHSE();
 #elif defined SYSCLK_FREQ_48MHz_HSE
diff --git a/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/usb_prop.c
index df43f43..04d5e45 100644
--- a/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/CH372/User/USBLIB/CONFIG/usb_prop.c
@@ -215,39 +215,41 @@ void USBD_Reset(void)
   _ClearDTOG_TX(ENDP0);
 
 
-    SetEPType(ENDP1, EP_BULK);
-    SetEPTxStatus(ENDP1, EP_TX_DIS);
-    SetEPRxAddr(ENDP1, ENDP1_RXADDR);
-    SetEPRxCount(ENDP1, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP1, EP_RX_VALID );
-    _ClearDTOG_TX(ENDP1);
-    _ClearDTOG_RX(ENDP1);
+  SetEPType(ENDP1, EP_BULK);
+  SetEPTxStatus(ENDP1, EP_TX_DIS);
+  SetEPRxAddr(ENDP1, ENDP1_RXADDR);
+  SetEPRxCount(ENDP1, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP1, EP_RX_VALID );
+  _ClearDTOG_TX(ENDP1);
+  _ClearDTOG_RX(ENDP1);
 
-    SetEPType(ENDP2, EP_BULK);
-    SetEPTxStatus(ENDP2, EP_TX_NAK);
-    SetEPTxAddr(ENDP2, ENDP2_TXADDR);
-    SetEPRxStatus(ENDP2,EP_RX_DIS);
-    _ClearDTOG_RX(ENDP2);
-    _ClearDTOG_TX(ENDP2);
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPRxStatus(ENDP2,EP_RX_DIS);
+  _ClearDTOG_RX(ENDP2);
+  _ClearDTOG_TX(ENDP2);
 
-    SetEPType(ENDP3, EP_BULK);
-    SetEPTxStatus(ENDP3, EP_TX_DIS);
-    SetEPRxAddr(ENDP3, ENDP3_RXADDR);
-    SetEPRxCount(ENDP3, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP3, EP_RX_VALID);
-    _ClearDTOG_TX(ENDP3);
-    _ClearDTOG_RX(ENDP3);
+  SetEPType(ENDP3, EP_BULK);
+  SetEPTxStatus(ENDP3, EP_TX_DIS);
+  SetEPRxAddr(ENDP3, ENDP3_RXADDR);
+  SetEPRxCount(ENDP3, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP3, EP_RX_VALID);
+  _ClearDTOG_TX(ENDP3);
+  _ClearDTOG_RX(ENDP3);
 
-    SetEPType(ENDP4, EP_BULK);
-    SetEPTxStatus(ENDP4, EP_TX_NAK);
-    SetEPTxAddr(ENDP4, ENDP4_TXADDR);
-    SetEPRxStatus(ENDP4,EP_RX_DIS);
-    _ClearDTOG_RX(ENDP4);
-    _ClearDTOG_TX(ENDP4);
+  SetEPType(ENDP4, EP_BULK);
+  SetEPTxStatus(ENDP4, EP_TX_NAK);
+  SetEPTxAddr(ENDP4, ENDP4_TXADDR);
+  SetEPRxStatus(ENDP4,EP_RX_DIS);
+  _ClearDTOG_RX(ENDP4);
+  _ClearDTOG_TX(ENDP4);
 
-    SetDeviceAddress(0);
+  SetDeviceAddress(0);
 
-    bDeviceState = ATTACHED;
+  USBD_Endp2_Busy = 0;
+
+  bDeviceState = ATTACHED;
 }
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/usb_prop.c
index 487f639..1f26944 100644
--- a/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/CompatibilityHID/User/USBLIB/CONFIG/usb_prop.c
@@ -24,6 +24,8 @@ __attribute__ ((aligned(4))) uint8_t Data_Buffer[DEF_RING_BUFFER_SIZE];
 
 uint8_t Request = 0;
 
+
+extern uint8_t USBD_Endp2_Busy;
 volatile uint8_t HID_Idle_Value[2] = {0};
 volatile uint8_t HID_Protocol_Value[2] = {0};
 
@@ -237,24 +239,26 @@ void USBD_Reset(void)
   _ClearDTOG_RX(ENDP0);
   _ClearDTOG_TX(ENDP0);
 
-    SetEPType(ENDP1, EP_INTERRUPT);
-    SetEPTxStatus(ENDP1, EP_TX_DIS);
-    SetEPRxAddr(ENDP1, ENDP1_RXADDR);
-    SetEPRxCount(ENDP1, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP1, EP_RX_VALID );
-    _ClearDTOG_TX(ENDP1);
-    _ClearDTOG_RX(ENDP1);
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxStatus(ENDP1, EP_TX_DIS);
+  SetEPRxAddr(ENDP1, ENDP1_RXADDR);
+  SetEPRxCount(ENDP1, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP1, EP_RX_VALID );
+  _ClearDTOG_TX(ENDP1);
+  _ClearDTOG_RX(ENDP1);
 
-    SetEPType(ENDP2, EP_INTERRUPT);
-    SetEPTxAddr(ENDP2, ENDP2_TXADDR);
-    SetEPTxStatus(ENDP2, EP_TX_NAK);
-    SetEPRxStatus(ENDP2,EP_RX_DIS);
-    _ClearDTOG_TX(ENDP2);
-    _ClearDTOG_RX(ENDP2);
-    
-    SetDeviceAddress(0);
+  SetEPType(ENDP2, EP_INTERRUPT);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  SetEPRxStatus(ENDP2,EP_RX_DIS);
+  _ClearDTOG_TX(ENDP2);
+  _ClearDTOG_RX(ENDP2);
+  
+  SetDeviceAddress(0);
 
-    bDeviceState = ATTACHED;
+  USBD_Endp2_Busy = 0;
+
+  bDeviceState = ATTACHED;
 }
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c b/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c
index 651cf1a..89b9f9e 100644
--- a/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c
+++ b/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/hw_config.c
@@ -80,13 +80,13 @@ void Set_USBConfig( )
  */
 void Enter_LowPowerMode(void)
 {  
+	bDeviceState = SUSPENDED;
  	printf("usb enter low power mode\r\n");
 	USBD_Sleep_Status |= 0x02;
 	if (USBD_Sleep_Status == 0x03)
 	{
 		MCU_Sleep_Wakeup_Operate();
 	}
-	bDeviceState = SUSPENDED;
 } 
 
 /*******************************************************************************
@@ -119,20 +119,18 @@ void USB_Interrupts_Config(void)
 
 	EXTI_ClearITPendingBit(EXTI_Line18);
 	EXTI_InitStructure.EXTI_Line = EXTI_Line18; 
-	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+	EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Event;
 	EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;	
 	EXTI_InitStructure.EXTI_LineCmd = ENABLE;
 	EXTI_Init(&EXTI_InitStructure); 	 
+    
+    EXTI->INTENR |= EXTI_INTENR_MR18;
 
 	NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;	
 	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
 	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
 	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
 	NVIC_Init(&NVIC_InitStructure);
-	
-	NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;  
-	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-	NVIC_Init(&NVIC_InitStructure);   
 }	
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/usb_prop.c
index 639c589..b5deb69 100644
--- a/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/CompositeKM/User/USBLIB/CONFIG/usb_prop.c
@@ -226,21 +226,24 @@ void USBD_Reset(void)
   _ClearDTOG_RX(ENDP0);
   _ClearDTOG_TX(ENDP0);
 
-    SetEPType(ENDP1, EP_INTERRUPT);
-    SetEPTxAddr(ENDP1, ENDP1_TXADDR);
-    SetEPTxStatus(ENDP1, EP_TX_NAK);
-    _ClearDTOG_TX(ENDP1);
-    _ClearDTOG_RX(ENDP1);
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  _ClearDTOG_TX(ENDP1);
+  _ClearDTOG_RX(ENDP1);
 
-    SetEPType(ENDP2, EP_INTERRUPT);
-    SetEPTxAddr(ENDP2, ENDP2_TXADDR);
-    SetEPTxStatus(ENDP2, EP_TX_NAK);
-    _ClearDTOG_TX(ENDP2);
-    _ClearDTOG_RX(ENDP2);
-    
-    SetDeviceAddress(0);
+  SetEPType(ENDP2, EP_INTERRUPT);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  _ClearDTOG_TX(ENDP2);
+  _ClearDTOG_RX(ENDP2);
+  
+  SetDeviceAddress(0);
 
-    bDeviceState = ATTACHED;
+  USBD_Endp1_Busy = 0;
+  USBD_Endp2_Busy = 0;
+
+  bDeviceState = ATTACHED;
 }
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBD/CompositeKM/User/usbd_compostie_km.c b/EVT/EXAM/USB/USBD/CompositeKM/User/usbd_compostie_km.c
index 8d02914..262f240 100644
--- a/EVT/EXAM/USB/USBD/CompositeKM/User/usbd_compostie_km.c
+++ b/EVT/EXAM/USB/USBD/CompositeKM/User/usbd_compostie_km.c
@@ -661,11 +661,17 @@ void MS_Scan_Handle( void )
  */
 void MCU_Sleep_Wakeup_Operate( void )
 {
+    printf( "Sleep\r\n" );
+    __disable_irq();
+    RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE);
     EXTI_ClearFlag( EXTI_Line12 | EXTI_Line13 | EXTI_Line14 | EXTI_Line15 );
     EXTI_ClearFlag( EXTI_Line4 | EXTI_Line5 | EXTI_Line6 | EXTI_Line7 );
-
-//    printf( "Sleep\r\n" );
-    __WFE( );
+    
+    PWR_EnterSTOPMode(PWR_Regulator_LowPower,PWR_STOPEntry_WFE);
+    
+    SystemInit();
+    SystemCoreClockUpdate();
+    Set_USBConfig();
     
     if( EXTI_GetFlagStatus( EXTI_Line12 | EXTI_Line13 | EXTI_Line14 | EXTI_Line15 ) != RESET  )
     {
@@ -677,8 +683,13 @@ void MCU_Sleep_Wakeup_Operate( void )
         EXTI_ClearFlag( EXTI_Line4 | EXTI_Line5 | EXTI_Line6 | EXTI_Line7 );
         Resume(RESUME_INTERNAL);
     }
-//    printf( "Wake\r\n" );
-}
+    else if(EXTI_GetFlagStatus(EXTI_Line18) != RESET )
+    {
+        EXTI_ClearFlag( EXTI_Line18 );
+        printf("USB Wake Up\n");
+    }
+    __enable_irq( );
+    printf( "Wake\r\n" );}
 
 
 
diff --git a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/usb_prop.c
index caf964b..5d8f52b 100644
--- a/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/MSC_CD-ROM/User/USBLIB/CONFIG/usb_prop.c
@@ -185,40 +185,40 @@ void USBD_init(void)
  */
 void USBD_Reset(void)
 {
-    pInformation->Current_Configuration = 0;
-    pInformation->Current_Feature = USBD_ConfigDescriptor[7];
-    pInformation->Current_Interface = 0;
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Feature = USBD_ConfigDescriptor[7];
+  pInformation->Current_Interface = 0;
 
-    SetBTABLE(BTABLE_ADDRESS);
+  SetBTABLE(BTABLE_ADDRESS);
 
-    SetEPType(ENDP0, EP_CONTROL);
-    SetEPTxStatus(ENDP0, EP_TX_STALL);
-    SetEPRxAddr(ENDP0, ENDP0_RXADDR);
-    SetEPTxAddr(ENDP0, ENDP0_TXADDR);
-    Clear_Status_Out(ENDP0);
-    SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
-    SetEPRxValid(ENDP0);
-    _ClearDTOG_RX(ENDP0);
-    _ClearDTOG_TX(ENDP0);
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+  _ClearDTOG_RX(ENDP0);
+  _ClearDTOG_TX(ENDP0);
 
-    SetEPType(ENDP2, EP_BULK);
-    SetEPTxAddr(ENDP2, ENDP2_TXADDR);
-    SetEPTxStatus(ENDP2, EP_TX_NAK);
-    SetEPRxStatus(ENDP2,EP_RX_DIS);
-    _ClearDTOG_TX(ENDP2);
-    _ClearDTOG_RX(ENDP2);
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  SetEPRxStatus(ENDP2,EP_RX_DIS);
+  _ClearDTOG_TX(ENDP2);
+  _ClearDTOG_RX(ENDP2);
 
-    SetEPType(ENDP3, EP_BULK);
-    SetEPTxStatus(ENDP3, EP_TX_DIS);
-    SetEPRxAddr(ENDP3, ENDP3_RXADDR);
-    SetEPRxCount(ENDP3, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP3, EP_RX_VALID );
-    _ClearDTOG_TX(ENDP3);
-    _ClearDTOG_RX(ENDP3);
-    
-    SetDeviceAddress(0);
+  SetEPType(ENDP3, EP_BULK);
+  SetEPTxStatus(ENDP3, EP_TX_DIS);
+  SetEPRxAddr(ENDP3, ENDP3_RXADDR);
+  SetEPRxCount(ENDP3, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP3, EP_RX_VALID );
+  _ClearDTOG_TX(ENDP3);
+  _ClearDTOG_RX(ENDP3);
+  
+  SetDeviceAddress(0);
 
-    bDeviceState = ATTACHED;
+  bDeviceState = ATTACHED;
 }
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/usb_prop.c
index c5f7065..a9f434e 100644
--- a/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/MSC_U-Disk/User/USBLIB/CONFIG/usb_prop.c
@@ -185,40 +185,40 @@ void USBD_init(void)
  */
 void USBD_Reset(void)
 {
-    pInformation->Current_Configuration = 0;
-    pInformation->Current_Feature = USBD_ConfigDescriptor[7];
-    pInformation->Current_Interface = 0;
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Feature = USBD_ConfigDescriptor[7];
+  pInformation->Current_Interface = 0;
 
-    SetBTABLE(BTABLE_ADDRESS);
+  SetBTABLE(BTABLE_ADDRESS);
 
-    SetEPType(ENDP0, EP_CONTROL);
-    SetEPTxStatus(ENDP0, EP_TX_STALL);
-    SetEPRxAddr(ENDP0, ENDP0_RXADDR);
-    SetEPTxAddr(ENDP0, ENDP0_TXADDR);
-    Clear_Status_Out(ENDP0);
-    SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
-    SetEPRxValid(ENDP0);
-    _ClearDTOG_RX(ENDP0);
-    _ClearDTOG_TX(ENDP0);
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+  _ClearDTOG_RX(ENDP0);
+  _ClearDTOG_TX(ENDP0);
 
-    SetEPType(ENDP2, EP_BULK);
-    SetEPTxAddr(ENDP2, ENDP2_TXADDR);
-    SetEPTxStatus(ENDP2, EP_TX_NAK);
-    SetEPRxStatus(ENDP2,EP_RX_DIS);
-    _ClearDTOG_TX(ENDP2);
-    _ClearDTOG_RX(ENDP2);
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  SetEPRxStatus(ENDP2,EP_RX_DIS);
+  _ClearDTOG_TX(ENDP2);
+  _ClearDTOG_RX(ENDP2);
 
-    SetEPType(ENDP3, EP_BULK);
-    SetEPTxStatus(ENDP3, EP_TX_DIS);
-    SetEPRxAddr(ENDP3, ENDP3_RXADDR);
-    SetEPRxCount(ENDP3, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP3, EP_RX_VALID );
-    _ClearDTOG_TX(ENDP3);
-    _ClearDTOG_RX(ENDP3);
-    
-    SetDeviceAddress(0);
+  SetEPType(ENDP3, EP_BULK);
+  SetEPTxStatus(ENDP3, EP_TX_DIS);
+  SetEPRxAddr(ENDP3, ENDP3_RXADDR);
+  SetEPRxCount(ENDP3, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP3, EP_RX_VALID );
+  _ClearDTOG_TX(ENDP3);
+  _ClearDTOG_RX(ENDP3);
+  
+  SetDeviceAddress(0);
 
-    bDeviceState = ATTACHED;
+  bDeviceState = ATTACHED;
 }
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_endp.c b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_endp.c
index 9176bc8..f80459c 100644
--- a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_endp.c
+++ b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_endp.c
@@ -22,7 +22,7 @@ uint8_t USBD_Endp3_Busy;
 uint16_t USB_Rx_Cnt = 0; 
 uint8_t HID_Buffer[DEF_USBD_MAX_PACK_SIZE];
 /*********************************************************************
- * @fn      EP2_IN_Callback
+ * @fn      EP1_IN_Callback
  *
  * @brief  Endpoint 1 IN.
  *
diff --git a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_prop.c
index 0b3ee96..fd7c466 100644
--- a/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/SimulateCDC-HID/User/USBLIB/CONFIG/usb_prop.c
@@ -210,57 +210,59 @@ void USBD_init(void)
  */
 void USBD_Reset(void)
 {
-    pInformation->Current_Configuration = 0;
-    pInformation->Current_Feature = USBD_ConfigDescriptor[7];
-    pInformation->Current_Interface = 0;
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Feature = USBD_ConfigDescriptor[7];
+  pInformation->Current_Interface = 0;
 
-    SetBTABLE(BTABLE_ADDRESS);
+  SetBTABLE(BTABLE_ADDRESS);
 
-    SetEPType(ENDP0, EP_CONTROL);
-    SetEPTxStatus(ENDP0, EP_TX_STALL);
-    SetEPRxAddr(ENDP0, ENDP0_RXADDR);
-    SetEPTxAddr(ENDP0, ENDP0_TXADDR);
-    Clear_Status_Out(ENDP0);
-    SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
-    SetEPRxValid(ENDP0);
-    _ClearDTOG_RX(ENDP0);
-    _ClearDTOG_TX(ENDP0);
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+  _ClearDTOG_RX(ENDP0);
+  _ClearDTOG_TX(ENDP0);
 
-    SetEPType(ENDP1, EP_INTERRUPT);
-    SetEPTxStatus(ENDP1, EP_TX_NAK);
-    SetEPTxAddr(ENDP1, ENDP1_TXADDR);
-    SetEPRxStatus(ENDP1, EP_RX_DIS);
-    _ClearDTOG_TX(ENDP1);
-    _ClearDTOG_RX(ENDP1);
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+  _ClearDTOG_TX(ENDP1);
+  _ClearDTOG_RX(ENDP1);
 
-    SetEPType(ENDP2, EP_BULK);
-    SetEPTxStatus(ENDP2, EP_TX_DIS);
-    SetEPRxAddr(ENDP2, ENDP2_RXADDR);
-    SetEPRxCount(ENDP2, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP2,EP_RX_VALID);
-    _ClearDTOG_RX(ENDP2);
-    _ClearDTOG_TX(ENDP2);
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxStatus(ENDP2, EP_TX_DIS);
+  SetEPRxAddr(ENDP2, ENDP2_RXADDR);
+  SetEPRxCount(ENDP2, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP2,EP_RX_VALID);
+  _ClearDTOG_RX(ENDP2);
+  _ClearDTOG_TX(ENDP2);
 
-    SetEPType(ENDP3, EP_BULK);
-    SetEPTxStatus(ENDP3, EP_TX_NAK);
-    SetEPTxAddr(ENDP3, ENDP3_TXADDR);
-    SetEPRxStatus(ENDP3, EP_RX_DIS);
-    _ClearDTOG_TX(ENDP3);
-    _ClearDTOG_RX(ENDP3);
-    USBD_Endp3_Busy = 0;
-	
-	SetEPType(ENDP4, EP_INTERRUPT);
-	SetEPTxStatus(ENDP4, EP_TX_NAK);
-	SetEPTxAddr(ENDP4, ENDP4_TXADDR);
-	SetEPRxAddr(ENDP4, ENDP4_RXADDR);
-	SetEPRxCount(ENDP4, DEF_USBD_MAX_PACK_SIZE);
-	SetEPRxStatus(ENDP4, EP_RX_VALID );
-	_ClearDTOG_TX(ENDP4);
-	_ClearDTOG_RX(ENDP4);
+  SetEPType(ENDP3, EP_BULK);
+  SetEPTxStatus(ENDP3, EP_TX_NAK);
+  SetEPTxAddr(ENDP3, ENDP3_TXADDR);
+  SetEPRxStatus(ENDP3, EP_RX_DIS);
+  _ClearDTOG_TX(ENDP3);
+  _ClearDTOG_RX(ENDP3);
+  USBD_Endp3_Busy = 0;
 
-    SetDeviceAddress(0);
+  SetEPType(ENDP4, EP_INTERRUPT);
+  SetEPTxStatus(ENDP4, EP_TX_NAK);
+  SetEPTxAddr(ENDP4, ENDP4_TXADDR);
+  SetEPRxAddr(ENDP4, ENDP4_RXADDR);
+  SetEPRxCount(ENDP4, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP4, EP_RX_VALID );
+  _ClearDTOG_TX(ENDP4);
+  _ClearDTOG_RX(ENDP4);
 
-    bDeviceState = ATTACHED;
+  SetDeviceAddress(0);
+
+  USBD_Endp3_Busy = 0;
+
+  bDeviceState = ATTACHED;
 }
 
 /*********************************************************************
diff --git a/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/usb_prop.c b/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/usb_prop.c
index af6f693..d5609e5 100644
--- a/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/usb_prop.c
+++ b/EVT/EXAM/USB/USBD/SimulateCDC/User/USBLIB/CONFIG/usb_prop.c
@@ -193,7 +193,7 @@ void USBD_init(void)
 /*******************************************************************************
  * @fn      USBD_Reset
  *
- * @brief   Virtual_Com_Port Mouse reset routine
+ * @brief   USBD reset routine
  *
  * @return  None.
  */
@@ -215,33 +215,33 @@ void USBD_Reset(void)
   _ClearDTOG_RX(ENDP0);
   _ClearDTOG_TX(ENDP0);
 
-    SetEPType(ENDP1, EP_INTERRUPT);
-    SetEPTxStatus(ENDP1, EP_TX_NAK);
-    SetEPTxAddr(ENDP1, ENDP1_TXADDR);
-    SetEPRxStatus(ENDP1, EP_RX_DIS);
-    _ClearDTOG_TX(ENDP1);
-    _ClearDTOG_RX(ENDP1);
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+  _ClearDTOG_TX(ENDP1);
+  _ClearDTOG_RX(ENDP1);
 
-    SetEPType(ENDP2, EP_BULK);
-    SetEPTxStatus(ENDP2, EP_TX_DIS);
-    SetEPRxAddr(ENDP2, ENDP2_RXADDR);
-    SetEPRxCount(ENDP2, DEF_USBD_MAX_PACK_SIZE);
-    SetEPRxStatus(ENDP2,EP_RX_VALID);
-    _ClearDTOG_RX(ENDP2);
-    _ClearDTOG_TX(ENDP2);
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxStatus(ENDP2, EP_TX_DIS);
+  SetEPRxAddr(ENDP2, ENDP2_RXADDR);
+  SetEPRxCount(ENDP2, DEF_USBD_MAX_PACK_SIZE);
+  SetEPRxStatus(ENDP2,EP_RX_VALID);
+  _ClearDTOG_RX(ENDP2);
+  _ClearDTOG_TX(ENDP2);
 
-    SetEPType(ENDP3, EP_BULK);
-    SetEPTxStatus(ENDP3, EP_TX_NAK);
-    SetEPTxAddr(ENDP3, ENDP3_TXADDR);
-    SetEPRxStatus(ENDP3, EP_RX_DIS);
-    _ClearDTOG_TX(ENDP3);
-    _ClearDTOG_RX(ENDP3);
-    
-    USBD_Endp3_Busy = 0;
+  SetEPType(ENDP3, EP_BULK);
+  SetEPTxStatus(ENDP3, EP_TX_NAK);
+  SetEPTxAddr(ENDP3, ENDP3_TXADDR);
+  SetEPRxStatus(ENDP3, EP_RX_DIS);
+  _ClearDTOG_TX(ENDP3);
+  _ClearDTOG_RX(ENDP3);
+  
+  SetDeviceAddress(0);
 
-    SetDeviceAddress(0);
+  USBD_Endp3_Busy = 0;
 
-    bDeviceState = ATTACHED;
+  bDeviceState = ATTACHED;
 }
 
 /*******************************************************************************
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject
index c480849..d1fcf8a 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/.cproject
@@ -139,15 +139,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="obj">
-			<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
-		</configuration>
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-	</storageModule>
+	
 </cproject>
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usb.h
deleted file mode 100644
index 201a5ce..0000000
--- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
- * File Name          : ch32v20x_usb.h
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2020/04/30
- * Description        : This file contains all the functions prototypes for the USB
- *                      firmware library.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __CH32V20X_USB_H
-#define __CH32V20X_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header File */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
-/* USB PID */
-#ifndef USB_PID_SETUP
-#define USB_PID_NULL                0x00
-#define USB_PID_SOF                 0x05
-#define USB_PID_SETUP               0x0D
-#define USB_PID_IN                  0x09
-#define USB_PID_OUT                 0x01
-#define USB_PID_NYET                0x06
-#define USB_PID_ACK                 0x02
-#define USB_PID_NAK                 0x0A
-#define USB_PID_STALL               0x0E
-#define USB_PID_DATA0               0x03
-#define USB_PID_DATA1               0x0B
-#define USB_PID_PRE                 0x0C
-#endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_CH32V20X_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usbfs_device.c
index 7664a04..93818c9 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/ch32v20x_usbfs_device.c
@@ -81,7 +81,6 @@ void USBFS_RCC_Init(void)
  */
 void USBFS_Device_Endp_Init( void )
 {
-    uint8_t i;
 
     USBOTG_FS->UEP4_1_MOD = USBFS_UEP4_TX_EN|USBFS_UEP1_RX_EN;
     USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_TX_EN|USBFS_UEP3_RX_EN;
@@ -113,7 +112,7 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP6_TX_CTRL = USBFS_UEP_T_RES_NAK;
 
     /* Clear End-points Busy Status */
-    for( i=0; i<DEF_UEP_NUM; i++ )
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
     {
         USBFS_Endp_Busy[ i ] = 0;
     }
@@ -409,7 +408,7 @@ void USBHD_IRQHandler( void )
                                 USBFS_EP6_Buf[i] = ~USBFS_EP5_Buf[i];
                             }
                             USBOTG_FS->UEP6_TX_LEN = len;
-                            USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK;
+                            USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK;
                         }
                         break;
                 }
@@ -800,6 +799,11 @@ void USBHD_IRQHandler( void )
     else if( intflag & USBFS_UIF_BUS_RST )
     {
         /* usb reset interrupt processing */
+        USBFS_DevConfig = 0;
+        USBFS_DevAddr = 0;
+        USBFS_DevSleepStatus = 0;
+        USBFS_DevEnumStatus = 0;
+
         USBOTG_FS->DEV_ADDR = 0;
         USBFS_Device_Endp_Init( );
         USBOTG_FS->INT_FG = USBFS_UIF_BUS_RST;
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/usb_desc.c b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/usb_desc.c
index 59fa021..6ebc490 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/usb_desc.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CH372Device/User/usb_desc.c
@@ -113,7 +113,7 @@ const uint8_t  MyManuInfo[] =
 /* Product Information */
 const uint8_t  MyProdInfo[] =
 {
-    0x12, 0x03, 'C', 0, 'H', 0, '3', 0, '2', 0, 'V', 0, '1', 0
+    0x12, 0x03, 'C', 0, 'H', 0, '3', 0, '2', 0, 'V', 0, '2', 0
               , '0', 0, 'x', 0
 };
 
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/.cproject b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/.cproject
index 9a2f25a..44d5301 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/.cproject
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/.cproject
@@ -139,15 +139,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="obj">
-			<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
-		</configuration>
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-	</storageModule>
+	
 </cproject>
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usb.h
deleted file mode 100644
index 7946dd2..0000000
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,531 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v20x_usb.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V20x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-
-
-#ifndef __CH32V20x_USB_H
-#define __CH32V20x_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header Files */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
-/* USB PID */
-#ifndef USB_PID_SETUP
-#define USB_PID_NULL                0x00
-#define USB_PID_SOF                 0x05
-#define USB_PID_SETUP               0x0D
-#define USB_PID_IN                  0x09
-#define USB_PID_OUT                 0x01
-#define USB_PID_NYET                0x06
-#define USB_PID_ACK                 0x02
-#define USB_PID_NAK                 0x0A
-#define USB_PID_STALL               0x0E
-#define USB_PID_DATA0               0x03
-#define USB_PID_DATA1               0x0B
-#define USB_PID_PRE                 0x0C
-#endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V20x_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c
index 1ae2738..47e64d8 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/ch32v20x_usbfs_device.c
@@ -96,7 +96,11 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP0_RX_CTRL = USBFS_UEP_R_RES_ACK;
     USBOTG_FS->UEP1_RX_CTRL = USBFS_UEP_R_RES_ACK;
     USBOTG_FS->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK;
-	USBFS_Endp_Busy[ 2 ] = 0;
+    /* Clear End-points Busy Status */
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
+    {
+        USBFS_Endp_Busy[ i ] = 0;
+    }
 }
 
 /*********************************************************************
@@ -796,6 +800,7 @@ void USBHD_IRQHandler( void )
         USBFS_DevAddr = 0;
         USBFS_DevSleepStatus = 0;
         USBFS_DevEnumStatus = 0;
+
         USBOTG_FS->DEV_ADDR = 0;
         USBFS_Device_Endp_Init( );
         USBOTG_FS->INT_FG = USBFS_UIF_BUS_RST;
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/.cproject b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/.cproject
index 3a5ad61..f89fb10 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/.cproject
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/.cproject
@@ -140,15 +140,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="obj">
-			<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
-		</configuration>
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-	</storageModule>
+	
 </cproject>
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usb.h
deleted file mode 100644
index 0856e0b..0000000
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v20x_usb.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V20x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-
-
-#ifndef __CH32V20x_USB_H
-#define __CH32V20x_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header Files */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
- /* USB Endpoint0 Size */
- #ifndef DEFAULT_ENDP0_SIZE
- #define DEFAULT_ENDP0_SIZE          8
- #endif
-
- /* USB PID */
- #ifndef USB_PID_SETUP
- #define USB_PID_NULL                0x00
- #define USB_PID_SOF                 0x05
- #define USB_PID_SETUP               0x0D
- #define USB_PID_IN                  0x09
- #define USB_PID_OUT                 0x01
- #define USB_PID_NYET                0x06
- #define USB_PID_ACK                 0x02
- #define USB_PID_NAK                 0x0A
- #define USB_PID_STALL               0x0E
- #define USB_PID_DATA0               0x03
- #define USB_PID_DATA1               0x0B
- #define USB_PID_DATA2               0x07
- #define USB_PID_MDATA               0x0F
- #define USB_PID_PRE                 0x0C
- #define USB_PID_SPLIT               0x08
- #define USB_PID_PING                0x04
- #endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V20x_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c
index f14c3c1..e1f3eda 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/ch32v20x_usbfs_device.c
@@ -95,6 +95,12 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK;
     USBOTG_FS->UEP1_TX_CTRL = USBFS_UEP_T_RES_NAK;
     USBOTG_FS->UEP2_TX_CTRL = USBFS_UEP_T_RES_NAK;
+
+    /* Clear End-points Busy Status */
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
+    {
+        USBFS_Endp_Busy[ i ] = 0;
+    }    
 }
 
 /*********************************************************************
@@ -847,7 +853,7 @@ void USBHD_IRQHandler( void )
 void USBFS_Send_Resume( void )
 {
     USBOTG_FS->UDEV_CTRL ^= USBFS_UD_LOW_SPEED;
-    Delay_Ms( 5 );
+    Delay_Ms( 8 );
     USBOTG_FS->UDEV_CTRL ^= USBFS_UD_LOW_SPEED;
     Delay_Ms( 1 );
 }
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/usbd_compostie_km.c b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/usbd_compostie_km.c
index 0a8f112..8b60162 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/usbd_compostie_km.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/CompositeKM/User/usbd_compostie_km.c
@@ -563,7 +563,7 @@ void MS_Sleep_Wakeup_Cfg( void )
     EXTI_InitStructure.EXTI_LineCmd = ENABLE;
     EXTI_Init( &EXTI_InitStructure );
 
-    EXTI->INTENR |= EXTI_INTENR_MR4 | EXTI_INTENR_MR5 | EXTI_INTENR_MR6 | EXTI_INTENR_MR7;
+//    EXTI->INTENR |= EXTI_INTENR_MR4 | EXTI_INTENR_MR5 | EXTI_INTENR_MR6 | EXTI_INTENR_MR7;
 }
 
 /*********************************************************************
@@ -684,11 +684,15 @@ void USB_Sleep_Wakeup_CFG( void )
  */
 void MCU_Sleep_Wakeup_Operate( void )
 {
+    printf( "Sleep\r\n" );
+    __disable_irq();
     EXTI_ClearFlag( EXTI_Line12 | EXTI_Line13 | EXTI_Line14 | EXTI_Line15 );
     EXTI_ClearFlag( EXTI_Line4 | EXTI_Line5 | EXTI_Line6 | EXTI_Line7 );
 
-//    printf( "Sleep\r\n" );
-    __WFE( );
+    PWR_EnterSTOPMode(PWR_Regulator_LowPower,PWR_STOPEntry_WFE);
+    SystemInit();
+    SystemCoreClockUpdate();
+    USBFS_RCC_Init();
 
     if( EXTI_GetFlagStatus( EXTI_Line12 | EXTI_Line13 | EXTI_Line14 | EXTI_Line15 ) != RESET  )
     {
@@ -700,5 +704,6 @@ void MCU_Sleep_Wakeup_Operate( void )
         EXTI_ClearFlag( EXTI_Line4 | EXTI_Line5 | EXTI_Line6 | EXTI_Line7 );
         USBFS_Send_Resume( );
     }
-//    printf( "Wake\r\n" );
+    __enable_irq( );
+    printf( "Wake\r\n" );
 }
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usb.h
deleted file mode 100644
index 201a5ce..0000000
--- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
- * File Name          : ch32v20x_usb.h
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2020/04/30
- * Description        : This file contains all the functions prototypes for the USB
- *                      firmware library.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __CH32V20X_USB_H
-#define __CH32V20X_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header File */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
-/* USB PID */
-#ifndef USB_PID_SETUP
-#define USB_PID_NULL                0x00
-#define USB_PID_SOF                 0x05
-#define USB_PID_SETUP               0x0D
-#define USB_PID_IN                  0x09
-#define USB_PID_OUT                 0x01
-#define USB_PID_NYET                0x06
-#define USB_PID_ACK                 0x02
-#define USB_PID_NAK                 0x0A
-#define USB_PID_STALL               0x0E
-#define USB_PID_DATA0               0x03
-#define USB_PID_DATA1               0x0B
-#define USB_PID_PRE                 0x0C
-#endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_CH32V20X_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c
index f328e1e..0dc5b66 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/ch32v20x_usbfs_device.c
@@ -75,7 +75,6 @@ void USBFS_RCC_Init( void )
  */
 void USBFS_Device_Endp_Init( void )
 {
-    uint8_t i;
 
     USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_TX_EN|USBFS_UEP3_RX_EN;
 
@@ -92,7 +91,7 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP2_TX_LEN = 0;
 
     /* Clear End-points Busy Status */
-    for( i=0; i<DEF_UEP_NUM; i++ )
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
     {
         USBFS_Endp_Busy[ i ] = 0;
     }
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/.cproject b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/.cproject
index a324419..dd2df04 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/.cproject
+++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/.cproject
@@ -139,15 +139,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="obj">
-			<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
-		</configuration>
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-	</storageModule>
+	
 </cproject>
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usb.h
deleted file mode 100644
index 201a5ce..0000000
--- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/********************************** (C) COPYRIGHT  *******************************
- * File Name          : ch32v20x_usb.h
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2020/04/30
- * Description        : This file contains all the functions prototypes for the USB
- *                      firmware library.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __CH32V20X_USB_H
-#define __CH32V20X_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header File */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
-/* USB PID */
-#ifndef USB_PID_SETUP
-#define USB_PID_NULL                0x00
-#define USB_PID_SOF                 0x05
-#define USB_PID_SETUP               0x0D
-#define USB_PID_IN                  0x09
-#define USB_PID_OUT                 0x01
-#define USB_PID_NYET                0x06
-#define USB_PID_ACK                 0x02
-#define USB_PID_NAK                 0x0A
-#define USB_PID_STALL               0x0E
-#define USB_PID_DATA0               0x03
-#define USB_PID_DATA1               0x0B
-#define USB_PID_PRE                 0x0C
-#endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_CH32V20X_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c
index b82a51e..ab6bb31 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_U-Disk/User/ch32v20x_usbfs_device.c
@@ -75,7 +75,6 @@ void USBFS_RCC_Init( void )
  */
 void USBFS_Device_Endp_Init( void )
 {
-    uint8_t i;
 
     USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_TX_EN|USBFS_UEP3_RX_EN;
 
@@ -92,7 +91,7 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP2_TX_LEN = 0;
 
     /* Clear End-points Busy Status */
-    for( i=0; i<DEF_UEP_NUM; i++ )
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
     {
         USBFS_Endp_Busy[ i ] = 0;
     }
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c
index 83d9067..2b53421 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/ch32v20x_usbfs_device.c
@@ -85,7 +85,6 @@ void USBFS_RCC_Init( void )
  */
 void USBFS_Device_Endp_Init( void )
 {
-    uint8_t i;
 
     USBOTG_FS->UEP4_1_MOD = USBFS_UEP1_TX_EN|USBFS_UEP4_TX_EN|USBFS_UEP4_RX_EN;
     USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_RX_EN|USBFS_UEP3_TX_EN;
@@ -111,7 +110,7 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP4_TX_CTRL = USBFS_UEP_T_RES_NAK;
 
     /* Clear End-points Busy Status */
-    for( i=0; i<DEF_UEP_NUM; i++ )
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
     {
         USBFS_Endp_Busy[ i ] = 0;
     }
@@ -920,6 +919,11 @@ void USBHD_IRQHandler( void )
     else if( intflag & USBFS_UIF_BUS_RST )
     {
         /* usb reset interrupt processing */
+        USBFS_DevConfig = 0;
+        USBFS_DevAddr = 0;
+        USBFS_DevSleepStatus = 0;
+        USBFS_DevEnumStatus = 0;
+
         USBOTG_FS->DEV_ADDR = 0;
         USBFS_Device_Endp_Init( );
         UART2_ParaInit( 1 );
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c
index 6d8c7d7..4d25126 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c
@@ -112,7 +112,7 @@ const uint8_t  MyManuInfo[] =
 /* Product Information */
 const uint8_t  MyProdInfo[] =
 {
-    0x12, 0x03, 'C', 0, 'H', 0, '3', 0, '2', 0, 'V', 0, '1', 0
+    0x12, 0x03, 'C', 0, 'H', 0, '3', 0, '2', 0, 'V', 0, '2', 0
               , '0', 0, 'x', 0
 };
 
diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c
index 78bc2a4..4e20dc2 100644
--- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c
+++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/ch32v20x_usbfs_device.c
@@ -76,7 +76,6 @@ void USBFS_RCC_Init( void )
  */
 void USBFS_Device_Endp_Init( void )
 {
-    uint8_t i;
 
     USBOTG_FS->UEP4_1_MOD = USBFS_UEP1_TX_EN;
     USBOTG_FS->UEP2_3_MOD = USBFS_UEP2_RX_EN|USBFS_UEP3_TX_EN;
@@ -98,7 +97,7 @@ void USBFS_Device_Endp_Init( void )
     USBOTG_FS->UEP3_TX_CTRL = USBFS_UEP_T_RES_NAK;
 
     /* Clear End-points Busy Status */
-    for( i=0; i<DEF_UEP_NUM; i++ )
+    for(uint8_t i=0; i<DEF_UEP_NUM; i++ )
     {
         USBFS_Endp_Busy[ i ] = 0;
     }
@@ -757,6 +756,11 @@ void USBHD_IRQHandler( void )
     else if( intflag & USBFS_UIF_BUS_RST )
     {
         /* usb reset interrupt processing */
+        USBFS_DevConfig = 0;
+        USBFS_DevAddr = 0;
+        USBFS_DevSleepStatus = 0;
+        USBFS_DevEnumStatus = 0;
+
         USBOTG_FS->DEV_ADDR = 0;
         USBFS_Device_Endp_Init( );
         UART2_ParaInit( 1 );
diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/.cproject b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/.cproject
index 9a05a92..0954e25 100644
--- a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/.cproject
+++ b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/.cproject
@@ -44,12 +44,12 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id.226017994" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id" useByScannerDiscovery="false" value="512258282" valueType="string"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialized)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.783101988" name="No common unitialized (-fno-common)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.308634391" name="Extra Compressed extension (RVXW)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1685636" name="Small prologue/epilogue (-msave-restore)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/ADC_DMA}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/ADC_DMA}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU Make 构建器" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
 							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1244756189" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
@@ -152,5 +152,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_conf.h b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_conf.h
index d1eeb38..aaecc68 100644
--- a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_conf.h
+++ b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_conf.h
@@ -32,6 +32,7 @@
 #include "ch32v20x_wwdg.h"
 #include "ch32v20x_it.h"
 #include "ch32v20x_misc.h"
+#include "ch32v20x_usb.h"
 
 
 #endif /* __CH32V20x_CONF_H */
diff --git a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_usb.h
deleted file mode 100644
index 2d121bd..0000000
--- a/EVT/EXAM/USB/USBFS/HOST_IAP/HOST_IAP/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,539 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v20x_usb.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V20x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-
-
-#ifndef __CH32V20x_USB_H
-#define __CH32V20x_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header Files */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
-/* USB Endpoint0 Size */
-#ifndef DEFAULT_ENDP0_SIZE
-#define DEFAULT_ENDP0_SIZE          8          // default maximum packet size for endpoint 0
-#endif
-#ifndef MAX_PACKET_SIZE
-#define MAX_PACKET_SIZE             64         // maximum packet size
-#endif
-
-/* USB PID */
-#ifndef USB_PID_SETUP
-#define USB_PID_NULL                0x00
-#define USB_PID_SOF                 0x05
-#define USB_PID_SETUP               0x0D
-#define USB_PID_IN                  0x09
-#define USB_PID_OUT                 0x01
-#define USB_PID_NYET                0x06
-#define USB_PID_ACK                 0x02
-#define USB_PID_NAK                 0x0A
-#define USB_PID_STALL               0x0E
-#define USB_PID_DATA0               0x03
-#define USB_PID_DATA1               0x0B
-#define USB_PID_PRE                 0x0C
-#endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V20x_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/HOST_KM/.cproject b/EVT/EXAM/USB/USBFS/HOST_KM/.cproject
index ecb0810..66d3202 100644
--- a/EVT/EXAM/USB/USBFS/HOST_KM/.cproject
+++ b/EVT/EXAM/USB/USBFS/HOST_KM/.cproject
@@ -140,15 +140,5 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="obj">
-			<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
-		</configuration>
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/000"/>
-		</configuration>
-	</storageModule>
+	
 </cproject>
diff --git a/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c b/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c
index bd36c34..c387061 100644
--- a/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c
+++ b/EVT/EXAM/USB/USBFS/HOST_KM/User/USB_Host/ch32v20x_usbfs_host.c
@@ -58,22 +58,25 @@ void USBFS_Host_Init( FunctionalState sta )
 {
     if( sta == ENABLE )
     {
-        /* Reset USB module */
-        USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
-        Delay_Us( 10 );
-        USBOTG_H_FS->BASE_CTRL = 0;
-
-        /* Initialize USB host configuration */
-        USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
+        USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE;
+        USBOTG_H_FS->HOST_CTRL = 0;
+        USBOTG_H_FS->DEV_ADDR = 0;
         USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN;
+
         USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf;
         USBOTG_H_FS->HOST_TX_DMA = (uint32_t)USBFS_TX_Buf;
+
+        USBOTG_H_FS->HOST_RX_CTRL = 0;
+        USBOTG_H_FS->HOST_TX_CTRL = 0;
+        USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
+
+        USBOTG_H_FS->INT_FG = 0xFF;
+
+        USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT;
     }
     else
     {
         USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
-        Delay_Us( 10 );
-        USBOTG_H_FS->BASE_CTRL = 0;
     }
 }
 
diff --git a/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_usb.h
deleted file mode 100644
index 0856e0b..0000000
--- a/EVT/EXAM/USB/USBFS/HOST_KM/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v20x_usb.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V20x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-
-
-#ifndef __CH32V20x_USB_H
-#define __CH32V20x_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header Files */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
- /* USB Endpoint0 Size */
- #ifndef DEFAULT_ENDP0_SIZE
- #define DEFAULT_ENDP0_SIZE          8
- #endif
-
- /* USB PID */
- #ifndef USB_PID_SETUP
- #define USB_PID_NULL                0x00
- #define USB_PID_SOF                 0x05
- #define USB_PID_SETUP               0x0D
- #define USB_PID_IN                  0x09
- #define USB_PID_OUT                 0x01
- #define USB_PID_NYET                0x06
- #define USB_PID_ACK                 0x02
- #define USB_PID_NAK                 0x0A
- #define USB_PID_STALL               0x0E
- #define USB_PID_DATA0               0x03
- #define USB_PID_DATA1               0x0B
- #define USB_PID_DATA2               0x07
- #define USB_PID_MDATA               0x0F
- #define USB_PID_PRE                 0x0C
- #define USB_PID_SPLIT               0x08
- #define USB_PID_PING                0x04
- #endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V20x_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c
index bd36c34..c387061 100644
--- a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c
+++ b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/USB_Host/ch32v20x_usbfs_host.c
@@ -58,22 +58,25 @@ void USBFS_Host_Init( FunctionalState sta )
 {
     if( sta == ENABLE )
     {
-        /* Reset USB module */
-        USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
-        Delay_Us( 10 );
-        USBOTG_H_FS->BASE_CTRL = 0;
-
-        /* Initialize USB host configuration */
-        USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
+        USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE;
+        USBOTG_H_FS->HOST_CTRL = 0;
+        USBOTG_H_FS->DEV_ADDR = 0;
         USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN;
+
         USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf;
         USBOTG_H_FS->HOST_TX_DMA = (uint32_t)USBFS_TX_Buf;
+
+        USBOTG_H_FS->HOST_RX_CTRL = 0;
+        USBOTG_H_FS->HOST_TX_CTRL = 0;
+        USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN;
+
+        USBOTG_H_FS->INT_FG = 0xFF;
+
+        USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT;
     }
     else
     {
         USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL;
-        Delay_Us( 10 );
-        USBOTG_H_FS->BASE_CTRL = 0;
     }
 }
 
diff --git a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_usb.h
deleted file mode 100644
index 440079e..0000000
--- a/EVT/EXAM/USB/USBFS/HOST_MTP_FileSystem/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v20x_usb.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V20x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-
-
-#ifndef __CH32V20x_USB_H
-#define __CH32V20x_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header Files */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
- /* USB Endpoint0 Size */
- #ifndef DEFAULT_ENDP0_SIZE
- #define DEFAULT_ENDP0_SIZE          8
- #endif
-
- /* USB PID */
- #ifndef USB_PID_SETUP
- #define USB_PID_NULL                0x00
- #define USB_PID_SOF                 0x05
- #define USB_PID_SETUP               0x0D
- #define USB_PID_IN                  0x09
- #define USB_PID_OUT                 0x01
- #define USB_PID_NYET                0x06
- #define USB_PID_ACK                 0x02
- #define USB_PID_NAK                 0x0A
- #define USB_PID_STALL               0x0E
- #define USB_PID_DATA0               0x03
- #define USB_PID_DATA1               0x0B
- #define USB_PID_DATA2               0x07
- #define USB_PID_MDATA               0x0F
- #define USB_PID_PRE                 0x0C
- #define USB_PID_SPLIT               0x08
- #define USB_PID_PING                0x04
- #endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_IMAGE         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V20x_USB_H */
diff --git a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_usb.h b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_usb.h
deleted file mode 100644
index 415cc4b..0000000
--- a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/ch32v20x_usb.h
+++ /dev/null
@@ -1,539 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : system_ch32v30x.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V30x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-
-
-#ifndef __CH32V20x_USB_H
-#define __CH32V20x_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*******************************************************************************/
-/* Header Files */
-#include "stdint.h"
-
-/*******************************************************************************/
-/* USB Communication Related Macro Definition */
-
-/* USB Endpoint0 Size */
-#ifndef DEFAULT_ENDP0_SIZE
-#define DEFAULT_ENDP0_SIZE          8          // default maximum packet size for endpoint 0
-#endif
-#ifndef MAX_PACKET_SIZE
-#define MAX_PACKET_SIZE             64         // maximum packet size
-#endif
-
-/* USB PID */
-#ifndef USB_PID_SETUP
-#define USB_PID_NULL                0x00
-#define USB_PID_SOF                 0x05
-#define USB_PID_SETUP               0x0D
-#define USB_PID_IN                  0x09
-#define USB_PID_OUT                 0x01
-#define USB_PID_NYET                0x06
-#define USB_PID_ACK                 0x02
-#define USB_PID_NAK                 0x0A
-#define USB_PID_STALL               0x0E
-#define USB_PID_DATA0               0x03
-#define USB_PID_DATA1               0x0B
-#define USB_PID_PRE                 0x0C
-#endif
-
-/* USB standard device request code */
-#ifndef USB_GET_DESCRIPTOR
-#define USB_GET_STATUS              0x00
-#define USB_CLEAR_FEATURE           0x01
-#define USB_SET_FEATURE             0x03
-#define USB_SET_ADDRESS             0x05
-#define USB_GET_DESCRIPTOR          0x06
-#define USB_SET_DESCRIPTOR          0x07
-#define USB_GET_CONFIGURATION       0x08
-#define USB_SET_CONFIGURATION       0x09
-#define USB_GET_INTERFACE           0x0A
-#define USB_SET_INTERFACE           0x0B
-#define USB_SYNCH_FRAME             0x0C
-#endif
-
-#define DEF_STRING_DESC_LANG        0x00
-#define DEF_STRING_DESC_MANU        0x01
-#define DEF_STRING_DESC_PROD        0x02
-#define DEF_STRING_DESC_SERN        0x03
-
-/* USB hub class request code */
-#ifndef HUB_GET_DESCRIPTOR
-#define HUB_GET_STATUS              0x00
-#define HUB_CLEAR_FEATURE           0x01
-#define HUB_GET_STATE               0x02
-#define HUB_SET_FEATURE             0x03
-#define HUB_GET_DESCRIPTOR          0x06
-#define HUB_SET_DESCRIPTOR          0x07
-#endif
-
-/* USB HID class request code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* Bit Define for USB Request Type */
-#ifndef USB_REQ_TYP_MASK
-#define USB_REQ_TYP_IN              0x80
-#define USB_REQ_TYP_OUT             0x00
-#define USB_REQ_TYP_READ            0x80
-#define USB_REQ_TYP_WRITE           0x00
-#define USB_REQ_TYP_MASK            0x60
-#define USB_REQ_TYP_STANDARD        0x00
-#define USB_REQ_TYP_CLASS           0x20
-#define USB_REQ_TYP_VENDOR          0x40
-#define USB_REQ_TYP_RESERVED        0x60
-#define USB_REQ_RECIP_MASK          0x1F
-#define USB_REQ_RECIP_DEVICE        0x00
-#define USB_REQ_RECIP_INTERF        0x01
-#define USB_REQ_RECIP_ENDP          0x02
-#define USB_REQ_RECIP_OTHER         0x03
-#define USB_REQ_FEAT_REMOTE_WAKEUP  0x01
-#define USB_REQ_FEAT_ENDP_HALT      0x00
-#endif
-
-/* USB Descriptor Type */
-#ifndef USB_DESCR_TYP_DEVICE
-#define USB_DESCR_TYP_DEVICE        0x01
-#define USB_DESCR_TYP_CONFIG        0x02
-#define USB_DESCR_TYP_STRING        0x03
-#define USB_DESCR_TYP_INTERF        0x04
-#define USB_DESCR_TYP_ENDP          0x05
-#define USB_DESCR_TYP_QUALIF        0x06
-#define USB_DESCR_TYP_SPEED         0x07
-#define USB_DESCR_TYP_OTG           0x09
-#define USB_DESCR_TYP_BOS           0X0F
-#define USB_DESCR_TYP_HID           0x21
-#define USB_DESCR_TYP_REPORT        0x22
-#define USB_DESCR_TYP_PHYSIC        0x23
-#define USB_DESCR_TYP_CS_INTF       0x24
-#define USB_DESCR_TYP_CS_ENDP       0x25
-#define USB_DESCR_TYP_HUB           0x29
-#endif
-
-/* USB Device Class */
-#ifndef USB_DEV_CLASS_HUB
-#define USB_DEV_CLASS_RESERVED      0x00
-#define USB_DEV_CLASS_AUDIO         0x01
-#define USB_DEV_CLASS_COMMUNIC      0x02
-#define USB_DEV_CLASS_HID           0x03
-#define USB_DEV_CLASS_MONITOR       0x04
-#define USB_DEV_CLASS_PHYSIC_IF     0x05
-#define USB_DEV_CLASS_POWER         0x06
-#define USB_DEV_CLASS_PRINTER       0x07
-#define USB_DEV_CLASS_STORAGE       0x08
-#define USB_DEV_CLASS_HUB           0x09
-#define USB_DEV_CLASS_VEN_SPEC      0xFF
-#endif
-
-/* USB Hub Class Request */
-#ifndef HUB_GET_HUB_DESCRIPTOR
-#define HUB_CLEAR_HUB_FEATURE       0x20
-#define HUB_CLEAR_PORT_FEATURE      0x23
-#define HUB_GET_BUS_STATE           0xA3
-#define HUB_GET_HUB_DESCRIPTOR      0xA0
-#define HUB_GET_HUB_STATUS          0xA0
-#define HUB_GET_PORT_STATUS         0xA3
-#define HUB_SET_HUB_DESCRIPTOR      0x20
-#define HUB_SET_HUB_FEATURE         0x20
-#define HUB_SET_PORT_FEATURE        0x23
-#endif
-
-/* Hub Class Feature Selectors */
-#ifndef HUB_PORT_RESET
-#define HUB_C_HUB_LOCAL_POWER       0
-#define HUB_C_HUB_OVER_CURRENT      1
-#define HUB_PORT_CONNECTION         0
-#define HUB_PORT_ENABLE             1
-#define HUB_PORT_SUSPEND            2
-#define HUB_PORT_OVER_CURRENT       3
-#define HUB_PORT_RESET              4
-#define HUB_PORT_POWER              8
-#define HUB_PORT_LOW_SPEED          9
-#define HUB_C_PORT_CONNECTION       16
-#define HUB_C_PORT_ENABLE           17
-#define HUB_C_PORT_SUSPEND          18
-#define HUB_C_PORT_OVER_CURRENT     19
-#define HUB_C_PORT_RESET            20
-#endif
-
-/* USB HID Class Request Code */
-#ifndef HID_GET_REPORT
-#define HID_GET_REPORT              0x01
-#define HID_GET_IDLE                0x02
-#define HID_GET_PROTOCOL            0x03
-#define HID_SET_REPORT              0x09
-#define HID_SET_IDLE                0x0A
-#define HID_SET_PROTOCOL            0x0B
-#endif
-
-/* USB UDisk */
-#ifndef USB_BO_CBW_SIZE
-#define USB_BO_CBW_SIZE             0x1F
-#define USB_BO_CSW_SIZE             0x0D
-#endif
-#ifndef USB_BO_CBW_SIG0
-#define USB_BO_CBW_SIG0             0x55
-#define USB_BO_CBW_SIG1             0x53
-#define USB_BO_CBW_SIG2             0x42
-#define USB_BO_CBW_SIG3             0x43
-#define USB_BO_CSW_SIG0             0x55
-#define USB_BO_CSW_SIG1             0x53
-#define USB_BO_CSW_SIG2             0x42
-#define USB_BO_CSW_SIG3             0x53
-#endif
-
-
-/*******************************************************************************/
-/* USBFS Related Register Macro Definition */
-
-/* R8_USB_CTRL */
-#define USBFS_UC_HOST_MODE          0x80
-#define USBFS_UC_LOW_SPEED          0x40
-#define USBFS_UC_DEV_PU_EN          0x20
-#define USBFS_UC_SYS_CTRL_MASK      0x30
-#define USBFS_UC_SYS_CTRL0          0x00
-#define USBFS_UC_SYS_CTRL1          0x10
-#define USBFS_UC_SYS_CTRL2          0x20
-#define USBFS_UC_SYS_CTRL3          0x30
-#define USBFS_UC_INT_BUSY           0x08
-#define USBFS_UC_RESET_SIE          0x04
-#define USBFS_UC_CLR_ALL            0x02
-#define USBFS_UC_DMA_EN             0x01
-
-/* R8_USB_INT_EN */
-#define USBFS_UIE_DEV_SOF           0x80
-#define USBFS_UIE_DEV_NAK           0x40
-#define USBFS_UIE_FIFO_OV           0x10
-#define USBFS_UIE_HST_SOF           0x08
-#define USBFS_UIE_SUSPEND           0x04
-#define USBFS_UIE_TRANSFER          0x02
-#define USBFS_UIE_DETECT            0x01
-#define USBFS_UIE_BUS_RST           0x01
-
-/* R8_USB_DEV_AD */
-#define USBFS_UDA_GP_BIT            0x80
-#define USBFS_USB_ADDR_MASK         0x7F
-
-/* R8_USB_MIS_ST */
-#define USBFS_UMS_SOF_PRES          0x80
-#define USBFS_UMS_SOF_ACT           0x40
-#define USBFS_UMS_SIE_FREE          0x20
-#define USBFS_UMS_R_FIFO_RDY        0x10
-#define USBFS_UMS_BUS_RESET         0x08
-#define USBFS_UMS_SUSPEND           0x04
-#define USBFS_UMS_DM_LEVEL          0x02
-#define USBFS_UMS_DEV_ATTACH        0x01
-
-/* R8_USB_INT_FG */
-#define USBFS_U_IS_NAK              0x80    // RO, indicate current USB transfer is NAK received
-#define USBFS_U_TOG_OK              0x40    // RO, indicate current USB transfer toggle is OK
-#define USBFS_U_SIE_FREE            0x20    // RO, indicate USB SIE free status
-#define USBFS_UIF_FIFO_OV           0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-#define USBFS_UIF_HST_SOF           0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-#define USBFS_UIF_SUSPEND           0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_TRANSFER          0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-#define USBFS_UIF_DETECT            0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
-#define USBFS_UIF_BUS_RST           0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
-
-/* R8_USB_INT_ST */
-#define USBFS_UIS_IS_NAK            0x80      // RO, indicate current USB transfer is NAK received for USB device mode
-#define USBFS_UIS_TOG_OK            0x40      // RO, indicate current USB transfer toggle is OK
-#define USBFS_UIS_TOKEN_MASK        0x30      // RO, bit mask of current token PID code received for USB device mode
-#define USBFS_UIS_TOKEN_OUT         0x00
-#define USBFS_UIS_TOKEN_SOF         0x10
-#define USBFS_UIS_TOKEN_IN          0x20
-#define USBFS_UIS_TOKEN_SETUP       0x30
-// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
-//   00: OUT token PID received
-//   01: SOF token PID received
-//   10: IN token PID received
-//   11: SETUP token PID received
-#define USBFS_UIS_ENDP_MASK         0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
-#define USBFS_UIS_H_RES_MASK        0x0F      // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
-
-/* R32_USB_OTG_CR */
-#define USBFS_CR_SESS_VTH           0x20
-#define USBFS_CR_VBUS_VTH           0x10
-#define USBFS_CR_OTG_EN             0x08
-#define USBFS_CR_IDPU               0x04
-#define USBFS_CR_CHARGE_VBUS        0x02
-#define USBFS_CR_DISCHAR_VBUS       0x01
-
-/* R32_USB_OTG_SR */
-#define USBFS_SR_ID_DIG             0x08
-#define USBFS_SR_SESS_END           0x04
-#define USBFS_SR_SESS_VLD           0x02
-#define USBFS_SR_VBUS_VLD           0x01
-
-/* R8_UDEV_CTRL */
-#define USBFS_UD_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UD_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UD_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UD_LOW_SPEED          0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
-#define USBFS_UD_GP_BIT             0x02      // general purpose bit
-#define USBFS_UD_PORT_EN            0x01      // enable USB physical port I/O: 0=disable, 1=enable
-
-/* R8_UEP4_1_MOD */
-#define USBFS_UEP1_RX_EN            0x80      // enable USB endpoint 1 receiving (OUT)
-#define USBFS_UEP1_TX_EN            0x40      // enable USB endpoint 1 transmittal (IN)
-#define USBFS_UEP1_BUF_MOD          0x10      // buffer mode of USB endpoint 1
-// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
-//   0 0 x:  disable endpoint and disable buffer
-//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
-//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
-//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
-//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
-//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
-//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
-#define USBFS_UEP4_RX_EN            0x08      // enable USB endpoint 4 receiving (OUT)
-#define USBFS_UEP4_TX_EN            0x04      // enable USB endpoint 4 transmittal (IN)
-// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
-//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
-//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
-//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
-//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
-#define USBFS_UEP4_BUF_MOD          0x01
-
-/* R8_UEP2_3_MOD */
-#define USBFS_UEP3_RX_EN            0x80      // enable USB endpoint 3 receiving (OUT)
-#define USBFS_UEP3_TX_EN            0x40      // enable USB endpoint 3 transmittal (IN)
-#define USBFS_UEP3_BUF_MOD          0x10      // buffer mode of USB endpoint 3
-#define USBFS_UEP2_RX_EN            0x08      // enable USB endpoint 2 receiving (OUT)
-#define USBFS_UEP2_TX_EN            0x04      // enable USB endpoint 2 transmittal (IN)
-#define USBFS_UEP2_BUF_MOD          0x01      // buffer mode of USB endpoint 2
-
-/* R8_UEP5_6_MOD */
-#define USBFS_UEP6_RX_EN            0x80      // enable USB endpoint 6 receiving (OUT)
-#define USBFS_UEP6_TX_EN            0x40      // enable USB endpoint 6 transmittal (IN)
-#define USBFS_UEP6_BUF_MOD          0x10      // buffer mode of USB endpoint 6
-#define USBFS_UEP5_RX_EN            0x08      // enable USB endpoint 5 receiving (OUT)
-#define USBFS_UEP5_TX_EN            0x04      // enable USB endpoint 5 transmittal (IN)
-#define USBFS_UEP5_BUF_MOD          0x01      // buffer mode of USB endpoint 5
-
-/* R8_UEP7_MOD */
-#define USBFS_UEP7_RX_EN            0x08      // enable USB endpoint 7 receiving (OUT)
-#define USBFS_UEP7_TX_EN            0x04      // enable USB endpoint 7 transmittal (IN)
-#define USBFS_UEP7_BUF_MOD          0x01      // buffer mode of USB endpoint 7
-
-/* R8_UEPn_TX_CTRL */
-#define USBFS_UEP_T_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_T_TOG             0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-#define USBFS_UEP_T_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
-#define USBFS_UEP_T_RES_ACK         0x00
-#define USBFS_UEP_T_RES_NONE        0x01
-#define USBFS_UEP_T_RES_NAK         0x02
-#define USBFS_UEP_T_RES_STALL       0x03
-// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
-//   00: DATA0 or DATA1 then expecting ACK (ready)
-//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-// host aux setup
-
-/* R8_UEPn_RX_CTRL, n=0-7 */
-#define USBFS_UEP_R_AUTO_TOG        0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
-#define USBFS_UEP_R_TOG             0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-#define USBFS_UEP_R_RES_MASK        0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
-#define USBFS_UEP_R_RES_ACK         0x00
-#define USBFS_UEP_R_RES_NONE        0x01
-#define USBFS_UEP_R_RES_NAK         0x02
-#define USBFS_UEP_R_RES_STALL       0x03
-// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
-//   00: ACK (ready)
-//   01: no response, time out to host, for non-zero endpoint isochronous transactions
-//   10: NAK (busy)
-//   11: STALL (error)
-
-/* R8_UHOST_CTRL */
-#define USBFS_UH_PD_DIS             0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
-#define USBFS_UH_DP_PIN             0x20      // ReadOnly: indicate current UDP pin level
-#define USBFS_UH_DM_PIN             0x10      // ReadOnly: indicate current UDM pin level
-#define USBFS_UH_LOW_SPEED          0x04      // enable USB port low speed: 0=full speed, 1=low speed
-#define USBFS_UH_BUS_RESET          0x02      // control USB bus reset: 0=normal, 1=force bus reset
-#define USBFS_UH_PORT_EN            0x01      // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
-/* R32_UH_EP_MOD */
-#define USBFS_UH_EP_TX_EN           0x40      // enable USB host OUT endpoint transmittal
-#define USBFS_UH_EP_TBUF_MOD        0x10      // buffer mode of USB host OUT endpoint
-// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
-#define USBFS_UH_EP_RX_EN           0x08      // enable USB host IN endpoint receiving
-#define USBFS_UH_EP_RBUF_MOD        0x01      // buffer mode of USB host IN endpoint
-// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
-//   0 x:  disable endpoint and disable buffer
-//   1 0:  64 bytes buffer for receiving (IN endpoint)
-//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
-
-/* R16_UH_SETUP */
-#define USBFS_UH_PRE_PID_EN         0x0400      // USB host PRE PID enable for low speed device via hub
-#define USBFS_UH_SOF_EN             0x0004      // USB host automatic SOF enable
-
-/* R8_UH_EP_PID */
-#define USBFS_UH_TOKEN_MASK         0xF0      // bit mask of token PID for USB host transfer
-#define USBFS_UH_ENDP_MASK          0x0F      // bit mask of endpoint number for USB host transfer
-
-/* R8_UH_RX_CTRL */
-#define USBFS_UH_R_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_R_TOG              0x04      // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
-#define USBFS_UH_R_RES              0x01      // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
-
-/* R8_UH_TX_CTRL */
-#define USBFS_UH_T_AUTO_TOG         0x08      // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
-#define USBFS_UH_T_TOG              0x04      // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
-#define USBFS_UH_T_RES              0x01      // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
-
-
-/*******************************************************************************/
-/* Struct Definition */
-
-/* USB Setup Request */
-typedef struct __attribute__((packed)) _USB_SETUP_REQ
-{
-    uint8_t  bRequestType;
-    uint8_t  bRequest;
-    uint16_t wValue;
-    uint16_t wIndex;
-    uint16_t wLength;
-} USB_SETUP_REQ, *PUSB_SETUP_REQ;
-
-/* USB Device Descriptor */
-typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdUSB;
-    uint8_t  bDeviceClass;
-    uint8_t  bDeviceSubClass;
-    uint8_t  bDeviceProtocol;
-    uint8_t  bMaxPacketSize0;
-    uint16_t idVendor;
-    uint16_t idProduct;
-    uint16_t bcdDevice;
-    uint8_t  iManufacturer;
-    uint8_t  iProduct;
-    uint8_t  iSerialNumber;
-    uint8_t  bNumConfigurations;
-} USB_DEV_DESCR, *PUSB_DEV_DESCR;
-
-/* USB Configuration Descriptor */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t wTotalLength;
-    uint8_t  bNumInterfaces;
-    uint8_t  bConfigurationValue;
-    uint8_t  iConfiguration;
-    uint8_t  bmAttributes;
-    uint8_t  MaxPower;
-} USB_CFG_DESCR, *PUSB_CFG_DESCR;
-
-/* USB Interface Descriptor */
-typedef struct __attribute__((packed)) _USB_INTERF_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bInterfaceNumber;
-    uint8_t  bAlternateSetting;
-    uint8_t  bNumEndpoints;
-    uint8_t  bInterfaceClass;
-    uint8_t  bInterfaceSubClass;
-    uint8_t  bInterfaceProtocol;
-    uint8_t  iInterface;
-} USB_ITF_DESCR, *PUSB_ITF_DESCR;
-
-/* USB Endpoint Descriptor */
-typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bEndpointAddress;
-    uint8_t  bmAttributes;
-    uint8_t  wMaxPacketSizeL;
-    uint8_t  wMaxPacketSizeH;
-    uint8_t  bInterval;
-} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
-
-/* USB Configuration Descriptor Set */
-typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
-{
-    USB_CFG_DESCR  cfg_descr;
-    USB_ITF_DESCR  itf_descr;
-    USB_ENDP_DESCR endp_descr[ 1 ];
-} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
-
-/* USB HUB Descriptor */
-typedef struct __attribute__((packed)) _USB_HUB_DESCR
-{
-    uint8_t  bDescLength;
-    uint8_t  bDescriptorType;
-    uint8_t  bNbrPorts;
-    uint8_t  wHubCharacteristicsL;
-    uint8_t  wHubCharacteristicsH;
-    uint8_t  bPwrOn2PwrGood;
-    uint8_t  bHubContrCurrent;
-    uint8_t  DeviceRemovable;
-    uint8_t  PortPwrCtrlMask;
-} USB_HUB_DESCR, *PUSB_HUB_DESCR;
-
-/* USB HID Descriptor */
-typedef struct __attribute__((packed)) _USB_HID_DESCR
-{
-    uint8_t  bLength;
-    uint8_t  bDescriptorType;
-    uint16_t bcdHID;
-    uint8_t  bCountryCode;
-    uint8_t  bNumDescriptors;
-    uint8_t  bDescriptorTypeX;
-    uint8_t  wDescriptorLengthL;
-    uint8_t  wDescriptorLengthH;
-} USB_HID_DESCR, *PUSB_HID_DESCR;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CBW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCBW_DataLen;
-    uint8_t  mCBW_Flag;
-    uint8_t  mCBW_LUN;
-    uint8_t  mCBW_CB_Len;
-    uint8_t  mCBW_CB_Buf[ 16 ];
-} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
-
-/* USB UDisk */
-typedef struct __attribute__((packed)) _UDISK_BOC_CSW
-{
-    uint32_t mCBW_Sig;
-    uint32_t mCBW_Tag;
-    uint32_t mCSW_Residue;
-    uint8_t  mCSW_Status;
-} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V20x_USB_H */
diff --git a/EVT/EXAM/WWDG/.template b/EVT/EXAM/WWDG/.template
deleted file mode 100644
index c2f4fb7..0000000
--- a/EVT/EXAM/WWDG/.template
+++ /dev/null
@@ -1,16 +0,0 @@
-Mcu Type=CH32V20x
-Address=0x08000000
-Target Path=obj/WWDG.hex
-Erase All=true
-Program=true
-Verify=true
-Reset=true
-
-Vendor=WCH
-Link=WCH-Link
-Toolchain=RISC-V
-Series=CH32V203
-Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
-
-PeripheralVersion=1.0
-MCU=CH32V203RBT6
diff --git a/EVT/EXAM/WWDG/User/system_ch32v20x.c b/EVT/EXAM/WWDG/User/system_ch32v20x.c
deleted file mode 100644
index 37730a5..0000000
--- a/EVT/EXAM/WWDG/User/system_ch32v20x.c
+++ /dev/null
@@ -1,986 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
- * File Name          : system_ch32v20x.c
- * Author             : WCH
- * Version            : V1.0.0
- * Date               : 2021/06/06
- * Description        : CH32V20x Device Peripheral Access Layer System Source File.
- *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
- *                      For HSE = 8Mhz (other CH32V203x)
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for 
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#include "ch32v20x.h" 
-
-/* 
-* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
-* reset the HSI is used as SYSCLK source).
-* If none of the define below is enabled, the HSI is used as System clock source. 
-*/
-//#define SYSCLK_FREQ_HSE    HSE_VALUE
-//#define SYSCLK_FREQ_48MHz_HSE  48000000
-//#define SYSCLK_FREQ_56MHz_HSE  56000000
-//#define SYSCLK_FREQ_72MHz_HSE  72000000
-#define SYSCLK_FREQ_96MHz_HSE  96000000
-//#define SYSCLK_FREQ_120MHz_HSE  120000000
-//#define SYSCLK_FREQ_144MHz_HSE  144000000
-//#define SYSCLK_FREQ_HSI    HSI_VALUE
-//#define SYSCLK_FREQ_48MHz_HSI  48000000
-//#define SYSCLK_FREQ_56MHz_HSI  56000000
-//#define SYSCLK_FREQ_72MHz_HSI  72000000
-//#define SYSCLK_FREQ_96MHz_HSI  96000000
-//#define SYSCLK_FREQ_120MHz_HSI  120000000
-//#define SYSCLK_FREQ_144MHz_HSI  144000000
-
-/* Clock Definitions */
-#ifdef SYSCLK_FREQ_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_96MHz_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_120MHz_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_144MHz_HSE
-uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz_HSI
-uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz_HSI
-uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz_HSI
-uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_96MHz_HSI
-uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_120MHz_HSI
-uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_144MHz_HSI
-uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
-#else
-uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
-
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-
-/* system_private_function_proto_types */
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-static void SetSysClockToHSE( void );
-#elif defined SYSCLK_FREQ_48MHz_HSE
-static void SetSysClockTo48_HSE( void );
-#elif defined SYSCLK_FREQ_56MHz_HSE
-static void SetSysClockTo56_HSE( void );
-#elif defined SYSCLK_FREQ_72MHz_HSE
-static void SetSysClockTo72_HSE( void );
-#elif defined SYSCLK_FREQ_96MHz_HSE
-static void SetSysClockTo96_HSE( void );
-#elif defined SYSCLK_FREQ_120MHz_HSE
-static void SetSysClockTo120_HSE( void );
-#elif defined SYSCLK_FREQ_144MHz_HSE
-static void SetSysClockTo144_HSE( void );
-#elif defined SYSCLK_FREQ_48MHz_HSI
-static void SetSysClockTo48_HSI( void );
-#elif defined SYSCLK_FREQ_56MHz_HSI
-static void SetSysClockTo56_HSI( void );
-#elif defined SYSCLK_FREQ_72MHz_HSI
-static void SetSysClockTo72_HSI( void );
-#elif defined SYSCLK_FREQ_96MHz_HSI
-static void SetSysClockTo96_HSI( void );
-#elif defined SYSCLK_FREQ_120MHz_HSI
-static void SetSysClockTo120_HSI( void );
-#elif defined SYSCLK_FREQ_144MHz_HSI
-static void SetSysClockTo144_HSI( void );
-
-#endif
-
-/*********************************************************************
- * @fn      SystemInit
- *
- * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
- *        the PLL and update the SystemCoreClock variable.
- *
- * @return  none
- */
-void SystemInit (void)
-{
-  RCC->CTLR |= (uint32_t)0x00000001;
-  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
-  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
-  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
-  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
-  RCC->INTR = 0x009F0000;    
-  SetSysClock();
-}
-
-
-/*********************************************************************
- * @fn      SystemCoreClockUpdate
- *
- * @brief   Update SystemCoreClock variable according to Clock Register Values.
- *
- * @return  none
- */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
-
-  tmp = RCC->CFGR0 & RCC_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:
-      pllmull = RCC->CFGR0 & RCC_PLLMULL;
-      pllsource = RCC->CFGR0 & RCC_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-      if(pllmull == 17) pllmull = 18;
-
-      if (pllsource == 0x00)
-      {
-          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
-              SystemCoreClock = HSI_VALUE * pllmull;
-          }
-          else{
-              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-          }
-      }
-      else
-      {
-#if defined (CH32V20x_D8W)
-        if((RCC->CFGR0 & (3<<22)) == (3<<22))
-        {
-          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
-        }
-        else
-#endif
-        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
-        {
-#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
-          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
-#else
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-#endif
-        }
-        else
-        {
-#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
-            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
-#else
-          SystemCoreClock = HSE_VALUE * pllmull;
-#endif
-        }
-      }
-
-      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
-
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-
-  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
-  SystemCoreClock >>= tmp;
-}
-
-/*********************************************************************
- * @fn      SetSysClock
- *
- * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-    SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_48MHz_HSE
-    SetSysClockTo48_HSE();
-#elif defined SYSCLK_FREQ_56MHz_HSE
-    SetSysClockTo56_HSE();
-#elif defined SYSCLK_FREQ_72MHz_HSE
-    SetSysClockTo72_HSE();
-#elif defined SYSCLK_FREQ_96MHz_HSE
-    SetSysClockTo96_HSE();
-#elif defined SYSCLK_FREQ_120MHz_HSE
-    SetSysClockTo120_HSE();
-#elif defined SYSCLK_FREQ_144MHz_HSE
-    SetSysClockTo144_HSE();
-#elif defined SYSCLK_FREQ_48MHz_HSI
-    SetSysClockTo48_HSI();
-#elif defined SYSCLK_FREQ_56MHz_HSI
-    SetSysClockTo56_HSI();
-#elif defined SYSCLK_FREQ_72MHz_HSI
-    SetSysClockTo72_HSI();
-#elif defined SYSCLK_FREQ_96MHz_HSI
-    SetSysClockTo96_HSI();
-#elif defined SYSCLK_FREQ_120MHz_HSI
-    SetSysClockTo120_HSI();
-#elif defined SYSCLK_FREQ_144MHz_HSI
-    SetSysClockTo144_HSI();
-
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-  * source (default after reset) 
-	*/ 
-}
-
-
-#ifdef SYSCLK_FREQ_HSE
-
-/*********************************************************************
- * @fn      SetSysClockToHSE
- *
- * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-   
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source
-     *  CH32V20x_D6 (HSE=8MHZ)
-     *  CH32V20x_D8 (HSE=32MHZ)
-     *  CH32V20x_D8W (HSE=32MHZ)
-     */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { 
-		/* If HSE fails to start-up, the application will have wrong clock 
-     * configuration. User can add here some code to deal with this error 
-		 */
-  }  
-}
-
-#elif defined SYSCLK_FREQ_48MHz_HSE
-
-/*********************************************************************
- * @fn      SetSysClockTo48_HSE
- *
- * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo48_HSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
-   
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
-     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
-     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
-     */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { 
-		/* 
-		 * If HSE fails to start-up, the application will have wrong clock 
-     * configuration. User can add here some code to deal with this error 
-		 */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz_HSE
-
-/*********************************************************************
- * @fn      SetSysClockTo56_HSE
- *
- * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo56_HSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-  
-    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
-     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
-     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
-     */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { 
-		/* 
-		 * If HSE fails to start-up, the application will have wrong clock 
-     * configuration. User can add here some code to deal with this error 
-		 */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz_HSE
-
-/*********************************************************************
- * @fn      SetSysClockTo72_HSE
- *
- * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo72_HSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
- 
-    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
-     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
-     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
-     */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }    
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { 
-		/* 
-		 * If HSE fails to start-up, the application will have wrong clock 
-     * configuration. User can add here some code to deal with this error 
-		 */
-  }
-}
-
-
-#elif defined SYSCLK_FREQ_96MHz_HSE
-
-/*********************************************************************
- * @fn      SetSysClockTo96_HSE
- *
- * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo96_HSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
-     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
-     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
-     */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-
-#elif defined SYSCLK_FREQ_120MHz_HSE
-
-/*********************************************************************
- * @fn      SetSysClockTo120_HSE
- *
- * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo120_HSE(void)
-{
-    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-    RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-    /* Wait till HSE is ready and if Time out is reached exit */
-    do
-    {
-        HSEStatus = RCC->CTLR & RCC_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if((RCC->CTLR & RCC_HSERDY) != RESET)
-    {
-        HSEStatus = (uint32_t)0x01;
-    }
-    else
-    {
-        HSEStatus = (uint32_t)0x00;
-    }
-
-    if(HSEStatus == (uint32_t)0x01)
-    {
-#if defined (CH32V20x_D8W)
-        RCC->CFGR0 |= (uint32_t)(3<<22);
-        /* HCLK = SYSCLK/2 */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
-#else
-        /* HCLK = SYSCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-#endif
-        /* PCLK2 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-        /* PCLK1 = HCLK */
-        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
-         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
-         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
-         */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                              RCC_PLLMULL));
-
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
-
-        /* Enable PLL */
-        RCC->CTLR |= RCC_PLLON;
-        /* Wait till PLL is ready */
-        while((RCC->CTLR & RCC_PLLRDY) == 0)
-        {
-        }
-        /* Select PLL as system clock source */
-        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-        /* Wait till PLL is used as system clock source */
-        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-        {
-        }
-    }
-    else
-    {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-         * configuration. User can add here some code to deal with this error
-         */
-    }
-}
-#elif defined SYSCLK_FREQ_144MHz_HSE
-
-/*********************************************************************
- * @fn      SetSysClockTo144_HSE
- *
- * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo144_HSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
-     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
-     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
-     */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-#elif defined SYSCLK_FREQ_48MHz_HSI
-
-/*********************************************************************
- * @fn      SetSysClockTo48_HSI
- *
- * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo48_HSI(void)
-{
-    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
-
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-}
-
-#elif defined SYSCLK_FREQ_56MHz_HSI
-
-/*********************************************************************
- * @fn      SetSysClockTo56_HSI
- *
- * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo56_HSI(void)
-{
-    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
-
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-}
-
-#elif defined SYSCLK_FREQ_72MHz_HSI
-
-/*********************************************************************
- * @fn      SetSysClockTo72_HSI
- *
- * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo72_HSI(void)
-{
-    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
-
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-}
-
-
-#elif defined SYSCLK_FREQ_96MHz_HSI
-
-/*********************************************************************
- * @fn      SetSysClockTo96_HSI
- *
- * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo96_HSI(void)
-{
-    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
-
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-}
-
-
-#elif defined SYSCLK_FREQ_120MHz_HSI
-
-/*********************************************************************
- * @fn      SetSysClockTo120_HSI
- *
- * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo120_HSI(void)
-{
-    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
-
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                          RCC_PLLMULL));
-
-    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-}
-#elif defined SYSCLK_FREQ_144MHz_HSI
-
-/*********************************************************************
- * @fn      SetSysClockTo144_HSI
- *
- * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo144_HSI(void)
-{
-    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
-
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-}
-
-
-#endif
diff --git a/EVT/EXAM/WWDG/WWDG/.cproject b/EVT/EXAM/WWDG/WWDG/.cproject
new file mode 100644
index 0000000..93c33ac
--- /dev/null
+++ b/EVT/EXAM/WWDG/WWDG/.cproject
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
+					<folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074." name="/" resourcePath="">
+						<toolChain id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release.231146001" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release">
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash.1311852988" name="Create flash image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting.1983282875" name="Create extended listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize.1000761142" name="Print size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.514997414" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.size" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.1008570639" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar.467272439" name="'char' is signed (-fsigned-char)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections.2047756949" name="Function sections (-ffunction-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections.207613650" name="Data sections (-fdata-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.1204865254" name="Debug level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level" useByScannerDiscovery="true"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format.867779652" name="Debug format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format" useByScannerDiscovery="true"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base.1900297968" name="Architecture" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.arch.rv32i" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.387605487" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.ilp32" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1509705449" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1038505275" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.name.1218760634" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.name" useByScannerDiscovery="false" value="GNU MCU RISC-V GCC" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix.103341323" name="Prefix" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix" useByScannerDiscovery="false" value="riscv-none-embed-" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c.487601824" name="C compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp.1062130429" name="C++ compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.ar.1194282993" name="Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.ar" useByScannerDiscovery="false" value="ar" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy.1529355265" name="Hex/Bin converter" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump.1053750745" name="Listing generator" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size.1441326233" name="Size command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size" useByScannerDiscovery="false" value="size" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make.550105535" name="Build command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make" useByScannerDiscovery="false" value="make" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm.719280496" name="Remove command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id.226017994" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id" useByScannerDiscovery="false" value="512258282" valueType="string"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.2003631682" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.1819910041" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1179366128" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/GPIO_Toggle}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1244756189" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Startup}&quot;"/>
+								</option>
+								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.126366858" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.1567947810" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Debug}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Core}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/User}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Peripheral/inc}&quot;"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std.2020844713" name="Language standard" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std.gnu99" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs.177116515" name="Defined symbols (-D)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols"/>
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+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.1610882921" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.1620074387" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker">
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+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.2057340378" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1390103472" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Ld/Link.ld}&quot;"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.913830613" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.239404511" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs.16994550" name="Other objects" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs" useByScannerDiscovery="false" valueType="userObjs"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags.1125808200" name="Linker flags (-Xlinker [option])" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags" useByScannerDiscovery="false" valueType="stringList"/>
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+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1947503520" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1689063433" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths.1029177148" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;../LD&quot;"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile.1751226764" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="Link.ld"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.1540675679" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
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+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1298918921" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry excluding="startup_ch32v20x_D8.S|startup_ch32v20x_D8W.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	
+</cproject>
diff --git a/EVT/EXAM/WWDG/.project b/EVT/EXAM/WWDG/WWDG/.project
similarity index 83%
rename from EVT/EXAM/WWDG/.project
rename to EVT/EXAM/WWDG/WWDG/.project
index ab27b41..bf71c2f 100644
--- a/EVT/EXAM/WWDG/.project
+++ b/EVT/EXAM/WWDG/WWDG/.project
@@ -35,27 +35,27 @@
     <link>
       <name>Core</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Core</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Core</location>
     </link>
     <link>
       <name>Debug</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Debug</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
     </link>
     <link>
       <name>Ld</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Ld</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
     </link>
     <link>
       <name>Peripheral</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Peripheral</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
     </link>
     <link>
       <name>Startup</name>
       <type>2</type>
-      <location>PARENT-1-PROJECT_LOC/SRC/Startup</location>
+      <location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
     </link>
   </linkedResources>
 </projectDescription>
diff --git a/EVT/EXAM/BKP/.template b/EVT/EXAM/WWDG/WWDG/.template
similarity index 94%
rename from EVT/EXAM/BKP/.template
rename to EVT/EXAM/WWDG/WWDG/.template
index 65e286f..aabecbc 100644
--- a/EVT/EXAM/BKP/.template
+++ b/EVT/EXAM/WWDG/WWDG/.template
@@ -1,6 +1,6 @@
 Mcu Type=CH32V20x
 Address=0x08000000
-Target Path=obj/BKP.hex
+Target Path=obj\WWDG.hex
 Erase All=true
 Program=true
 Verify=true
@@ -14,3 +14,4 @@ Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH
 
 PeripheralVersion=1.0
 MCU=CH32V203RBT6
+CLKSpeed=1
diff --git a/EVT/EXAM/WWDG/WWDG/User/ch32v20x_conf.h b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_conf.h
new file mode 100644
index 0000000..d1eeb38
--- /dev/null
+++ b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_conf.h
@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : Library configuration file.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_CONF_H
+#define __CH32V20x_CONF_H
+
+#include "ch32v20x_adc.h"
+#include "ch32v20x_bkp.h"
+#include "ch32v20x_can.h"
+#include "ch32v20x_crc.h"
+#include "ch32v20x_dbgmcu.h"
+#include "ch32v20x_dma.h"
+#include "ch32v20x_exti.h"
+#include "ch32v20x_flash.h"
+#include "ch32v20x_gpio.h"
+#include "ch32v20x_i2c.h"
+#include "ch32v20x_iwdg.h"
+#include "ch32v20x_pwr.h"
+#include "ch32v20x_rcc.h"
+#include "ch32v20x_rtc.h"
+#include "ch32v20x_spi.h"
+#include "ch32v20x_tim.h"
+#include "ch32v20x_usart.h"
+#include "ch32v20x_wwdg.h"
+#include "ch32v20x_it.h"
+#include "ch32v20x_misc.h"
+
+
+#endif /* __CH32V20x_CONF_H */
+
+
+	
+	
+	
diff --git a/EVT/EXAM/WWDG/User/ch32v20x_it.c b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.c
similarity index 100%
rename from EVT/EXAM/WWDG/User/ch32v20x_it.c
rename to EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.c
diff --git a/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.h b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.h
new file mode 100644
index 0000000..f68b203
--- /dev/null
+++ b/EVT/EXAM/WWDG/WWDG/User/ch32v20x_it.h
@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v20x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_IT_H
+#define __CH32V20x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V20x_IT_H */
+
+
diff --git a/EVT/EXAM/WWDG/User/main.c b/EVT/EXAM/WWDG/WWDG/User/main.c
similarity index 100%
rename from EVT/EXAM/WWDG/User/main.c
rename to EVT/EXAM/WWDG/WWDG/User/main.c
diff --git a/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c b/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c
new file mode 100644
index 0000000..8d3a568
--- /dev/null
+++ b/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.c
@@ -0,0 +1,987 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Source File.
+ *                      For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
+ *                      For HSE = 8Mhz (other CH32V203x)
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32v20x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(pllmull == 17) pllmull = 18;
+
+      if (pllsource == 0x00)
+      {
+          if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+              SystemCoreClock = HSI_VALUE * pllmull;
+          }
+          else{
+              SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+          }
+      }
+      else
+      {
+#if defined (CH32V20x_D8W)
+        if((RCC->CFGR0 & (3<<22)) == (3<<22))
+        {
+          SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+        }
+        else
+#endif
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+          SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
+#else
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+#endif
+        }
+        else
+        {
+#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
+            SystemCoreClock = (HSE_VALUE>>2) * pllmull;
+#else
+          SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+  //GPIO_IPD_Unused();
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source
+     *  CH32V20x_D6 (HSE=8MHZ)
+     *  CH32V20x_D8 (HSE=32MHZ)
+     *  CH32V20x_D8W (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+#if defined (CH32V20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(3<<22);
+        /* HCLK = SYSCLK/2 */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
+         *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
+         *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
+         */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
+     *  CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     *  CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
+     */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                          RCC_PLLMULL));
+
+    RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI(void)
+{
+    EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+     RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#endif
diff --git a/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.h b/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.h
new file mode 100644
index 0000000..9c8a3f7
--- /dev/null
+++ b/EVT/EXAM/WWDG/WWDG/User/system_ch32v20x.h
@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v20x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : CH32V20x Device Peripheral Access Layer System Header File.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __SYSTEM_ch32v20x_H 
+#define __SYSTEM_ch32v20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V20x_SYSTEM_H */
+
+
+
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diff --git a/EVT/PUB/SCHPCB/CH32F&V208C-R0/CH32F&V208C-R0.SchDoc b/EVT/PUB/SCHPCB/CH32F&V208C-R0/CH32F&V208C-R0.SchDoc
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diff --git a/EVT/PUB/SCHPCB/CH32F&V208G-R0/CH32F&V208G-R0.SchDoc b/EVT/PUB/SCHPCB/CH32F&V208G-R0/CH32F&V208G-R0.SchDoc
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diff --git a/EVT/PUB/SCHPCB/CH32F&V208R_R0/CH32F&V208R-R0-1v1.PcbDoc b/EVT/PUB/SCHPCB/CH32F&V208R-R0/CH32F&V208R-R0-1v1.PcbDoc
similarity index 100%
rename from EVT/PUB/SCHPCB/CH32F&V208R_R0/CH32F&V208R-R0-1v1.PcbDoc
rename to EVT/PUB/SCHPCB/CH32F&V208R-R0/CH32F&V208R-R0-1v1.PcbDoc
diff --git a/EVT/PUB/SCHPCB/CH32F&V208R_R0/CH32F&V208R-R0.SchDoc b/EVT/PUB/SCHPCB/CH32F&V208R-R0/CH32F&V208R-R0.SchDoc
similarity index 100%
rename from EVT/PUB/SCHPCB/CH32F&V208R_R0/CH32F&V208R-R0.SchDoc
rename to EVT/PUB/SCHPCB/CH32F&V208R-R0/CH32F&V208R-R0.SchDoc
diff --git a/EVT/PUB/SCHPCB/CH32F&V208W_R0/CH32F&V208W-R0-1v4.PcbDoc b/EVT/PUB/SCHPCB/CH32F&V208W-R0/CH32F&V208W-R0-1v4.PcbDoc
similarity index 100%
rename from EVT/PUB/SCHPCB/CH32F&V208W_R0/CH32F&V208W-R0-1v4.PcbDoc
rename to EVT/PUB/SCHPCB/CH32F&V208W-R0/CH32F&V208W-R0-1v4.PcbDoc
diff --git a/EVT/PUB/SCHPCB/CH32F&V208W_R0/CH32F&V208W-R0.SchDoc b/EVT/PUB/SCHPCB/CH32F&V208W-R0/CH32F&V208W-R0.SchDoc
similarity index 100%
rename from EVT/PUB/SCHPCB/CH32F&V208W_R0/CH32F&V208W-R0.SchDoc
rename to EVT/PUB/SCHPCB/CH32F&V208W-R0/CH32F&V208W-R0.SchDoc
diff --git a/EVT/PUB/SCHPCB/CH32V20xG8_R0/CH32V20xG8-R0-1v1.PcbDoc b/EVT/PUB/SCHPCB/CH32V20xG8-R0/CH32V20xG8-R0-1v1.PcbDoc
similarity index 100%
rename from EVT/PUB/SCHPCB/CH32V20xG8_R0/CH32V20xG8-R0-1v1.PcbDoc
rename to EVT/PUB/SCHPCB/CH32V20xG8-R0/CH32V20xG8-R0-1v1.PcbDoc
diff --git a/EVT/PUB/SCHPCB/CH32V20xG8_R0/CH32V20xG8-R0.SchDoc b/EVT/PUB/SCHPCB/CH32V20xG8-R0/CH32V20xG8-R0.SchDoc
similarity index 100%
rename from EVT/PUB/SCHPCB/CH32V20xG8_R0/CH32V20xG8-R0.SchDoc
rename to EVT/PUB/SCHPCB/CH32V20xG8-R0/CH32V20xG8-R0.SchDoc