diff --git a/EVT/CH32V20x_List.txt b/EVT/CH32V20x_List.txt index 2c8e32f..e27cd51 100644 --- a/EVT/CH32V20x_List.txt +++ b/EVT/CH32V20x_List.txt @@ -1,5 +1,5 @@ -南京沁恒微电子股份有限公司 2024.02 +南京沁恒微电子股份有限公司 2024.04 最新资料请到我们的网站上查询 https://wch.cn @@ -210,6 +210,7 @@ https://wch.cn | | | | |-- USART_Printf：串口打印调试例程 | | | | |-- USART_SynchronousMode：同步模式，Master/Slave 模式收发例程 | | | | |-- USART_Idle_Recv：串口使用DMA进行不定长接收例程 + | | | | |-- USART_SmartCard：串口智能卡例程 | | | |-- USB | | | | |-- USBD | | | | | |-- CH372：模拟自定义USB设备（CH372设备），端点1，3下传，2，4上传，端点1下传的数据从端点3上传，不取反，端点2下传的数据从端点4上传，取反。 diff --git a/EVT/CH32V20x_List_EN.txt b/EVT/CH32V20x_List_EN.txt index e995dbc..572edf7 100644 --- a/EVT/CH32V20x_List_EN.txt +++ b/EVT/CH32V20x_List_EN.txt @@ -1,5 +1,5 @@ -Nanjing Qinheng Microelectronics Co., Ltd. 2024.02 +Nanjing Qinheng Microelectronics Co., Ltd. 2024.04 https://wch-ic.com @@ -210,6 +210,7 @@ Directory | | | | |-- USART_SynchronousMode: synchronous mode, master/slave mode, transceiver routine | | | | |-- USART_Printf:Serial port printing debugging routines | | | | |-- USART_Idle_Recv锛歎SART use DMA receiving indeterminate length data routines + | | | | |-- USART_SmartCard锛歎SART_SmartCard routines | | | |-- USB | | | | |-- USBD | | | | | |-- CH372:Simulates a custom USB device (CH372 device) with endpoints 1, 3 down and 2, 4 up. Data down from endpoint 1 is uploaded from endpoint 3 and not reversed, and data down from endpoint 2 is uploaded from endpoint 4 and reversed. diff --git a/EVT/EXAM/CAN/TestMode/User/main.c b/EVT/EXAM/CAN/TestMode/User/main.c index f1b8e80..fc22768 100644 --- a/EVT/EXAM/CAN/TestMode/User/main.c +++ b/EVT/EXAM/CAN/TestMode/User/main.c @@ -2,7 +2,7 @@ * File Name : main.c * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2024/04/06 * Description : Main program body. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -234,7 +234,7 @@ int main(void) printf("Receive Data:\r\n"); for(i = 0; i < 8; i++) { - printf("%02x\r\n", txbuf[i]); + printf("%02x\r\n", rxbuf[i]); } } else diff --git a/EVT/EXAM/PWR/PVD_Wakeup/User/main.c b/EVT/EXAM/PWR/PVD_Wakeup/User/main.c index a2969e9..f7e0911 100644 --- a/EVT/EXAM/PWR/PVD_Wakeup/User/main.c +++ b/EVT/EXAM/PWR/PVD_Wakeup/User/main.c @@ -90,7 +90,7 @@ int main(void) printf("Fall asleep...\r\n"); Delay_Ms(100); PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI); - printf("Woke up!!\r\n"); + printf("Wake up!!\r\n"); while (1) { diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h index 2075627..fc5c540 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h @@ -39,7 +39,7 @@ extern "C" { /* CH32V20x Standard Peripheral Library version number */ #define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ -#define __CH32V20x_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */ +#define __CH32V20x_STDPERIPH_VERSION_SUB (0x01) /* [7:0] sub version */ #define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\ |(__CH32V20x_STDPERIPH_VERSION_SUB << 0)) diff --git a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h index 0609d4c..04dfb51 100644 --- a/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h +++ b/EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h @@ -2,7 +2,7 @@ * File Name : ch32v20x_gpio.h * Author : WCH * Version : V1.0.0 - * Date : 2021/06/06 + * Date : 2024/03/02 * Description : This file contains all the functions prototypes for the * GPIO firmware library. ********************************************************************************* @@ -106,7 +106,7 @@ typedef enum #define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ #define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */ #define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ to TIM2 Internal Trigger 1 for calibration \ diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c index 3038063..675552e 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c @@ -2,7 +2,7 @@ * File Name : ch32v20x_gpio.c * Author : WCH * Version : V1.0.0 - * Date : 2023/11/23 + * Date : 2024/05/06 * Description : This file provides all the GPIO firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. @@ -517,9 +517,7 @@ void GPIO_EventOutputCmd(FunctionalState NewState) * GPIO_Remap_ETH - Ethernet remapping * GPIO_Remap_CAN2 - CAN2 remapping * GPIO_Remap_MII_RMII_SEL - MII or RMII selection - * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled - * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected * to TIM2 Internal Trigger 1 for calibration * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) @@ -721,7 +719,10 @@ void GPIO_IPD_Unused(void) |GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1\ |GPIO_Pin_3|GPIO_Pin_4\ |GPIO_Pin_5|GPIO_Pin_8\ |GPIO_Pin_9|GPIO_Pin_10\ @@ -751,7 +752,10 @@ void GPIO_IPD_Unused(void) GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ |GPIO_Pin_4|GPIO_Pin_5\ |GPIO_Pin_6|GPIO_Pin_7\ |GPIO_Pin_8|GPIO_Pin_9\ @@ -780,7 +784,10 @@ void GPIO_IPD_Unused(void) GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ |GPIO_Pin_10|GPIO_Pin_11\ |GPIO_Pin_12|GPIO_Pin_13\ |GPIO_Pin_14|GPIO_Pin_15; @@ -809,7 +816,10 @@ void GPIO_IPD_Unused(void) GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\ |GPIO_Pin_4|GPIO_Pin_9; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOB, &GPIO_InitStructure); @@ -832,7 +842,10 @@ void GPIO_IPD_Unused(void) } case 0x20350500: //CH32V203K6T6 { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ |GPIO_Pin_10|GPIO_Pin_11\ |GPIO_Pin_12|GPIO_Pin_13\ |GPIO_Pin_14|GPIO_Pin_15; @@ -857,7 +870,10 @@ void GPIO_IPD_Unused(void) } case 0x20320500: //CH32V203K8T6 { - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ |GPIO_Pin_10|GPIO_Pin_11\ |GPIO_Pin_12|GPIO_Pin_13\ |GPIO_Pin_14|GPIO_Pin_15; @@ -950,8 +966,11 @@ void GPIO_IPD_Unused(void) |GPIO_Pin_10|GPIO_Pin_15; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ - |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_3\ |GPIO_Pin_4|GPIO_Pin_5\ |GPIO_Pin_9|GPIO_Pin_10\ |GPIO_Pin_11|GPIO_Pin_12\ diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_iwdg.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_iwdg.c index 9f60181..cc7f2f7 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_iwdg.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_iwdg.c @@ -92,7 +92,7 @@ void IWDG_ReloadCounter(void) void IWDG_Enable(void) { IWDG->CTLR = CTLR_KEY_Enable; - while((RCC->RSTSCKR)|(0x2)!=SET); + while((RCC->RSTSCKR & 0x2)==RESET); } /********************************************************************* diff --git a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c index 1b528d1..6c89fed 100644 --- a/EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c +++ b/EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c @@ -21,15 +21,15 @@ #define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ #define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ #define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ -#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ #define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ #define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ #define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ #define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ -#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ -#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ #define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ #define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ @@ -41,7 +41,7 @@ #define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ #define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ -#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ #define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ #define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ diff --git a/EVT/EXAM/TIM/Encoder/User/main.c b/EVT/EXAM/TIM/Encoder/User/main.c index 85344f9..9f52d57 100644 --- a/EVT/EXAM/TIM/Encoder/User/main.c +++ b/EVT/EXAM/TIM/Encoder/User/main.c @@ -69,7 +69,7 @@ void TIM3_Encoder_Init() GPIO_InitTypeDef GPIO_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; diff --git a/EVT/EXAM/USART/USART_SmartCard/.cproject b/EVT/EXAM/USART/USART_SmartCard/.cproject new file mode 100644 index 0000000..10003c3 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/.cproject @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/EVT/EXAM/USART/USART_SmartCard/.project b/EVT/EXAM/USART/USART_SmartCard/.project new file mode 100644 index 0000000..50a004a --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/.project @@ -0,0 +1,61 @@ + + + USART_SmartCard + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + + + Core + 2 + PARENT-2-PROJECT_LOC/SRC/Core + + + Debug + 2 + PARENT-2-PROJECT_LOC/SRC/Debug + + + Ld + 2 + PARENT-2-PROJECT_LOC/SRC/Ld + + + Peripheral + 2 + PARENT-2-PROJECT_LOC/SRC/Peripheral + + + Startup + 2 + PARENT-2-PROJECT_LOC/SRC/Startup + + + diff --git a/EVT/EXAM/USART/USART_SmartCard/.template b/EVT/EXAM/USART/USART_SmartCard/.template new file mode 100644 index 0000000..f43112f --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/.template @@ -0,0 +1,17 @@ +Mcu Type=CH32V20x +Address=0x08000000 +Target Path=obj\USART_SmartCard.hex +Erase All=true +Program=true +Verify=true +Reset=true + +Vendor=WCH +Link=WCH-Link +Toolchain=RISC-V +Series=CH32V203 +Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. + +PeripheralVersion=1.0 +MCU=CH32V203RBT6 +CLKSpeed=1 diff --git a/EVT/EXAM/USART/USART_SmartCard/USART_SmartCard.wvproj b/EVT/EXAM/USART/USART_SmartCard/USART_SmartCard.wvproj new file mode 100644 index 0000000..2cd99d9 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/USART_SmartCard.wvproj @@ -0,0 +1,2 @@ +iCZ ?"莵竢焷F<.勄趴?/O┠緾hQN$*籈Bk!2t+buh唍Ub]xl媗| ++"<摨AH42}z8p;mu1-h籓d聎氮7x{5丆qEx=;Βe⒑2 偒*BP M" \ No newline at end of file diff --git a/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_conf.h b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_conf.h new file mode 100644 index 0000000..d1eeb38 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_conf.h @@ -0,0 +1,42 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_conf.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_CONF_H +#define __CH32V20x_CONF_H + +#include "ch32v20x_adc.h" +#include "ch32v20x_bkp.h" +#include "ch32v20x_can.h" +#include "ch32v20x_crc.h" +#include "ch32v20x_dbgmcu.h" +#include "ch32v20x_dma.h" +#include "ch32v20x_exti.h" +#include "ch32v20x_flash.h" +#include "ch32v20x_gpio.h" +#include "ch32v20x_i2c.h" +#include "ch32v20x_iwdg.h" +#include "ch32v20x_pwr.h" +#include "ch32v20x_rcc.h" +#include "ch32v20x_rtc.h" +#include "ch32v20x_spi.h" +#include "ch32v20x_tim.h" +#include "ch32v20x_usart.h" +#include "ch32v20x_wwdg.h" +#include "ch32v20x_it.h" +#include "ch32v20x_misc.h" + + +#endif /* __CH32V20x_CONF_H */ + + + + + diff --git a/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c new file mode 100644 index 0000000..f2598c2 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.c @@ -0,0 +1,42 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.h b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.h new file mode 100644 index 0000000..f68b203 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/User/ch32v20x_it.h @@ -0,0 +1,20 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v20x_it.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : This file contains the headers of the interrupt handlers. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V20x_IT_H +#define __CH32V20x_IT_H + +#include "debug.h" + + +#endif /* __CH32V20x_IT_H */ + + diff --git a/EVT/EXAM/USART/USART_SmartCard/User/main.c b/EVT/EXAM/USART/USART_SmartCard/User/main.c new file mode 100644 index 0000000..6044a5a --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/User/main.c @@ -0,0 +1,404 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : main.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/02/20 + * Description : Main program body. + ********************************************************************************* + * Copyright (c) 2024 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +/* + *@Note + This example shows that the USART peripheral is configured in smart card mode + and reads ATR data, and then attempts to read the data in T=0 mode. + pins: + SMARTCARD_CK -- PA4 + SMARTCARD_IO -- PA2 + SMARTCARD_RST -- PA5 + SMARTCARD_VCC -- 3.3V + * + */ + +#include "debug.h" +#include "string.h" + +/* Paramenters */ +#define ATR_MAX_SIZE ((uint8_t)33) /* Maximum size of ATR byte array */ +#define ATR_MAX_HISTORICAL ((uint8_t)15) /* Maximum number of historical bytes */ +#define ATR_MAX_PROTOCOLS ((uint8_t)7) /* Maximun number of protocols */ +#define ATR_MAX_IB ((uint8_t)4) /* Maximum number of interface bytes per protocol */ +#define ATR_INTERFACE_BYTE_TA ((uint8_t)0) /* Interface byte TAi */ +#define ATR_INTERFACE_BYTE_TB ((uint8_t)1) /* Interface byte TBi */ +#define ATR_INTERFACE_BYTE_TC ((uint8_t)2) /* Interface byte TCi */ +#define ATR_INTERFACE_BYTE_TD ((uint8_t)3) /* Interface byte TDi */ + +#define STATE_PARSE_TS 1 +#define STATE_PARSE_T0 2 +#define STATE_PARSE_TA 3 +#define STATE_PARSE_TB 4 +#define STATE_PARSE_TC 5 +#define STATE_PARSE_TD 6 +#define STATE_PARSE_HIST_BYTES 7 +#define STATE_PARSE_TCK 8 +#define STATE_PARSE_END 255 + +#define LC_MAX (20) +#define RST_PIN GPIO_Pin_5 + +typedef struct { + uint32_t length; + uint8_t TS; /* Initial character */ + uint8_t T0; /* Format character */ + + struct { + uint8_t value; /* The value of the Interface byte */ + uint8_t present; /* The presence of the Interface byte */ + } ib[ATR_MAX_PROTOCOLS][ATR_MAX_IB], TCK; /* Interface bytes, TCK */ + + uint8_t pn; /* Protocol number: the value of i of the Interface bytes */ + uint8_t Ti[ATR_MAX_HISTORICAL]; /* Historical bytes table */ + uint8_t Tin; /* Historical bytes number */ + int8_t protocol; +} ATR_TypeDef; + +int ATR_Parse(ATR_TypeDef *atr, uint8_t *atr_buf, int32_t len) { + uint8_t data; + uint8_t TCK = 0; + uint8_t K = 0; + uint8_t Yi = 0; + int32_t k, state, index, length, protocol; + uint8_t *ptr; + + length = len; + ptr = atr_buf; + state = STATE_PARSE_TS; + index = 0; + k = 0; + protocol = 0; + + while (ptr < (atr_buf + length)) { + data = *ptr++; + if (state != STATE_PARSE_TS) { + TCK ^= data; + } + + switch (state) { + case STATE_PARSE_TS: + atr->TS = data; + printf("Ts=%x \n", data); + if (data == 0x3b) { + state = STATE_PARSE_T0; + } else if (data == 0x03) { + printf("not support\n"); + return 1; + } else { + printf("error Ts\n"); + return 1; + } + break; + case STATE_PARSE_T0: + atr->T0 = data; + atr->Tin = data & 0x0f; + printf("T0=%x\n", data); + printf("Historical bytes number=%d\n", data & 0x0f); + K = data & 0x0F; + Yi = data; + if (data & 0x10) { + state = STATE_PARSE_TA; + } else if (data & 0x20) { + state = STATE_PARSE_TB; + } else { + if (data & 0x40) { + state = STATE_PARSE_TC; + } else if (data & 0x80) { + state = STATE_PARSE_TD; + } else { + state = STATE_PARSE_HIST_BYTES; + } + } + break; + case STATE_PARSE_TA: + printf("TA%d=%x \n", index, data); + atr->ib[index][ATR_INTERFACE_BYTE_TA].present = 1; + atr->ib[index][ATR_INTERFACE_BYTE_TA].value = data; + if (Yi & 0x20) { + state = STATE_PARSE_TB; + } else if (Yi & 0x40) { + state = STATE_PARSE_TC; + } else if (Yi & 0x80) { + state = STATE_PARSE_TD; + } else { + state = STATE_PARSE_HIST_BYTES; + } + break; + case STATE_PARSE_TB: + printf("TB%d=%x \n", index, data); + atr->ib[index][ATR_INTERFACE_BYTE_TB].present = 1; + atr->ib[index][ATR_INTERFACE_BYTE_TB].value = data; + if (Yi & 0x40) { + state = STATE_PARSE_TC; + } else if (Yi & 0x80) { + state = STATE_PARSE_TD; + } else { + state = STATE_PARSE_HIST_BYTES; + } + break; + case STATE_PARSE_TC: + printf("TC%d=%x \n", index, data); + atr->ib[index][ATR_INTERFACE_BYTE_TC].present = 1; + atr->ib[index][ATR_INTERFACE_BYTE_TC].value = data; + if (Yi & 0x80) { + state = STATE_PARSE_TD; + } else { + state = STATE_PARSE_HIST_BYTES; + } + break; + case STATE_PARSE_TD: + + Yi = data; + printf("TD%d=%x \n", index, data); + atr->ib[index][ATR_INTERFACE_BYTE_TD].present = 1; + atr->ib[index][ATR_INTERFACE_BYTE_TD].value = data; + if (index == 0) { + protocol = Yi & 0x0F; + } + index++; + atr->pn = index; + + if (Yi & 0xF0) { + if (Yi & 0x10) { + /* TAx character present */ + state = STATE_PARSE_TA; + } else if (Yi & 0x20) { + /* TBx character present */ + state = STATE_PARSE_TB; + } else if (Yi & 0x40) { + /* TCx character present */ + state = STATE_PARSE_TC; + } else if (Yi & 0x80) { + /* TDx character present */ + state = STATE_PARSE_TD; + } else { + state = STATE_PARSE_HIST_BYTES; + } + } else { + state = STATE_PARSE_HIST_BYTES; + } + break; + case STATE_PARSE_HIST_BYTES: + if (K) { + + if (k < K) { + atr->Ti[k] = data; + printf("T[%d]=%x\n", k, data); + k++; + if (k == K) { + if (protocol > 0) { + state = STATE_PARSE_TCK; + } + } + } + break; + } + case STATE_PARSE_TCK: + atr->TCK.present = 1; + atr->TCK.value = data; + printf("get TCK %x\n", data); + if (TCK) { + // TCK != 0 + printf("TCK error\n"); + return 1; + } + // printf("cal TCK result %x\n", TCK); + break; + } + if (state == STATE_PARSE_HIST_BYTES && K == 0 && protocol == 0) + break; + } + + atr->protocol = protocol; + return 0; +} + +void USART2_ReCFG(void) { + GPIO_InitTypeDef GPIO_InitStructure = {0}; + USART_InitTypeDef USART_InitStructure = {0}; + USART_ClockInitTypeDef USART_ClockInitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + + /* USART2 Ck-->A.4 TX-->A.2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + USART_ClockInitStructure.USART_Clock = USART_Clock_Enable; + USART_ClockInit(USART2, &USART_ClockInitStructure); + + USART_InitStructure.USART_BaudRate = 9600; + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + USART_InitStructure.USART_StopBits = USART_StopBits_1_5; + USART_InitStructure.USART_Parity = USART_Parity_Even; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + USART_Init(USART2, &USART_InitStructure); + + USART_Cmd(USART2, ENABLE); + + /// Enable NACK transmission + USART_SmartCardNACKCmd(USART2, ENABLE); + + /// Enable Smartcard mode + USART_SmartCardCmd(USART2, ENABLE); + + USART_SetPrescaler(USART2, 5); + USART_SetGuardTime(USART2, 15); +} + +void RST_Init() { + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = RST_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOA, RST_PIN); +} + +void SC_ClearUart() { + int32_t i = 0; + while (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == SET) { + i++; + if (i > 1) { + break; + } + USART_ReceiveData(USART2); + } +} + +void SC_TransmitData(uint8_t *data, uint16_t size) { + uint8_t dat = 0; + for (uint8_t index = 0; index < size; index++) { + dat = data[index]; + USART_SendData(USART2, dat); + while (USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET) { + } + } + while (USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET) { + } +} + +void SC_ReceiveData(uint8_t *data, uint16_t *size) { + uint32_t i = 0, t = 0; + SC_ClearUart(); + while (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == RESET) { + t++; + Delay_Ms(1); + if (t > 10) { + break; + } + } + t = 0; + while (1) { + if (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == SET) { + data[i] = USART_ReceiveData(USART2); + i++; + t = 0; + } else if (t < 10) { + Delay_Ms(1); + t++; + } else { + break; + } + } + *size = i; +} + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) { + ATR_TypeDef atr = {0}; /* Answer To Reset structure */ + + uint8_t pps[] = {0xff, 0x00, 0xff}; + uint8_t testcmd[] = {0x00, 0x84, 0x00, 0x00, 0x08}; + uint8_t recvbuf[ATR_MAX_SIZE] = {0}; + uint16_t recvpos = 0; + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + SystemCoreClockUpdate(); + Delay_Init(); + USART_Printf_Init(115200); + printf("SystemClk:%d\r\n", SystemCoreClock); + printf("ChipID:%08x\r\n", DBGMCU_GetCHIPID()); + printf("USART SmartCard TEST\r\n"); + RST_Init(); + USART2_ReCFG(); /* USART2 INIT */ + + GPIO_ResetBits(GPIOA, RST_PIN); + Delay_Ms(1); + GPIO_SetBits(GPIOA, RST_PIN); + + // try to get ATR + SC_ReceiveData(recvbuf, &(recvpos)); + + if (recvpos == 0) { + printf("cannot get atr\n"); + printf("end\n"); + while (1) { + } + } + + if (ATR_Parse(&atr, recvbuf, recvpos) != 0) { + printf("end\n"); + while (1) { + } + } + + printf("mode T=%d \n", atr.protocol); + if (atr.protocol != 0) { + recvpos = 0; + // send pps + SC_TransmitData(pps, 3); + SC_ReceiveData(recvbuf, &(recvpos)); + if (memcmp(pps, recvbuf, recvpos) != 0) { + printf("cannot switch to T=0 mode\n"); + printf("end\n"); + while (1) { + } + } else { + printf("switch to T=0 mode\n"); + } + } + + SC_TransmitData(testcmd, 5); + SC_ReceiveData(recvbuf, &(recvpos)); + + for (int i = 0; i < recvpos; i++) { + printf("[%d]=%x \n", i, recvbuf[i]); + } + printf("SW1 = %x \n", recvbuf[recvpos - 2]); + printf("SW2 = %x \n", recvbuf[recvpos - 1]); + if (recvbuf[recvpos - 2] == 0x90 && recvbuf[recvpos - 1] == 0x00 && recvpos == 11) { + printf("success\n"); + } + printf("end\n"); + while (1) { + } +} diff --git a/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c b/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c new file mode 100644 index 0000000..2846805 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.c @@ -0,0 +1,987 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Source File. + * For HSE = 32Mhz (CH32V208x/CH32V203RBT6) + * For HSE = 8Mhz (other CH32V203x) +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v20x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +#define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +//#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE( void ); +#elif defined SYSCLK_FREQ_144MHz_HSE +static void SetSysClockTo144_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI( void ); +#elif defined SYSCLK_FREQ_144MHz_HSI +static void SetSysClockTo144_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if(pllmull == 17) pllmull = 18; + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ + SystemCoreClock = HSI_VALUE * pllmull; + } + else{ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#if defined (CH32V20x_D8W) + if((RCC->CFGR0 & (3<<22)) == (3<<22)) + { + SystemCoreClock = ((HSE_VALUE>>1)) * pllmull; + } + else +#endif + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull; +#else + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; +#endif + } + else + { +#if defined (CH32V20x_D8) || defined (CH32V20x_D8W) + SystemCoreClock = (HSE_VALUE>>2) * pllmull; +#else + SystemCoreClock = HSE_VALUE * pllmull; +#endif + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source + * CH32V20x_D6 (HSE=8MHZ) + * CH32V20x_D8 (HSE=32MHZ) + * CH32V20x_D8W (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { +#if defined (CH32V20x_D8W) + RCC->CFGR0 |= (uint32_t)(3<<22); + /* HCLK = SYSCLK/2 */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; +#else + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; +#endif + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ) + * CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + * CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ) + */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#endif diff --git a/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.h b/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.h new file mode 100644 index 0000000..9c8a3f7 --- /dev/null +++ b/EVT/EXAM/USART/USART_SmartCard/User/system_ch32v20x.h @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v20x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : CH32V20x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_ch32v20x_H +#define __SYSTEM_ch32v20x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V20x_SYSTEM_H */ + + + diff --git a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/usb_desc.c b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/usb_desc.c index 9872b6e..d523c39 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/usb_desc.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/CompatibilityHID/User/usb_desc.c @@ -24,7 +24,7 @@ const uint8_t MyDevDescr[] = 0x00, // bDeviceProtocol DEF_USBD_UEP0_SIZE, // bMaxPacketSize0 (uint8_t)DEF_USB_VID, (uint8_t)(DEF_USB_VID >> 8), // idVendor 0x1A86 - (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0xE6E1 + (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0xFE07 0x00, DEF_IC_PRG_VER, // bcdDevice 1.00 0x01, // iManufacturer (String Index) 0x02, // iProduct (String Index) diff --git a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/usb_desc.c b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/usb_desc.c index 827d9eb..ad4ea0e 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/usb_desc.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/MSC_CD-ROM/User/usb_desc.c @@ -24,7 +24,7 @@ const uint8_t MyDevDescr[] = 0x00, // bDeviceProtocol DEF_USBD_UEP0_SIZE, // bMaxPacketSize0 64 (uint8_t)DEF_USB_VID, (uint8_t)(DEF_USB_VID >> 8), // idVendor 0x1A86 - (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0xFE10 + (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0xFE11 DEF_IC_PRG_VER, 0x00, // bcdDevice 0.01 0x01, // iManufacturer (String Index) 0x02, // iProduct (String Index) diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c index 4d25126..b0f77cb 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC-HID/User/USB_Device/usb_desc.c @@ -24,7 +24,7 @@ const uint8_t MyDevDescr[ ] = 0x00, // bDeviceProtocol DEF_USBD_UEP0_SIZE, // bMaxPacketSize0 64 (uint8_t)DEF_USB_VID, (uint8_t)(DEF_USB_VID >> 8), // idVendor 0x1A86 - (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0x5537 + (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0xFE0C DEF_IC_PRG_VER, 0x00, // bcdDevice 0.01 0x01, // iManufacturer (String Index) 0x02, // iProduct (String Index) diff --git a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/usb_desc.c b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/usb_desc.c index 5d940cb..a7eaa72 100644 --- a/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/usb_desc.c +++ b/EVT/EXAM/USB/USBFS/DEVICE/SimulateCDC/User/USB_Device/usb_desc.c @@ -24,7 +24,7 @@ const uint8_t MyDevDescr[] = 0x00, // bDeviceProtocol DEF_USBD_UEP0_SIZE, // bMaxPacketSize0 64 (uint8_t)DEF_USB_VID, (uint8_t)(DEF_USB_VID >> 8), // idVendor 0x1A86 - (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0x5537 + (uint8_t)DEF_USB_PID, (uint8_t)(DEF_USB_PID >> 8), // idProduct 0xFE0C DEF_IC_PRG_VER, 0x00, // bcdDevice 0.01 0x01, // iManufacturer (String Index) 0x02, // iProduct (String Index) diff --git a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/Host_UDisk/Udisk_Func_BasicOp.c b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/Host_UDisk/Udisk_Func_BasicOp.c index a212c9a..03b4a3f 100644 --- a/EVT/EXAM/USB/USBFS/HOST_Udisk/User/Host_UDisk/Udisk_Func_BasicOp.c +++ b/EVT/EXAM/USB/USBFS/HOST_Udisk/User/Host_UDisk/Udisk_Func_BasicOp.c @@ -93,6 +93,20 @@ void UDisk_USBH_ByteOperation( void ) mStopIfError( ret ); printf("成功写入 %02X次\r\n",(uint16_t)t); } + + //演示修改文件属性 + printf( "Modify\r\n" ); + mCmdParam.Modify.mFileAttr = 0xff; //输入参数: 新的文件属性,为0FFH则不修改 + mCmdParam.Modify.mFileTime = 0xffff; //输入参数: 新的文件时间,为0FFFFH则不修改,使用新建文件产生的默认时间 + mCmdParam.Modify.mFileDate = MAKE_FILE_DATE( 2015, 5, 18 ); //输入参数: 新的文件日期: 2015.05.18 + mCmdParam.Modify.mFileSize = 0xffffffff; // 输入参数: 新的文件长度,以字节为单位写文件应该由程序库关闭文件时自动更新长度,所以此处不修改 + i = CHRV3FileModify( ); //修改当前文件的信息,修改日期 + mStopIfError( i ); + printf( "Close\r\n" ); + mCmdParam.Close.mUpdateLen = 1; //自动计算文件长度,以字节为单位写文件,建议让程序库关闭文件以便自动更新文件长度 + i = CHRV3FileClose( ); + mStopIfError( i ); + /* 二、读取文件前N字节 */ TotalCount = 60; //设置准备读取总长度100字节 strcpy( (char *)mCmdParam.Open.mPathName, "/NEWFILE.C" ); //设置将要操作的文件路径和文件名/C51/NEWFILE.C