332 lines
8.5 KiB
C
332 lines
8.5 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32v20x.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/06/26
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* Description : CH32V20x Device Peripheral Access Layer System Source File.
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* For HSE = 32Mhz (CH32V208x/CH32V203RBT)
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* For HSE = 8Mhz (other CH32V203x)
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v20x.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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*/
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//#define SYSCLK_FREQ_24MHz 24000000
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//#define SYSCLK_FREQ_48MHz 48000000
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#define SYSCLK_FREQ_72MHz 72000000
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/* Clock Definitions */
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#ifdef SYSCLK_FREQ_24MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */
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#endif
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* system_private_function_proto_types */
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_24MHz
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static void SetSysClockTo24(void);
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#elif defined SYSCLK_FREQ_48MHz
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static void SetSysClockTo48(void);
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#elif defined SYSCLK_FREQ_72MHz
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static void SetSysClockTo72(void);
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#endif
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* the PLL and update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit (void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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RCC->CFGR0 &= (uint32_t)0xF0FF0000;
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RCC->CTLR &= (uint32_t)0xFEF6FFFF;
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RCC->CTLR &= (uint32_t)0xFFFBFFFF;
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RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
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RCC->INTR = 0x009F0000;
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SetSysClock();
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
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tmp = RCC->CFGR0 & RCC_SWS;
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switch (tmp)
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{
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case 0x00:
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04:
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08:
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pllmull = RCC->CFGR0 & RCC_PLLMULL;
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pllsource = RCC->CFGR0 & RCC_PLLSRC;
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pllmull = ( pllmull >> 18) + 2;
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if(pllmull == 17) pllmull = 18;
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if (pllsource == 0x00)
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{
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if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
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SystemCoreClock = HSI_VALUE * pllmull;
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}
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else{
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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}
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}
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else
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{
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#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
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if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
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{
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SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
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}
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else
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#endif
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if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
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{
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#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
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SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
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#else
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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#endif
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}
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else
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{
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#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
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SystemCoreClock = (HSE_VALUE>>2) * pllmull;
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#else
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SystemCoreClock = HSE_VALUE * pllmull;
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#endif
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}
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}
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if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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SystemCoreClock >>= tmp;
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_24MHz
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SetSysClockTo24();
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#elif defined SYSCLK_FREQ_48MHz
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SetSysClockTo48();
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#elif defined SYSCLK_FREQ_72MHz
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SetSysClockTo72();
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#endif
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}
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#ifdef SYSCLK_FREQ_24MHz
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/*********************************************************************
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* @fn SetSysClockTo24
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*
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* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo24(void)
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{
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#if (PLL_Source == HSI)
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EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
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#endif
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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#if (PLL_Source == HSI)
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/* PLL configuration: PLLCLK = HSI * 3 = 24 MHz */
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL3);
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#else
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/* PLL configuration: PLLCLK = HSI/2 * 6 = 24 MHz */
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RCC->CFGR0 |= (uint32_t)(RRCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
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#endif
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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#elif defined SYSCLK_FREQ_48MHz
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/*********************************************************************
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* @fn SetSysClockTo48
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*
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo48(void)
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{
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#if (PLL_Source == HSI)
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EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
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#endif
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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#if (PLL_Source == HSI)
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/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
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#else
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/* PLL configuration: PLLCLK = HSI/2 * 12 = 48 MHz */
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
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#endif
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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#elif defined SYSCLK_FREQ_72MHz
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/*********************************************************************
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* @fn SetSysClockTo72
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*
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo72(void)
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{
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#if (PLL_Source == HSI)
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EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
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#endif
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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#if (PLL_Source == HSI)
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/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
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#else
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/* PLL configuration: PLLCLK = HSI/2 * 18 = 72 MHz */
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
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#endif
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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#endif
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