127 lines
3.7 KiB
C
127 lines
3.7 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32v20x.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : CH32V20x Device Peripheral Access Layer System Source File.
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* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
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* For HSE = 8Mhz (other CH32V203x)
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v20x.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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* If none of the define below is enabled, the HSI is used as System clock source.
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*/
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/* Clock Definitions */
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uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
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__I uint8_t AHBPrescTable[16] =
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{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
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/* system_private_function_proto_types */
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static void SetSysClock(void);
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* the PLL and update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit(void) {
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RCC->CTLR |= (uint32_t) 0x00000001;
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RCC->CFGR0 &= (uint32_t) 0xF8FF0000;
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RCC->CTLR &= (uint32_t) 0xFEF6FFFF;
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RCC->CTLR &= (uint32_t) 0xFFFBFFFF;
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RCC->CFGR0 &= (uint32_t) 0xFF80FFFF;
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RCC->INTR = 0x009F0000;
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SetSysClock();
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate(void) {
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
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tmp = RCC->CFGR0 & RCC_SWS;
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switch (tmp) {
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case 0x00:
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04:
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08:
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pllmull = RCC->CFGR0 & RCC_PLLMULL;
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pllsource = RCC->CFGR0 & RCC_PLLSRC;
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pllmull = (pllmull >> 18) + 2;
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if (pllmull == 17)
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pllmull = 18;
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if (pllsource == 0x00) {
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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}
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else
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{
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if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t) RESET)
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{
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#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
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SystemCoreClock = ((HSE_VALUE >> 2) >> 1) * pllmull;
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#else
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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#endif
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}
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else
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{
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#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
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SystemCoreClock = (HSE_VALUE >> 2) * pllmull;
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#else
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SystemCoreClock = HSE_VALUE * pllmull;
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#endif
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}
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}
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if (Pll_6_5 == 1)
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SystemCoreClock = (SystemCoreClock / 2);
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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SystemCoreClock >>= tmp;
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClock(void) {
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/* If none of the define above is enabled, the HSI is used as System clock
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* source (default after reset)
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*/
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}
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