118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : main.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/08/23
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* Description : Main program body.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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/*
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*@Note
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*TIMER_INT
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*MODE 1 Timer count triggers update interrupt. Updata_time = psc*arr*RepetitionCounter/system
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*MODE 2 generates an update event and triggers an update interrupt.
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*
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*/
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#include "debug.h"
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/* Mode Definition */
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#define MODE1 0
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#define MODE2 1
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/* Mode Selection */
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#define MODE MODE1
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//#define MODE MODE2
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/*********************************************************************
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* @fn TIM1_UP_IRQHandler
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*
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* @brief This function handles TIM1 UP exception.
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*
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*
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* @return none
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*/
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void TIM1_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void TIM1_UP_IRQHandler(void)
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{
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if(TIM_GetITStatus(TIM1, TIM_IT_Update)==SET)
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{
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printf("--------updata\r\n");
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}
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TIM_ClearITPendingBit( TIM1, TIM_IT_Update );
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}
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/*********************************************************************
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* @fn TIM1_INT_Init
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*
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* @brief Initializes TIM1 output compare.
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*
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* @param arr - the period value.
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* psc - the prescaler value.
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*
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* @return none
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*/
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void TIM1_INT_Init( u16 arr, u16 psc)
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{
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NVIC_InitTypeDef NVIC_InitStructure={0};
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TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure={0};
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE );
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TIM_TimeBaseInitStructure.TIM_Period = arr;
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TIM_TimeBaseInitStructure.TIM_Prescaler = psc;
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TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
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TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInitStructure.TIM_RepetitionCounter = 50;
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TIM_TimeBaseInit( TIM1, &TIM_TimeBaseInitStructure);
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TIM_ClearITPendingBit( TIM1, TIM_IT_Update );
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NVIC_InitStructure.NVIC_IRQChannel =TIM1_UP_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority =1;
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NVIC_InitStructure.NVIC_IRQChannelCmd =ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
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}
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/*********************************************************************
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* @fn main
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*
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* @brief Main program.
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*
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* @return none
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*/
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int main(void)
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{
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SystemCoreClockUpdate();
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Delay_Init();
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#if (SDI_PRINT == SDI_PR_OPEN)
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SDI_Printf_Enable();
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#else
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USART_Printf_Init(115200);
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#endif
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printf("SystemClk:%d\r\n",SystemCoreClock);
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printf( "ChipID:%08x\r\n", DBGMCU_GetCHIPID() );
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TIM1_INT_Init( 200-1, 48000-1);
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#if(MODE==MODE1)
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TIM_Cmd( TIM1, ENABLE );//5S
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#elif(MODE==MODE2)
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TIM_GenerateEvent(TIM1, TIM_IT_Update);
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#endif
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while(1);
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}
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