bstanwell/wch-uf2-example
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micro-optimizations in startup assembly code

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R
2024-04-14 04:08:13 +01:00
parent 394046a4b1
commit 8feb1d2ea8
2 changed files with 2 additions and 5 deletions
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bootloader.c
-3
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@@ -296,9 +296,6 @@ __attribute__((always_inline)) static inline void synthesize_block(uint32_t bloc
} }
__attribute__((naked)) int main(void) { __attribute__((naked)) int main(void) {
// Don't reenter bootloader again
R16_BKP_DATAR10 = 0;
// PLL setup: system clock 96 MHz // PLL setup: system clock 96 MHz
R32_EXTEN_CTR |= (1 << 4); // sneaky div2 R32_EXTEN_CTR |= (1 << 4); // sneaky div2
R32_RCC_CFGR0 = (R32_RCC_CFGR0 & ~0xff0000) | (0b01101000 << 16); R32_RCC_CFGR0 = (R32_RCC_CFGR0 & ~0xff0000) | (0b01101000 << 16);
startup.S
+2 -2
View File
@@ -28,7 +28,7 @@ _start:
la a0, RCC_BASE la a0, RCC_BASE
lw a1, (R32_RCC_RSTSCKR-RCC_BASE)(a0) lw a1, (R32_RCC_RSTSCKR-RCC_BASE)(a0)
slli a1, a1, (31 - 26) slli a1, a1, (31 - 26)
bgez a1, _enter_application_code // if PINRSTF == 0 bgez a1, _bootloader_limit // if PINRSTF == 0
// Enable BKP and PWR clock // Enable BKP and PWR clock
lw a1, (R32_RCC_APB1PCENR-RCC_BASE)(a0) lw a1, (R32_RCC_APB1PCENR-RCC_BASE)(a0)
@@ -66,7 +66,6 @@ _start:
// Delay done, clear systick and magic // Delay done, clear systick and magic
sw zero, (STK_CTLR-SYSTICK_BASE)(a0) sw zero, (STK_CTLR-SYSTICK_BASE)(a0)
sw zero, (STK_SR-SYSTICK_BASE)(a0) sw zero, (STK_SR-SYSTICK_BASE)(a0)
sh zero, (a3)
// If the delay expires, boot the application after all // If the delay expires, boot the application after all
_enter_application_code_magic: _enter_application_code_magic:
@@ -86,6 +85,7 @@ _enter_application_code:
j _bootloader_limit j _bootloader_limit
_enter_bootloader: _enter_bootloader:
sh zero, (a3)
la gp, 0 la gp, 0
la sp, 0 la sp, 0