bstanwell/wch-uf2-example
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xxx try to fix ram boot bug

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ram boot doesn't seem to work if there's no flash application for some reason
This commit is contained in:
R
2024-04-14 18:10:59 +01:00
parent c2665c139d
commit b490e6917d
2 changed files with 17 additions and 5 deletions
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bootloader.c
+9
View File
@@ -188,6 +188,8 @@ extern uint32_t UF2_GOT_BLOCKS[36];
#define R16_BKP_DATAR10 (*(volatile uint32_t*)0x40006C28) #define R16_BKP_DATAR10 (*(volatile uint32_t*)0x40006C28)
#define R32_PWR_CTLR (*(volatile uint32_t*)0x40007000)
#define R32_RCC_CTLR (*(volatile uint32_t*)0x40021000) #define R32_RCC_CTLR (*(volatile uint32_t*)0x40021000)
#define R32_RCC_CFGR0 (*(volatile uint32_t*)0x40021004) #define R32_RCC_CFGR0 (*(volatile uint32_t*)0x40021004)
#define R32_RCC_APB2PCENR (*(volatile uint32_t*)0x40021018) #define R32_RCC_APB2PCENR (*(volatile uint32_t*)0x40021018)
@@ -348,6 +350,11 @@ static void make_msc_csw(uint32_t dCSWTag, uint32_t error) {
} }
__attribute__((naked)) int main(void) { __attribute__((naked)) int main(void) {
// Make sure this stuff is enabled
R32_RCC_APB1PCENR |= (1 << 27) | (1 << 28);
R32_PWR_CTLR |= 1 << 8;
R16_BKP_DATAR10 = 0;
// PLL setup: system clock 96 MHz // PLL setup: system clock 96 MHz
R32_EXTEN_CTR |= (1 << 4); // sneaky div2 R32_EXTEN_CTR |= (1 << 4); // sneaky div2
R32_RCC_CFGR0 = (R32_RCC_CFGR0 & ~0xff0000) | (0b01101000 << 16); R32_RCC_CFGR0 = (R32_RCC_CFGR0 & ~0xff0000) | (0b01101000 << 16);
@@ -855,6 +862,8 @@ __attribute__((naked)) int main(void) {
R32_EXTEN_CTR &= ~(1 << 1); R32_EXTEN_CTR &= ~(1 << 1);
if (ADDRESS_HI >> 8 == 0x20) { if (ADDRESS_HI >> 8 == 0x20) {
// ram boot // ram boot
R32_RCC_CFGR0 = (R32_RCC_CFGR0 & ~0b11) | 0b00;
while ((R32_RCC_CFGR0 & 0b1100) != 0b0000) {}
((void (*)())0x20000000)(); ((void (*)())0x20000000)();
} else { } else {
// wtf why does this work and the other stuff doesn't? // wtf why does this work and the other stuff doesn't?
startup.S
+8 -5
View File
@@ -19,6 +19,12 @@
.global _start .global _start
_start: _start:
// Weird things seem to happen if you fall off the end of flash
la a0, _bootloader_limit
lw a0, (a0)
la a1, 0xe339e339
beq a0, a1, _enter_bootloader
// Use Adafruit(?)-inspired boot entry, namely "double-reset in short succession to enter bootloader" // Use Adafruit(?)-inspired boot entry, namely "double-reset in short succession to enter bootloader"
// 1. If the reset wasn't triggered by the nRST pin, go to application // 1. If the reset wasn't triggered by the nRST pin, go to application
// 2. On nRST, if not first reset, go to bootloader // 2. On nRST, if not first reset, go to bootloader
@@ -45,7 +51,7 @@ _start:
la a3, R16_BKP_DATAR10 la a3, R16_BKP_DATAR10
lhu a1, (a3) lhu a1, (a3)
la a2, BOOT_MAGIC_APP_IMMEDIATELY la a2, BOOT_MAGIC_APP_IMMEDIATELY
beq a1, a2, _enter_application_code_magic beq a1, a2, _enter_application_code
la a2, BOOT_MAGIC_BOOTLOADER la a2, BOOT_MAGIC_BOOTLOADER
beq a1, a2, _enter_bootloader beq a1, a2, _enter_bootloader
@@ -68,9 +74,8 @@ _start:
sw zero, (STK_SR-SYSTICK_BASE)(a0) sw zero, (STK_SR-SYSTICK_BASE)(a0)
// If the delay expires, boot the application after all // If the delay expires, boot the application after all
_enter_application_code_magic:
sh zero, (a3)
_enter_application_code: _enter_application_code:
sh zero, (a3)
// Clear all of these enables that we had set // Clear all of these enables that we had set
la a0, R32_PWR_CTLR la a0, R32_PWR_CTLR
lw a1, (a0) lw a1, (a0)
@@ -85,8 +90,6 @@ _enter_application_code:
j _bootloader_limit j _bootloader_limit
_enter_bootloader: _enter_bootloader:
sh zero, (a3)
// Set up global pointer // Set up global pointer
.option push .option push
.option norelax .option norelax