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# WCH RISC-V UF2 Bootloader # WCH RISC-V UF2 Bootloader
This code implements a [uf2](https://github.com/microsoft/uf2) bootloader for RISC-V microcontrollers from [WCH](https://www.wch-ic.com). This allows user-friendly uploading of code by dragging files onto a virtual USB Mass Storage device (i.e. a pretend thumb drive). This means that, unlike the vendor ISP bootloader, no special software is required.
## Usage notes
- Triggered by a double reset within 0.5 seconds (like Adafruit bootloaders) - Triggered by a double reset within 0.5 seconds (like Adafruit bootloaders)
- Needs usage of `R16_BKP_DATAR10` - Needs usage of `R16_BKP_DATAR10`
- Write 0x4170 ('Ap') to boot into the application immediately without delay - Write 0x4170 ('Ap') to boot into the application immediately without delay
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- Note that USBD requires a USB A-A cable if using the official devkit - Note that USBD requires a USB A-A cable if using the official devkit
- Runs off of internal 8 MHz oscillator (despite stability concerns) - Runs off of internal 8 MHz oscillator (despite stability concerns)
- The HSI oscillator's tolerance (-1.0% to +1.6%) is well outside of the range specified for USB full speed ($\pm$ 0.25%), but it seems to work in practice n=1 ¯\\\_(ツ)\_/¯ - The HSI oscillator's tolerance (-1.0% to +1.6%) is well outside of the range specified for USB full speed ($\pm$ 0.25%), but it seems to work in practice n=1 ¯\\\_(ツ)\_/¯
- The vendor's ISP ROM bootloader also does this
- Should work across most of the CH32V2xx and CH32V3xx family with appropriate changes to hardcoded constants. - Should work across most of the CH32V2xx and CH32V3xx family with appropriate changes to hardcoded constants.
- Allows both download to flash and to SRAM with the "not main flash" flag (this is how the RP2040 bootrom works) - Allows both download to flash and to SRAM with the "not main flash" flag (this is how the RP2040 bootrom works)
- Flash download address must be 08xxxxxx (i.e. not starting at 0) - Flash download address must be 08xxxxxx (i.e. not starting at 0)