bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-11-11 14:32:11 +08:00
parent c4c38f507e
commit 961943f623
452 changed files with 9316 additions and 862 deletions
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EVT/EXAM/RCC/Get_CLK/User/ch32v20x_it.c
+1
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@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/RCC/Get_CLK/User/system_ch32v20x.c
+2 -2
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@@ -114,8 +114,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/RCC/HSE_CLK/User/ch32v20x_it.c
+1
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@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/RCC/HSE_CLK/User/main.c
+2 -2
View File
@@ -14,8 +14,8 @@
*@Note
*HSE frequency check routine:
*Checking the frequency value of HSE by using of HSI.
* When HSE is 3 ~ 25M,the HSE clock is effective ,When CH32F20x_D8 and CH32F20x_D6 used.
* When HSE is 32M,the HSE clock is effective ,When CH32F20x_D8C and CH32F20x_D8W used.
* When HSE is 3 ~ 25M,the HSE clock is effective ,When CH32V20x_D6 used.
* When HSE is 32M,the HSE clock is effective ,When CH32V20x_D8 and CH32V20x_D8W used.
*HSE value -the frequency of HSE
*MCO(PA8) - outputs the HSE clock
*
EVT/EXAM/RCC/HSE_CLK/User/system_ch32v20x.c
+12 -5
View File
@@ -6,9 +6,11 @@
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x.h"
/*
@@ -75,14 +77,19 @@ void SystemCoreClockUpdate(void) {
if (pllsource == 0x00) {
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
} else {
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t) RESET) {
}
else
{
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t) RESET)
{
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = ((HSE_VALUE >> 2) >> 1) * pllmull;
#else
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
#endif
} else {
}
else
{
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = (HSE_VALUE >> 2) * pllmull;
#else
EVT/EXAM/RCC/HSI_Calibration/User/ch32v20x_it.c
+1
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@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/RCC/HSI_Calibration/User/system_ch32v20x.c
+2 -2
View File
@@ -114,8 +114,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/RCC/HSI_PLL_Source/User/ch32v20x_it.c
+1
View File
@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/RCC/HSI_PLL_Source/User/main.c
+1 -7
View File
@@ -2,7 +2,7 @@
* File Name : main.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/06/26
* Description : Main program body.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -22,12 +22,6 @@
*/
#include "debug.h"
#define HSI 0 //HSI
#define HSI_1_2 1 //HSI/2
#define PLL_Source HSI
//#define PLL_Source HSI_1_2
/*********************************************************************
* @fn main
*
EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.c
+3 -3
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@@ -2,7 +2,7 @@
* File Name : system_ch32v20x.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/06/26
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 8Mhz (other CH32V203x)
@@ -102,8 +102,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
EVT/EXAM/RCC/HSI_PLL_Source/User/system_ch32v20x.h
+7 -1
View File
@@ -2,7 +2,7 @@
* File Name : system_ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/06/26
* Description : CH32V20x Device Peripheral Access Layer System Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -16,6 +16,12 @@
extern "C" {
#endif
#define HSI 0 //HSI
#define HSI_1_2 1 //HSI/2
//#define PLL_Source HSI
#define PLL_Source HSI_1_2
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */
EVT/EXAM/RCC/MCO/User/ch32v20x_it.c
+1
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@@ -37,6 +37,7 @@ void NMI_Handler(void)
*/
void HardFault_Handler(void)
{
NVIC_SystemReset();
while (1)
{
}
EVT/EXAM/RCC/MCO/User/system_ch32v20x.c
+2 -2
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@@ -159,8 +159,8 @@ void SystemCoreClockUpdate (void)
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}