bstanwell/ch32v20x-examples
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V1.9

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This commit is contained in:
qiyongshuang
2023-12-01 10:33:09 +08:00
parent de6d68c654
commit ec059e0b18
395 changed files with 37947 additions and 28760 deletions
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EVT/EXAM/ETH/MAC_RAW/.cproject
+1 -1
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@@ -235,5 +235,5 @@
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="refreshScope"/>
</cproject>
EVT/EXAM/ETH/MAC_RAW/ETH_Driver/eth_driver.c
+2
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@@ -460,6 +460,8 @@ void ETH_Configuration( uint8_t *macAddr )
R8_ETH_MACON2 |= RB_ETH_MACON2_TXCRCEN; //Hardware padded CRC
R8_ETH_MACON2 &= ~RB_ETH_MACON2_HFRMEN; //Jumbo frames are not received
R16_ETH_MAMXFL = ETH_MAX_PACKET_SIZE;
R8_ETH_ECON2 &= ~(0x07 << 1);
R8_ETH_ECON2 |= 5 << 1;
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
}
EVT/EXAM/ETH/MAC_RAW/User/system_ch32v20x.c
+2 -5
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@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
*/
static void SetSysClock(void)
{
//GPIO_IPD_Unused();
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_48MHz_HSE
@@ -281,7 +282,7 @@ static void SetSysClockToHSE(void)
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
/* Select HSE as system clock source
/* Select HSE as system clock source
* CH32V20x_D6 (HSE=8MHZ)
* CH32V20x_D8 (HSE=32MHZ)
* CH32V20x_D8W (HSE=32MHZ)
@@ -413,7 +414,6 @@ static void SetSysClockTo56_HSE(void)
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
@@ -486,7 +486,6 @@ static void SetSysClockTo72_HSE(void)
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
@@ -560,7 +559,6 @@ static void SetSysClockTo96_HSE(void)
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
@@ -711,7 +709,6 @@ static void SetSysClockTo144_HSE(void)
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)