V1.9
This commit is contained in:
qiyongshuang
@@ -1,8 +1,8 @@
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;/********************************** (C) COPYRIGHT *******************************
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;* File Name : startup_ch32v20x_D6.s
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;* Author : WCH
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;* Version : V1.0.0
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;* Date : 2021/06/06
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;* Version : V1.0.1
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;* Date : 2023/11/11
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;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K6-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
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;* vector table for eclipse toolchain.
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;*********************************************************************************
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@@ -16,19 +16,7 @@
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.align 1
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_start:
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j handle_reset
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00000013
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.word 0x00100073
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.section .vector,"ax",@progbits
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.align 1
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_vector_base:
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@@ -99,7 +87,6 @@ _vector_base:
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.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
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.option rvc;
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.section .text.vector_handler, "ax", @progbits
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.weak NMI_Handler /* NMI */
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.weak HardFault_Handler /* Hard Fault */
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@@ -156,60 +143,62 @@ _vector_base:
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.weak UART4_IRQHandler /* UART4 */
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.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
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NMI_Handler: 1: j 1b
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HardFault_Handler: 1: j 1b
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Ecall_M_Mode_Handler: 1: j 1b
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Ecall_U_Mode_Handler: 1: j 1b
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Break_Point_Handler: 1: j 1b
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SysTick_Handler: 1: j 1b
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SW_Handler: 1: j 1b
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WWDG_IRQHandler: 1: j 1b
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PVD_IRQHandler: 1: j 1b
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TAMPER_IRQHandler: 1: j 1b
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RTC_IRQHandler: 1: j 1b
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FLASH_IRQHandler: 1: j 1b
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RCC_IRQHandler: 1: j 1b
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EXTI0_IRQHandler: 1: j 1b
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EXTI1_IRQHandler: 1: j 1b
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EXTI2_IRQHandler: 1: j 1b
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EXTI3_IRQHandler: 1: j 1b
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EXTI4_IRQHandler: 1: j 1b
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DMA1_Channel1_IRQHandler: 1: j 1b
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DMA1_Channel2_IRQHandler: 1: j 1b
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DMA1_Channel3_IRQHandler: 1: j 1b
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DMA1_Channel4_IRQHandler: 1: j 1b
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DMA1_Channel5_IRQHandler: 1: j 1b
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DMA1_Channel6_IRQHandler: 1: j 1b
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DMA1_Channel7_IRQHandler: 1: j 1b
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ADC1_2_IRQHandler: 1: j 1b
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USB_HP_CAN1_TX_IRQHandler: 1: j 1b
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USB_LP_CAN1_RX0_IRQHandler: 1: j 1b
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CAN1_RX1_IRQHandler: 1: j 1b
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CAN1_SCE_IRQHandler: 1: j 1b
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EXTI9_5_IRQHandler: 1: j 1b
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TIM1_BRK_IRQHandler: 1: j 1b
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TIM1_UP_IRQHandler: 1: j 1b
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TIM1_TRG_COM_IRQHandler: 1: j 1b
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TIM1_CC_IRQHandler: 1: j 1b
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TIM2_IRQHandler: 1: j 1b
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TIM3_IRQHandler: 1: j 1b
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TIM4_IRQHandler: 1: j 1b
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I2C1_EV_IRQHandler: 1: j 1b
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I2C1_ER_IRQHandler: 1: j 1b
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I2C2_EV_IRQHandler: 1: j 1b
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I2C2_ER_IRQHandler: 1: j 1b
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SPI1_IRQHandler: 1: j 1b
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SPI2_IRQHandler: 1: j 1b
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USART1_IRQHandler: 1: j 1b
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USART2_IRQHandler: 1: j 1b
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USART3_IRQHandler: 1: j 1b
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EXTI15_10_IRQHandler: 1: j 1b
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RTCAlarm_IRQHandler: 1: j 1b
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USBWakeUp_IRQHandler: 1: j 1b
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USBHD_IRQHandler: 1: j 1b
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USBHDWakeUp_IRQHandler: 1: j 1b
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UART4_IRQHandler: 1: j 1b
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DMA1_Channel8_IRQHandler: 1: j 1b
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NMI_Handler:
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HardFault_Handler:
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Ecall_M_Mode_Handler:
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Ecall_U_Mode_Handler:
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Break_Point_Handler:
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SysTick_Handler:
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SW_Handler:
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WWDG_IRQHandler:
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PVD_IRQHandler:
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TAMPER_IRQHandler:
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RTC_IRQHandler:
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FLASH_IRQHandler:
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RCC_IRQHandler:
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EXTI0_IRQHandler:
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EXTI1_IRQHandler:
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EXTI2_IRQHandler:
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EXTI3_IRQHandler:
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EXTI4_IRQHandler:
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DMA1_Channel1_IRQHandler:
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DMA1_Channel2_IRQHandler:
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DMA1_Channel3_IRQHandler:
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DMA1_Channel4_IRQHandler:
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DMA1_Channel5_IRQHandler:
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DMA1_Channel6_IRQHandler:
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DMA1_Channel7_IRQHandler:
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ADC1_2_IRQHandler:
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USB_HP_CAN1_TX_IRQHandler:
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USB_LP_CAN1_RX0_IRQHandler:
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CAN1_RX1_IRQHandler:
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CAN1_SCE_IRQHandler:
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EXTI9_5_IRQHandler:
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TIM1_BRK_IRQHandler:
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TIM1_UP_IRQHandler:
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TIM1_TRG_COM_IRQHandler:
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TIM1_CC_IRQHandler:
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TIM2_IRQHandler:
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TIM3_IRQHandler:
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TIM4_IRQHandler:
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I2C1_EV_IRQHandler:
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I2C1_ER_IRQHandler:
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I2C2_EV_IRQHandler:
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I2C2_ER_IRQHandler:
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SPI1_IRQHandler:
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SPI2_IRQHandler:
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USART1_IRQHandler:
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USART2_IRQHandler:
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USART3_IRQHandler:
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EXTI15_10_IRQHandler:
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RTCAlarm_IRQHandler:
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USBWakeUp_IRQHandler:
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USBHD_IRQHandler:
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USBHDWakeUp_IRQHandler:
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UART4_IRQHandler:
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DMA1_Channel8_IRQHandler:
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1:
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j 1b
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.section .text.handle_reset,"ax",@progbits
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.weak handle_reset
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@@ -222,7 +211,7 @@ handle_reset:
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1:
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la sp, _eusrstack
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2:
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/* Load data section from flash to RAM */
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/* Load data section from flash to RAM */
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la a0, _data_lma
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la a1, _data_vma
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la a2, _edata
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@@ -234,7 +223,7 @@ handle_reset:
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Clear bss section */
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/* Clear bss section */
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, 2f
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@@ -243,17 +232,16 @@ handle_reset:
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* Configure pipelining and instruction prediction */
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li t0, 0x1f
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csrw 0xbc0, t0
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/* Enable nested */
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/* Enable interrupt nesting and hardware stack */
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li t0, 0x2
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csrw 0x804, t0
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/* Enable interrupt */
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li t0, 0x1800
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csrs mstatus, t0
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/* Enable global interrupt and configure privileged mode */
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li t0, 0x1800
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csrw mstatus, t0
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/* Configure the interrupt vector table recognition mode and entry address mode */
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la t0, _vector_base
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ori t0, t0, 3
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csrw mtvec, t0
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