V1.9
This commit is contained in:
qiyongshuang
@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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@@ -205,6 +205,7 @@ void SystemCoreClockUpdate (void)
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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@@ -0,0 +1,144 @@
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<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
</tool>
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
|
||||
<entry excluding="startup_ch32v20x_D8.S|startup_ch32v20x_D8W.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
</cproject>
|
||||
@@ -0,0 +1,61 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<projectDescription>
|
||||
<name>SPI_LCD</name>
|
||||
<comment/>
|
||||
<projects/>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
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||||
<arguments/>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
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||||
<arguments/>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>1595986042669</id>
|
||||
<name/>
|
||||
<type>22</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
</filteredResources>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>Core</name>
|
||||
<type>2</type>
|
||||
<location>PARENT-2-PROJECT_LOC/SRC/Core</location>
|
||||
</link>
|
||||
<link>
|
||||
<name>Debug</name>
|
||||
<type>2</type>
|
||||
<location>PARENT-2-PROJECT_LOC/SRC/Debug</location>
|
||||
</link>
|
||||
<link>
|
||||
<name>Ld</name>
|
||||
<type>2</type>
|
||||
<location>PARENT-2-PROJECT_LOC/SRC/Ld</location>
|
||||
</link>
|
||||
<link>
|
||||
<name>Peripheral</name>
|
||||
<type>2</type>
|
||||
<location>PARENT-2-PROJECT_LOC/SRC/Peripheral</location>
|
||||
</link>
|
||||
<link>
|
||||
<name>Startup</name>
|
||||
<type>2</type>
|
||||
<location>PARENT-2-PROJECT_LOC/SRC/Startup</location>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,17 @@
|
||||
Mcu Type=CH32V20x
|
||||
Address=0x08000000
|
||||
Target Path=obj\SPI_LCD.hex
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=true
|
||||
Reset=true
|
||||
|
||||
Vendor=WCH
|
||||
Link=WCH-Link
|
||||
Toolchain=RISC-V
|
||||
Series=CH32V203
|
||||
Description=ROM(byte): 64K, SRAM(byte): 20K, CHIP PINS: 32, GPIO PORTS: 27.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||
|
||||
PeripheralVersion=1.0
|
||||
MCU=CH32V203RBT6
|
||||
CLKSpeed=1
|
||||
@@ -0,0 +1,51 @@
|
||||
/*********************************************************************
|
||||
* File Name : config.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for Config.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CONFIG_H__
|
||||
#define __CONFIG_H__
|
||||
|
||||
/* LCD Screen Definition */
|
||||
#define USE_HORIZONTAL 2
|
||||
#define LCD_W (240u)
|
||||
#define LCD_H (320u)
|
||||
|
||||
/* Buffer Definition */
|
||||
#define COLOR_BYTE (2u)
|
||||
#define FILL_BUFFER_COUNT (256u * 1u)
|
||||
#define FILL_BUFFER_SIZE (FILL_BUFFER_COUNT * COLOR_BYTE)
|
||||
|
||||
/* SPI Flash Speed Definition */
|
||||
#define SPI_NORMAL_MODE 1
|
||||
#define SPI_FAST_MODE 2
|
||||
#define SPI_SPEED_MODE SPI_NORMAL_MODE
|
||||
|
||||
/* SPI FLASH and LCD_SCREEN GPIO Definition */
|
||||
#define FLASH_CS_PORT GPIOA
|
||||
#define FLASH_CS_RCC RCC_APB2Periph_GPIOA
|
||||
#define FLASH_CS_PIN (GPIO_Pin_2)
|
||||
|
||||
#define LCD_LED_RCC RCC_APB2Periph_GPIOB
|
||||
#define LCD_LED_PORT GPIOB
|
||||
#define LCD_LED_PIN (GPIO_Pin_9)
|
||||
|
||||
#define LCD_DC_RCC RCC_APB2Periph_GPIOB
|
||||
#define LCD_DC_PORT GPIOB
|
||||
#define LCD_DC_PIN (GPIO_Pin_10)
|
||||
|
||||
#define LCD_RST_RCC RCC_APB2Periph_GPIOB
|
||||
#define LCD_RST_PORT GPIOB
|
||||
#define LCD_RST_PIN (GPIO_Pin_11)
|
||||
|
||||
#define LCD_CS_RCC RCC_APB2Periph_GPIOB
|
||||
#define LCD_CS_PORT GPIOB
|
||||
#define LCD_CS_PIN (GPIO_Pin_12)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,462 @@
|
||||
/*********************************************************************
|
||||
* File Name : flash.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for spi flash.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "flash.h"
|
||||
#include "spi.h"
|
||||
|
||||
static uint8_t FLASH_readWrite(uint8_t TxData)
|
||||
{
|
||||
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET)
|
||||
;
|
||||
SPI_I2S_SendData(SPI1, TxData);
|
||||
|
||||
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET)
|
||||
;
|
||||
|
||||
return SPI_I2S_ReceiveData(SPI1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn cs_pin_init
|
||||
*
|
||||
* @brief gpio cs pin init
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void cs_pin_init()
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
RCC_APB2PeriphClockCmd(FLASH_CS_RCC, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = FLASH_CS_PIN;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(FLASH_CS_PORT, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_FLASH_Init
|
||||
*
|
||||
* @brief SPI FLASH Init
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_FLASH_Init(void)
|
||||
{
|
||||
SPI1_Init();
|
||||
SPI1_Read_DMA_Init();
|
||||
cs_pin_init();
|
||||
FLASH_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_ReadSR
|
||||
*
|
||||
* @brief Read W25Qxx status register.
|
||||
* ！！BIT7 6 5 4 3 2 1 0
|
||||
* ！！SPR RV TB BP2 BP1 BP0 WEL BUSY
|
||||
*
|
||||
* @return byte - status register value.
|
||||
*/
|
||||
uint8_t SPI_Flash_ReadSR(void)
|
||||
{
|
||||
uint8_t byte = 0;
|
||||
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_ReadStatusReg);
|
||||
byte = FLASH_readWrite(0Xff);
|
||||
FLASH_CS_SET;
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_FLASH_Write_SR
|
||||
*
|
||||
* @brief Write W25Qxx status register.
|
||||
*
|
||||
* @param sr - status register value.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_FLASH_Write_SR(uint8_t sr)
|
||||
{
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_WriteStatusReg);
|
||||
FLASH_readWrite(sr);
|
||||
FLASH_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Wait_Busy
|
||||
*
|
||||
* @brief Wait flash free.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Wait_Busy(void)
|
||||
{
|
||||
while ((SPI_Flash_ReadSR() & 0x01) == 0x01)
|
||||
;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_FLASH_Write_Enable
|
||||
*
|
||||
* @brief Enable flash write.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_FLASH_Write_Enable(void)
|
||||
{
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_WriteEnable);
|
||||
FLASH_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_FLASH_Write_Disable
|
||||
*
|
||||
* @brief Disable flash write.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_FLASH_Write_Disable(void)
|
||||
{
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_WriteDisable);
|
||||
FLASH_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_ReadID
|
||||
*
|
||||
* @brief Read flash ID.
|
||||
*
|
||||
* @return Temp - FLASH ID.
|
||||
*/
|
||||
uint16_t SPI_Flash_ReadID(void)
|
||||
{
|
||||
uint16_t Temp = 0;
|
||||
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_ManufactDeviceID);
|
||||
FLASH_readWrite(0x00);
|
||||
FLASH_readWrite(0x00);
|
||||
FLASH_readWrite(0x00);
|
||||
Temp |= FLASH_readWrite(0xFF) << 8;
|
||||
Temp |= FLASH_readWrite(0xFF);
|
||||
FLASH_CS_SET;
|
||||
|
||||
return Temp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_ReadJedecDeviceID
|
||||
*
|
||||
* @brief Read JedecDevice ID.
|
||||
*
|
||||
* @return JedecDevice ID.
|
||||
*/
|
||||
uint32_t SPI_Flash_ReadJedecDeviceID(void)
|
||||
{
|
||||
uint32_t Temp = 0;
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_JedecDeviceID);
|
||||
Temp |= FLASH_readWrite(0xFF) << 16;
|
||||
Temp |= FLASH_readWrite(0xFF) << 8;
|
||||
Temp |= FLASH_readWrite(0xFF);
|
||||
FLASH_CS_SET;
|
||||
return Temp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Erase_Sector
|
||||
*
|
||||
* @brief Erase one sector(4Kbyte).
|
||||
*
|
||||
* @param Dst_Addr - 0 ！！ 2047
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Erase_Sector(uint32_t Dst_Addr)
|
||||
{
|
||||
Dst_Addr *= 4096;
|
||||
SPI_FLASH_Write_Enable();
|
||||
SPI_Flash_Wait_Busy();
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_SectorErase);
|
||||
FLASH_readWrite((uint8_t)((Dst_Addr) >> 16));
|
||||
FLASH_readWrite((uint8_t)((Dst_Addr) >> 8));
|
||||
FLASH_readWrite((uint8_t)Dst_Addr);
|
||||
FLASH_CS_SET;
|
||||
SPI_Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Read
|
||||
*
|
||||
* @brief Read data from flash.
|
||||
*
|
||||
* @param pBuffer -
|
||||
* ReadAddr -Initial address(24bit).
|
||||
* size - Data length.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Read(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t size)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_ReadData);
|
||||
FLASH_readWrite((uint8_t)((ReadAddr) >> 16));
|
||||
FLASH_readWrite((uint8_t)((ReadAddr) >> 8));
|
||||
FLASH_readWrite((uint8_t)ReadAddr);
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
pBuffer[i] = FLASH_readWrite(0XFF);
|
||||
}
|
||||
|
||||
FLASH_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Write_Page
|
||||
*
|
||||
* @brief Write data by one page.
|
||||
*
|
||||
* @param pBuffer -
|
||||
* WriteAddr - Initial address(24bit).
|
||||
* size - Data length.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Write_Page(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
SPI_FLASH_Write_Enable();
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_PageProgram);
|
||||
FLASH_readWrite((uint8_t)((WriteAddr) >> 16));
|
||||
FLASH_readWrite((uint8_t)((WriteAddr) >> 8));
|
||||
FLASH_readWrite((uint8_t)WriteAddr);
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
FLASH_readWrite(pBuffer[i]);
|
||||
}
|
||||
|
||||
FLASH_CS_SET;
|
||||
SPI_Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Write_NoCheck
|
||||
*
|
||||
* @brief Write data to flash.(need Erase)
|
||||
* All data in address rang is 0xFF.
|
||||
*
|
||||
* @param pBuffer -
|
||||
* WriteAddr - Initial address(24bit).
|
||||
* size - Data length.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Write_NoCheck(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size)
|
||||
{
|
||||
uint16_t pageremain;
|
||||
|
||||
pageremain = 256 - WriteAddr % 256;
|
||||
|
||||
if (size <= pageremain)
|
||||
pageremain = size;
|
||||
|
||||
while (1)
|
||||
{
|
||||
SPI_Flash_Write_Page(pBuffer, WriteAddr, pageremain);
|
||||
|
||||
if (size == pageremain)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
pBuffer += pageremain;
|
||||
WriteAddr += pageremain;
|
||||
size -= pageremain;
|
||||
|
||||
if (size > 256)
|
||||
pageremain = 256;
|
||||
else
|
||||
pageremain = size;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t W25QXX_BUFFER[4096];
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Write
|
||||
*
|
||||
* @brief Write data to flash.(no need Erase)
|
||||
*
|
||||
* @param pBuffer -
|
||||
* WriteAddr - Initial address(24bit).
|
||||
* size - Data length.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Write(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size)
|
||||
{
|
||||
uint32_t secpos;
|
||||
uint16_t secoff;
|
||||
uint16_t secremain;
|
||||
uint16_t i;
|
||||
|
||||
secpos = WriteAddr / 4096;
|
||||
secoff = WriteAddr % 4096;
|
||||
secremain = 4096 - secoff;
|
||||
|
||||
if (size <= secremain)
|
||||
secremain = size;
|
||||
|
||||
while (1)
|
||||
{
|
||||
SPI_Flash_Read(W25QXX_BUFFER, secpos * 4096, 4096);
|
||||
|
||||
for (i = 0; i < secremain; i++)
|
||||
{
|
||||
if (W25QXX_BUFFER[secoff + i] != 0XFF)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i < secremain)
|
||||
{
|
||||
SPI_Flash_Erase_Sector(secpos);
|
||||
|
||||
for (i = 0; i < secremain; i++)
|
||||
{
|
||||
W25QXX_BUFFER[i + secoff] = pBuffer[i];
|
||||
}
|
||||
|
||||
SPI_Flash_Write_NoCheck(W25QXX_BUFFER, secpos * 4096, 4096);
|
||||
}
|
||||
else
|
||||
{
|
||||
SPI_Flash_Write_NoCheck(pBuffer, WriteAddr, secremain);
|
||||
}
|
||||
|
||||
if (size == secremain)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
secpos++;
|
||||
secoff = 0;
|
||||
|
||||
pBuffer += secremain;
|
||||
WriteAddr += secremain;
|
||||
size -= secremain;
|
||||
|
||||
if (size > 4096)
|
||||
{
|
||||
secremain = 4096;
|
||||
}
|
||||
else
|
||||
{
|
||||
secremain = size;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Erase_Chip
|
||||
*
|
||||
* @brief Erase all FLASH pages.
|
||||
*
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Erase_Chip(void)
|
||||
{
|
||||
SPI_FLASH_Write_Enable();
|
||||
SPI_Flash_Wait_Busy();
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_ChipErase);
|
||||
FLASH_CS_SET;
|
||||
SPI_Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_PowerDown
|
||||
*
|
||||
* @brief Enter power down mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_PowerDown(void)
|
||||
{
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_PowerDown);
|
||||
FLASH_CS_SET;
|
||||
Delay_Us(3);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_WAKEUP
|
||||
*
|
||||
* @brief Power down wake up.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_WAKEUP(void)
|
||||
{
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_ReleasePowerDown);
|
||||
FLASH_CS_SET;
|
||||
Delay_Us(3);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Read_dma_start
|
||||
*
|
||||
* @brief enable spi dma and set read address
|
||||
*
|
||||
* @param ReadAddr - the address in spi flash
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Read_dma_start(uint32_t ReadAddr)
|
||||
{
|
||||
FLASH_CS_CLR;
|
||||
FLASH_readWrite(W25X_FastReadData);
|
||||
FLASH_readWrite((uint8_t)((ReadAddr) >> 16));
|
||||
FLASH_readWrite((uint8_t)((ReadAddr) >> 8));
|
||||
FLASH_readWrite((uint8_t)ReadAddr);
|
||||
FLASH_readWrite(0xFF);
|
||||
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Flash_Read_dma_end
|
||||
*
|
||||
* @brief disable spi dma
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Flash_Read_dma_end(void)
|
||||
{
|
||||
FLASH_CS_SET;
|
||||
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, DISABLE);
|
||||
}
|
||||
@@ -0,0 +1,57 @@
|
||||
/*********************************************************************
|
||||
* File Name : flash.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for spi flash.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SPI_FLASH_H
|
||||
#define __SPI_FLASH_H
|
||||
#include "debug.h"
|
||||
#include "spi.h"
|
||||
#include "config.h"
|
||||
|
||||
#define W25X_WriteEnable 0x06
|
||||
#define W25X_WriteDisable 0x04
|
||||
#define W25X_ReadStatusReg 0x05
|
||||
#define W25X_WriteStatusReg 0x01
|
||||
#define W25X_ReadData 0x03
|
||||
#define W25X_FastReadData 0x0B
|
||||
#define W25X_FastReadDual 0x3B
|
||||
#define W25X_PageProgram 0x02
|
||||
#define W25X_BlockErase 0xD8
|
||||
#define W25X_SectorErase 0x20
|
||||
#define W25X_ChipErase 0xC7
|
||||
#define W25X_PowerDown 0xB9
|
||||
#define W25X_ReleasePowerDown 0xAB
|
||||
#define W25X_DeviceID 0xAB
|
||||
#define W25X_ManufactDeviceID 0x90
|
||||
#define W25X_JedecDeviceID 0x9F
|
||||
|
||||
#define FLASH_CS_SET (FLASH_CS_PORT->BSHR = FLASH_CS_PIN)
|
||||
#define FLASH_CS_CLR (FLASH_CS_PORT->BCR = FLASH_CS_PIN)
|
||||
|
||||
void SPI_FLASH_Init(void);
|
||||
uint8_t SPI_Flash_ReadSR(void);
|
||||
void SPI_FLASH_Write_SR(uint8_t sr);
|
||||
void SPI_Flash_Wait_Busy(void);
|
||||
void SPI_FLASH_Write_Enable(void);
|
||||
void SPI_FLASH_Write_Disable(void);
|
||||
uint16_t SPI_Flash_ReadID(void);
|
||||
uint32_t SPI_Flash_ReadJedecDeviceID(void);
|
||||
void SPI_Flash_Erase_Sector(uint32_t Dst_Addr);
|
||||
void SPI_Flash_Read(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t size);
|
||||
void SPI_Flash_Write_Page(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
|
||||
void SPI_Flash_Write_NoCheck(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
|
||||
void SPI_Flash_Write(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
|
||||
void SPI_Flash_Erase_Chip(void);
|
||||
void SPI_Flash_PowerDown(void);
|
||||
void SPI_Flash_WAKEUP(void);
|
||||
void SPI_Flash_Read_dma_start(uint32_t ReadAddr);
|
||||
void SPI_Flash_Read_dma_end(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,407 @@
|
||||
/*********************************************************************
|
||||
* File Name : lcd.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for lcd screen.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "lcd.h"
|
||||
#include "debug.h"
|
||||
|
||||
static uint16_t width;
|
||||
static uint16_t height;
|
||||
|
||||
#define LCD_SOFT_RESET (0x01)
|
||||
#define LCD_READ_ID (0x04)
|
||||
#define LCD_READ_DISPLAY_STATUS (0x09)
|
||||
#define LCD_ON (0x28)
|
||||
#define LCD_OFF (0x29)
|
||||
|
||||
#define LCD_SET_X (0x2a)
|
||||
#define LCD_SET_Y (0x2B)
|
||||
#define LCD_MEM_WRITE (0x2C)
|
||||
#define LCD_MEM_READ (0x2e)
|
||||
|
||||
static uint16_t color_buffer[2][FILL_BUFFER_COUNT] = {0};
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_WR_REG
|
||||
*
|
||||
* @brief Write an 8-bit command to the LCD screen
|
||||
*
|
||||
* @param data - Command value to be written
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void LCD_WR_REG(uint8_t data)
|
||||
{
|
||||
LCD_CS_CLR;
|
||||
LCD_DC_CLR;
|
||||
SPI2_Write(data);
|
||||
LCD_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_WR_DATA
|
||||
*
|
||||
* @brief Write an 8-bit data to the LCD screen
|
||||
*
|
||||
* @param data - the data to write
|
||||
*
|
||||
*/
|
||||
static void LCD_WR_DATA(uint8_t data)
|
||||
{
|
||||
LCD_CS_CLR;
|
||||
LCD_DC_SET;
|
||||
SPI2_Write(data);
|
||||
LCD_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_WriteReg
|
||||
*
|
||||
* @brief write a data to the register
|
||||
*
|
||||
* @param LCD_Reg - register address
|
||||
* LCD_RegValue - the data to write
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void LCD_WriteReg(uint8_t LCD_Reg, uint8_t LCD_RegValue)
|
||||
{
|
||||
LCD_WR_REG(LCD_Reg);
|
||||
LCD_WR_DATA(LCD_RegValue);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Lcd_WriteData_16Bit
|
||||
*
|
||||
* @brief write two bytes to the lcd screen
|
||||
*
|
||||
* @param Data - the data to write
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void Lcd_WriteData_16Bit(uint16_t Data)
|
||||
{
|
||||
LCD_CS_CLR;
|
||||
LCD_DC_SET;
|
||||
SPI2_Write(Data >> 8);
|
||||
SPI2_Write(Data);
|
||||
LCD_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_GPIOInit
|
||||
*
|
||||
* @brief Configuring the control gpio for the lcd screen
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_GPIOInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
RCC_APB2PeriphClockCmd(LCD_LED_RCC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(LCD_DC_RCC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(LCD_RST_RCC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(LCD_CS_RCC, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = LCD_LED_PIN;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(LCD_LED_PORT, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = LCD_DC_PIN;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(LCD_DC_PORT, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = LCD_RST_PIN;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(LCD_RST_PORT, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = LCD_CS_PIN;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_Init(LCD_CS_PORT, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_RESET
|
||||
*
|
||||
* @brief reset the lcd screen by the rst pin
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_RESET(void)
|
||||
{
|
||||
LCD_RST_CLR;
|
||||
Delay_Ms(100);
|
||||
LCD_RST_SET;
|
||||
Delay_Ms(50);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_Init
|
||||
*
|
||||
* @brief Initialization LCD screen
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_Init(void)
|
||||
{
|
||||
SPI2_Init();
|
||||
SPI2_DMA_Init();
|
||||
LCD_GPIOInit();
|
||||
LCD_RESET();
|
||||
LCD_LED_SET;
|
||||
|
||||
LCD_WR_REG(0xCF);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0xC9); //C1
|
||||
LCD_WR_DATA(0X30);
|
||||
LCD_WR_REG(0xED);
|
||||
LCD_WR_DATA(0x64);
|
||||
LCD_WR_DATA(0x03);
|
||||
LCD_WR_DATA(0X12);
|
||||
LCD_WR_DATA(0X81);
|
||||
LCD_WR_REG(0xE8);
|
||||
LCD_WR_DATA(0x85);
|
||||
LCD_WR_DATA(0x10);
|
||||
LCD_WR_DATA(0x7A);
|
||||
LCD_WR_REG(0xCB);
|
||||
LCD_WR_DATA(0x39);
|
||||
LCD_WR_DATA(0x2C);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x34);
|
||||
LCD_WR_DATA(0x02);
|
||||
LCD_WR_REG(0xF7);
|
||||
LCD_WR_DATA(0x20);
|
||||
LCD_WR_REG(0xEA);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_REG(0xC0); //Power control
|
||||
LCD_WR_DATA(0x1B); //VRH[5:0]
|
||||
LCD_WR_REG(0xC1); //Power control
|
||||
LCD_WR_DATA(0x00); //SAP[2:0];BT[3:0] 01
|
||||
LCD_WR_REG(0xC5); //VCM control
|
||||
LCD_WR_DATA(0x30); //3F
|
||||
LCD_WR_DATA(0x30); //3C
|
||||
LCD_WR_REG(0xC7); //VCM control2
|
||||
LCD_WR_DATA(0XB7);
|
||||
LCD_WR_REG(0x36); // Memory Access Control
|
||||
LCD_WR_DATA(0x08);
|
||||
LCD_WR_REG(0x3A);
|
||||
LCD_WR_DATA(0x55);
|
||||
LCD_WR_REG(0xB1);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x1A);
|
||||
LCD_WR_REG(0xB6); // Display Function Control
|
||||
LCD_WR_DATA(0x0A);
|
||||
LCD_WR_DATA(0xA2);
|
||||
LCD_WR_REG(0xF2); // 3Gamma Function Disable
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_REG(0x26); //Gamma curve selected
|
||||
LCD_WR_DATA(0x01);
|
||||
LCD_WR_REG(0xE0); //Set Gamma
|
||||
LCD_WR_DATA(0x0F);
|
||||
LCD_WR_DATA(0x2A);
|
||||
LCD_WR_DATA(0x28);
|
||||
LCD_WR_DATA(0x08);
|
||||
LCD_WR_DATA(0x0E);
|
||||
LCD_WR_DATA(0x08);
|
||||
LCD_WR_DATA(0x54);
|
||||
LCD_WR_DATA(0XA9);
|
||||
LCD_WR_DATA(0x43);
|
||||
LCD_WR_DATA(0x0A);
|
||||
LCD_WR_DATA(0x0F);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_REG(0XE1); //Set Gamma
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x15);
|
||||
LCD_WR_DATA(0x17);
|
||||
LCD_WR_DATA(0x07);
|
||||
LCD_WR_DATA(0x11);
|
||||
LCD_WR_DATA(0x06);
|
||||
LCD_WR_DATA(0x2B);
|
||||
LCD_WR_DATA(0x56);
|
||||
LCD_WR_DATA(0x3C);
|
||||
LCD_WR_DATA(0x05);
|
||||
LCD_WR_DATA(0x10);
|
||||
LCD_WR_DATA(0x0F);
|
||||
LCD_WR_DATA(0x3F);
|
||||
LCD_WR_DATA(0x3F);
|
||||
LCD_WR_DATA(0x0F);
|
||||
LCD_WR_REG(0x2B);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x01);
|
||||
LCD_WR_DATA(0x3f);
|
||||
LCD_WR_REG(0x2A);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0x00);
|
||||
LCD_WR_DATA(0xef);
|
||||
LCD_WR_REG(0x11); //Exit Sleep
|
||||
Delay_Ms(120);
|
||||
LCD_WR_REG(0x29); //display on
|
||||
|
||||
LCD_direction(USE_HORIZONTAL);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_SetWindows
|
||||
*
|
||||
* @brief Setting LCD display window
|
||||
*
|
||||
* @param xStar - the bebinning x coordinate of the LCD display window
|
||||
* yStar - the bebinning y coordinate of the LCD display window
|
||||
* xEnd - the endning x coordinate of the LCD display window
|
||||
* yEnd - the endning y coordinate of the LCD display window
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_SetWindows(uint16_t xStar, uint16_t yStar, uint16_t xEnd, uint16_t yEnd)
|
||||
{
|
||||
LCD_WR_REG(LCD_SET_X);
|
||||
LCD_WR_DATA(xStar >> 8);
|
||||
LCD_WR_DATA(0x00FF & xStar);
|
||||
LCD_WR_DATA(xEnd >> 8);
|
||||
LCD_WR_DATA(0x00FF & xEnd);
|
||||
|
||||
LCD_WR_REG(LCD_SET_Y);
|
||||
LCD_WR_DATA(yStar >> 8);
|
||||
LCD_WR_DATA(0x00FF & yStar);
|
||||
LCD_WR_DATA(yEnd >> 8);
|
||||
LCD_WR_DATA(0x00FF & yEnd);
|
||||
LCD_WR_REG(LCD_MEM_WRITE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_direction
|
||||
*
|
||||
* @brief Setting the display direction of LCD screen
|
||||
*
|
||||
* @param direction - direction:0-0 degree 1-90 degree 2-180 degree 3-270 degree
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_direction(uint8_t direction)
|
||||
{
|
||||
switch (direction)
|
||||
{
|
||||
case 0:
|
||||
width = LCD_W;
|
||||
height = LCD_H;
|
||||
LCD_WriteReg(0x36, (1 << 3) | (0 << 6) | (0 << 7)); //BGR==1,MY==0,MX==0,MV==0
|
||||
break;
|
||||
case 1:
|
||||
width = LCD_H;
|
||||
height = LCD_W;
|
||||
LCD_WriteReg(0x36, (1 << 3) | (0 << 7) | (1 << 6) | (1 << 5)); //BGR==1,MY==1,MX==0,MV==1
|
||||
break;
|
||||
case 2:
|
||||
width = LCD_W;
|
||||
height = LCD_H;
|
||||
LCD_WriteReg(0x36, (1 << 3) | (1 << 6) | (1 << 7)); //BGR==1,MY==0,MX==0,MV==0
|
||||
break;
|
||||
case 3:
|
||||
width = LCD_H;
|
||||
height = LCD_W;
|
||||
LCD_WriteReg(0x36, (1 << 3) | (1 << 7) | (1 << 5)); //BGR==1,MY==1,MX==0,MV==1
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_Clear
|
||||
*
|
||||
* @brief Full screen filled LCD screen
|
||||
*
|
||||
* @param Color - Filled color
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_Clear(uint16_t Color)
|
||||
{
|
||||
unsigned int i, m;
|
||||
LCD_SetWindows(0, 0, width - 1, height - 1);
|
||||
LCD_CS_CLR;
|
||||
LCD_DC_SET;
|
||||
for (i = 0; i < height; i++)
|
||||
{
|
||||
for (m = 0; m < width; m++)
|
||||
{
|
||||
Lcd_WriteData_16Bit(Color);
|
||||
}
|
||||
}
|
||||
LCD_CS_SET;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn LCD_drawImageWithSize
|
||||
*
|
||||
* @brief read image from SPI Flash and display on the LCD screen
|
||||
*
|
||||
* @param x - the x coordinate of the LCD screen
|
||||
* y - the y coordinate of the LCD screen
|
||||
* width - the image width
|
||||
* height - the image height
|
||||
* addr - the image address in SPI flash
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void LCD_drawImageWithSize(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint32_t addr)
|
||||
{
|
||||
uint32_t m = 0;
|
||||
uint16_t x2 = (x + width) - 1;
|
||||
uint16_t y2 = (y + height) - 1;
|
||||
LCD_WR_REG(LCD_SET_X);
|
||||
LCD_WR_DATA(x >> 8);
|
||||
LCD_WR_DATA(0x00FF & x);
|
||||
LCD_WR_DATA(x2 >> 8);
|
||||
LCD_WR_DATA(0x00FF & x2);
|
||||
|
||||
LCD_WR_REG(LCD_SET_Y);
|
||||
LCD_WR_DATA(y >> 8);
|
||||
LCD_WR_DATA(0x00FF & y);
|
||||
LCD_WR_DATA(y2 >> 8);
|
||||
LCD_WR_DATA(0x00FF & y2);
|
||||
|
||||
LCD_WR_REG(LCD_MEM_WRITE);
|
||||
LCD_CS_CLR;
|
||||
LCD_DC_SET;
|
||||
|
||||
uint32_t count = width * height;
|
||||
|
||||
uint32_t fill_count = count / FILL_BUFFER_COUNT;
|
||||
uint32_t else_count = count % FILL_BUFFER_COUNT;
|
||||
SPI_Flash_Read_dma_start(addr);
|
||||
|
||||
SPI1_Read_DMA((uint8_t *)color_buffer[m], FILL_BUFFER_SIZE);
|
||||
|
||||
while (fill_count > 0)
|
||||
{
|
||||
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET)
|
||||
;
|
||||
fill_count--;
|
||||
SPI2_Write_DMA((uint8_t *)color_buffer[m], FILL_BUFFER_SIZE);
|
||||
m = !m;
|
||||
SPI1_Read_DMA((uint8_t *)color_buffer[m], FILL_BUFFER_SIZE);
|
||||
}
|
||||
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET)
|
||||
;
|
||||
SPI2_Write_DMA((uint8_t *)color_buffer[m], else_count * COLOR_BYTE);
|
||||
SPI_Flash_Read_dma_end();
|
||||
}
|
||||
@@ -0,0 +1,57 @@
|
||||
/*********************************************************************
|
||||
* File Name : lcd.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for lcd screen.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __LCD_H
|
||||
#define __LCD_H
|
||||
#include "spi.h"
|
||||
#include "stdio.h"
|
||||
#include "stdlib.h"
|
||||
#include "flash.h"
|
||||
#include "config.h"
|
||||
|
||||
// [15:11] 5bit red
|
||||
// [10:5] 6bit green
|
||||
// [4:0] 5bit blue
|
||||
#define LCD_WHITE 0xFFFF
|
||||
#define LCD_BLACK 0x0000
|
||||
#define LCD_BLUE 0x001F
|
||||
#define LCD_BRED 0XF81F
|
||||
#define LCD_GRED 0XFFE0
|
||||
#define LCD_GBLUE 0X07FF
|
||||
#define LCD_RED 0xF800
|
||||
#define LCD_MAGENTA 0xF81F
|
||||
#define LCD_GREEN 0x07E0
|
||||
#define LCD_CYAN 0x7FFF
|
||||
#define LCD_YELLOW 0xFFE0
|
||||
#define LCD_BROWN 0XBC40
|
||||
#define LCD_BRRED 0XFC07
|
||||
#define LCD_GRAY 0X8430
|
||||
|
||||
#define LCD_LED_SET (LCD_LED_PORT->BSHR = LCD_LED_PIN)
|
||||
#define LCD_CS_SET (LCD_CS_PORT->BSHR = LCD_CS_PIN)
|
||||
#define LCD_DC_SET (LCD_DC_PORT->BSHR = LCD_DC_PIN)
|
||||
#define LCD_RST_SET (LCD_RST_PORT->BSHR = LCD_RST_PIN)
|
||||
|
||||
#define LCD_LED_CLR (LCD_LED_PORT->BCR = LCD_LED_PIN)
|
||||
#define LCD_CS_CLR (LCD_CS_PORT->BCR = LCD_CS_PIN)
|
||||
#define LCD_DC_CLR (LCD_DC_PORT->BCR = LCD_DC_PIN)
|
||||
#define LCD_RST_CLR (LCD_RST_PORT->BCR = LCD_RST_PIN)
|
||||
|
||||
void LCD_Init(void);
|
||||
void LCD_Clear(uint16_t Color);
|
||||
|
||||
void Lcd_WriteData_16Bit(uint16_t Data);
|
||||
void LCD_direction(uint8_t direction);
|
||||
void LCD_SetWindows(uint16_t xStar, uint16_t yStar, uint16_t xEnd, uint16_t yEnd);
|
||||
|
||||
void LCD_drawImageWithSize(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint32_t addr);
|
||||
#endif
|
||||
@@ -0,0 +1,253 @@
|
||||
/*********************************************************************
|
||||
* File Name : spi.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for spi.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "spi.h"
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI1_Init
|
||||
*
|
||||
* @brief Initialize SPI1
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
SPI_InitTypeDef SPI_InitStructure = {0};
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_SPI1, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
|
||||
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
|
||||
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
|
||||
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
|
||||
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
|
||||
#if SPI_SPEED_MODE == SPI_FAST_MODE
|
||||
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
#else
|
||||
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
|
||||
#endif
|
||||
|
||||
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||
SPI_Init(SPI1, &SPI_InitStructure);
|
||||
|
||||
SPI_Cmd(SPI1, ENABLE);
|
||||
|
||||
#if SPI_SPEED_MODE == SPI_FAST_MODE
|
||||
SPI1->HSCR = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI1_Read_DMA_Init
|
||||
*
|
||||
* @brief Initialize DMA for SPI1, In this condition every time send 0XFF to read data
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_Read_DMA_Init()
|
||||
{
|
||||
static uint32_t DummyByte = 0xff;
|
||||
DMA_InitTypeDef DMA_InitStructure = {0};
|
||||
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
|
||||
|
||||
// Tx
|
||||
DMA_DeInit(SPI1_DMA_TX_CH);
|
||||
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DATAR;
|
||||
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&DummyByte;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
|
||||
DMA_InitStructure.DMA_BufferSize = 0;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
|
||||
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
|
||||
DMA_Init(SPI1_DMA_TX_CH, &DMA_InitStructure);
|
||||
|
||||
// Rx
|
||||
DMA_DeInit(SPI1_DMA_RX_CH);
|
||||
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DATAR;
|
||||
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)NULL;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
DMA_InitStructure.DMA_BufferSize = 0;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
|
||||
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
|
||||
DMA_Init(SPI1_DMA_RX_CH, &DMA_InitStructure);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI1_Read_DMA
|
||||
*
|
||||
* @brief read data from SPI1 via DMA
|
||||
*
|
||||
* @param data - the data to recive
|
||||
* len - read length
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_Read_DMA(uint8_t *data, uint16_t len)
|
||||
{
|
||||
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET)
|
||||
;
|
||||
DMA_Cmd(SPI1_DMA_TX_CH, DISABLE);
|
||||
DMA_Cmd(SPI1_DMA_RX_CH, DISABLE);
|
||||
DMA_ClearFlag(DMA1_FLAG_TC3);
|
||||
DMA_ClearFlag(DMA1_FLAG_TC3);
|
||||
SPI1_DMA_TX_CH->CNTR = len;
|
||||
|
||||
SPI1_DMA_RX_CH->MADDR = (uint32_t)data;
|
||||
SPI1_DMA_RX_CH->CNTR = len;
|
||||
|
||||
DMA_Cmd(SPI1_DMA_TX_CH, ENABLE);
|
||||
DMA_Cmd(SPI1_DMA_RX_CH, ENABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI2_Init
|
||||
*
|
||||
* @brief Initialize SPI2
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI2_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
SPI_InitTypeDef SPI_InitStructure = {0};
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
|
||||
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
|
||||
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
|
||||
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
|
||||
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
|
||||
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
|
||||
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||
SPI_Init(SPI2, &SPI_InitStructure);
|
||||
|
||||
SPI_Cmd(SPI2, ENABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI2_DMA_Init
|
||||
*
|
||||
* @brief Initialize DMA for SPI2
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI2_DMA_Init()
|
||||
{
|
||||
DMA_InitTypeDef DMA_InitStructure = {0};
|
||||
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
|
||||
|
||||
DMA_DeInit(SPI2_DMA_TX_CH);
|
||||
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI2->DATAR;
|
||||
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)NULL;
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
|
||||
DMA_InitStructure.DMA_BufferSize = 0;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
|
||||
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
|
||||
DMA_Init(SPI2_DMA_TX_CH, &DMA_InitStructure);
|
||||
|
||||
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI2_Write
|
||||
*
|
||||
* @brief send one byte
|
||||
*
|
||||
* @param data - the data to send
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI2_Write(uint8_t data)
|
||||
{
|
||||
while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET)
|
||||
;
|
||||
SPI_I2S_SendData(SPI2, data);
|
||||
|
||||
while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET)
|
||||
;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI2_Write_DMA
|
||||
*
|
||||
* @brief send a lot of data
|
||||
*
|
||||
* @param data - the data to be send
|
||||
* len - the length of data
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI2_Write_DMA(uint8_t *data, uint16_t len)
|
||||
{
|
||||
while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET)
|
||||
;
|
||||
|
||||
DMA_Cmd(SPI2_DMA_TX_CH, DISABLE);
|
||||
DMA_ClearFlag(SPI2_DMA_TC_FLAG);
|
||||
SPI2_DMA_TX_CH->MADDR = (uint32_t)data;
|
||||
SPI2_DMA_TX_CH->CNTR = len;
|
||||
|
||||
DMA_Cmd(SPI2_DMA_TX_CH, ENABLE);
|
||||
}
|
||||
@@ -0,0 +1,39 @@
|
||||
/*********************************************************************
|
||||
* File Name : spi.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : file for spi.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
#include "debug.h"
|
||||
#include "config.h"
|
||||
|
||||
#define SPI1_DMA_RX_CH DMA1_Channel2
|
||||
#define SPI1_DMA_TX_CH DMA1_Channel3
|
||||
|
||||
#define SPI1_DMA_TC_FLAG DMA1_FLAG_TC3
|
||||
#define SPI1_DMA_RC_FLAG DMA1_FLAG_TC2
|
||||
|
||||
#define SPI2_DMA_RX_CH DMA1_Channel4
|
||||
#define SPI2_DMA_TX_CH DMA1_Channel5
|
||||
|
||||
#define SPI2_DMA_TC_FLAG DMA1_FLAG_TC5
|
||||
#define SPI2_DMA_RC_FLAG DMA1_FLAG_TC4
|
||||
|
||||
void SPI1_Init(void);
|
||||
void SPI1_Read_DMA_Init(void);
|
||||
void SPI1_Read_DMA(uint8_t *data, uint16_t len);
|
||||
|
||||
void SPI2_Init(void);
|
||||
void SPI2_DMA_Init(void);
|
||||
void SPI2_Write(uint8_t data);
|
||||
void SPI2_Write_DMA(uint8_t *data, uint16_t len);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,2 @@
|
||||
�i“CZ ?"Ç�¸rŸ�F<Fy8E9Y‡½„%P a³D¶La† %Ã'y€¡]Ç;’¶ ŸS)1†1+R4><‚.„ÇÅ¿º° ?/£XO©Ä¿ChQN$*¢”»EÅBk‹!2tŒ+buh†nUb]xl‹l|
|
||||
+"Ÿ<“¯AH42}z8p;m€u 1Ž-¦eh»Od¼Âwµª7x{5�CqEx©=;¦¢e¢º»2£Š ‚«* BP Mš"
|
||||
@@ -0,0 +1,42 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_CONF_H
|
||||
#define __CH32V20x_CONF_H
|
||||
|
||||
#include "ch32v20x_adc.h"
|
||||
#include "ch32v20x_bkp.h"
|
||||
#include "ch32v20x_can.h"
|
||||
#include "ch32v20x_crc.h"
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_exti.h"
|
||||
#include "ch32v20x_flash.h"
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_i2c.h"
|
||||
#include "ch32v20x_iwdg.h"
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
#include "ch32v20x_rtc.h"
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_tim.h"
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_it.h"
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_CONF_H */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,40 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_it.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V20x_IT_H
|
||||
#define __CH32V20x_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
|
||||
#endif /* __CH32V20x_IT_H */
|
||||
|
||||
|
||||
@@ -0,0 +1,80 @@
|
||||
/*********************************************************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/8/15
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2023 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
*@Note
|
||||
This example reads image data from SPI flash and displays it on the LCD screen.
|
||||
You should first put your image in SPI flash, the image format is RGB 565 and big-endian byte order
|
||||
Both types of hardware communicate using the SPI interface.
|
||||
You can set the lcd screen size and buffer size in config.h
|
||||
pins:
|
||||
FLASH_CS -- PA2
|
||||
FLASH_DO -- PA6(SPI1_MISO)
|
||||
FLASH_WP -- 3.3V
|
||||
FLASH_DI -- PA7(SPI1_MOSI)
|
||||
FLASH_CLK -- PA5(SPI1_SCK)
|
||||
FLASH_HOLD -- 3.3V
|
||||
|
||||
LCD_LED -- PB9
|
||||
LCD_DC -- PB10
|
||||
LCD_RST -- PB11
|
||||
LCD_CS -- PB12
|
||||
LCD_SCK -- PB13(SPI2_SCK)
|
||||
LCD_MOSI -- PB15(SPI2_MOSI)
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#include "debug.h"
|
||||
#include "string.h"
|
||||
#include "lcd.h"
|
||||
#include "flash.h"
|
||||
#include "config.h"
|
||||
|
||||
/* Global define */
|
||||
|
||||
|
||||
/* Global Variable */
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
uint32_t addr = 0;
|
||||
uint16_t i = 0;
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
Delay_Init();
|
||||
USART_Printf_Init(115200);
|
||||
printf("SystemClk:%d\r\n", SystemCoreClock);
|
||||
SPI_FLASH_Init();
|
||||
LCD_Init();
|
||||
|
||||
while (1)
|
||||
{
|
||||
addr = 0;
|
||||
i = 0;
|
||||
while (i < 11)
|
||||
{
|
||||
i++;
|
||||
LCD_drawImageWithSize(0, 0, LCD_W, LCD_H, addr);
|
||||
addr += (LCD_W * LCD_H * COLOR_BYTE);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,987 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Source File.
|
||||
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
|
||||
* For HSE = 8Mhz (other CH32V203x)
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSE 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
#define SYSCLK_FREQ_144MHz_HSE 144000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
//#define SYSCLK_FREQ_96MHz_HSI 96000000
|
||||
//#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_144MHz_HSI 144000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
static void SetSysClockTo96_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
static void SetSysClockTo144_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
static void SetSysClockTo96_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
static void SetSysClockTo144_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if(pllmull == 17) pllmull = 18;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
|
||||
SystemCoreClock = HSI_VALUE * pllmull;
|
||||
}
|
||||
else{
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
if((RCC->CFGR0 & (3<<22)) == (3<<22))
|
||||
{
|
||||
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
|
||||
#else
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
|
||||
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
//GPIO_IPD_Unused();
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
SetSysClockTo96_HSE();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
SetSysClockTo144_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
SetSysClockTo96_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
SetSysClockTo144_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source
|
||||
* CH32V20x_D6 (HSE=8MHZ)
|
||||
* CH32V20x_D8 (HSE=32MHZ)
|
||||
* CH32V20x_D8W (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
#if defined (CH32V20x_D8W)
|
||||
RCC->CFGR0 |= (uint32_t)(3<<22);
|
||||
/* HCLK = SYSCLK/2 */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
#else
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
#endif
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
|
||||
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
|
||||
*/
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_96MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo96_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo96_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
#elif defined SYSCLK_FREQ_144MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo144_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo144_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,32 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v20x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : CH32V20x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_ch32v20x_H
|
||||
#define __SYSTEM_ch32v20x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V20x_SYSTEM_H */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user