bstanwell/ch32v20x-examples
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This commit is contained in:
qiyongshuang
2024-05-09 16:45:21 +08:00
parent 3ae6808745
commit eec5b06019
25 changed files with 1814 additions and 29 deletions
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EVT/EXAM/SRC/Peripheral/inc/ch32v20x.h
+1 -1
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@@ -39,7 +39,7 @@ extern "C" {
/* CH32V20x Standard Peripheral Library version number */
#define __CH32V20x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x00) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION_SUB (0x01) /* [7:0] sub version */
#define __CH32V20x_STDPERIPH_VERSION ( (__CH32V20x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V20x_STDPERIPH_VERSION_SUB << 0))
EVT/EXAM/SRC/Peripheral/inc/ch32v20x_gpio.h
+2 -2
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Date : 2024/03/02
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*********************************************************************************
@@ -106,7 +106,7 @@ typedef enum
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
to TIM2 Internal Trigger 1 for calibration \
EVT/EXAM/SRC/Peripheral/src/ch32v20x_gpio.c
+30 -11
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@@ -2,7 +2,7 @@
* File Name : ch32v20x_gpio.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/11/23
* Date : 2024/05/06
* Description : This file provides all the GPIO firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@@ -517,9 +517,7 @@ void GPIO_EventOutputCmd(FunctionalState NewState)
* GPIO_Remap_ETH - Ethernet remapping
* GPIO_Remap_CAN2 - CAN2 remapping
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
* GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
* GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
@@ -721,7 +719,10 @@ void GPIO_IPD_Unused(void)
|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1\
|GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_8\
|GPIO_Pin_9|GPIO_Pin_10\
@@ -751,7 +752,10 @@ void GPIO_IPD_Unused(void)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
@@ -780,7 +784,10 @@ void GPIO_IPD_Unused(void)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
@@ -809,7 +816,10 @@ void GPIO_IPD_Unused(void)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
@@ -832,7 +842,10 @@ void GPIO_IPD_Unused(void)
}
case 0x20350500: //CH32V203K6T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
@@ -857,7 +870,10 @@ void GPIO_IPD_Unused(void)
}
case 0x20320500: //CH32V203K8T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
@@ -950,8 +966,11 @@ void GPIO_IPD_Unused(void)
|GPIO_Pin_10|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_9|GPIO_Pin_10\
|GPIO_Pin_11|GPIO_Pin_12\
EVT/EXAM/SRC/Peripheral/src/ch32v20x_iwdg.c
+1 -1
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@@ -92,7 +92,7 @@ void IWDG_ReloadCounter(void)
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
while((RCC->RSTSCKR)|(0x2)!=SET);
while((RCC->RSTSCKR & 0x2)==RESET);
}
/*********************************************************************
EVT/EXAM/SRC/Peripheral/src/ch32v20x_usart.c
+4 -4
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@@ -21,15 +21,15 @@
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
@@ -41,7 +41,7 @@
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */