304 lines
8.8 KiB
C
304 lines
8.8 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : main.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : Main program body.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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/*
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*@Note
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*HSE frequency check routine:
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*Checking the frequency value of HSE by using of HSI.
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* When HSE is 3 ~ 25M,the HSE clock is effective ,When CH32V20x_D6 used.
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* When HSE is 32M,the HSE clock is effective ,When CH32V20x_D8 and CH32V20x_D8W used.
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*HSE value -the frequency of HSE
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*MCO(PA8) - outputs the HSE clock
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*
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*/
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#include "debug.h"
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uint8_t HSEFrequencyMhz;
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uint8_t value;
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#define F1M 1000000
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#define CHECK_ERR_COUNT (8)
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#define RTC_COUNT_DELAY (100)
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#define HSIClock (8000000)
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#define PPL2_ENABLE 1
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#define HSE_ENABLE 0
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#define STclk_div8 0
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#define STclk_div1 1
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#define CHECK_MODE STclk_div8
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//#define CHECK_MODE STclk_div1
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uint8_t value=0;
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/*********************************************************************
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* @fn HSE_FrequencyCheck
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*
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* @brief Checking HSE Frequency Values.
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*
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* @return HSEFrequencyMhz - HSE Frequency
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*/
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uint8_t HSE_FrequencyCheck(void) {
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uint32_t rtc_val;
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uint32_t tick_val;
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uint32_t HSEFrequency, HSEFrequency_x, RTC_DIV_VAL,RTC_CHANGE_TIMEOUT,RTC_COUNT_MAX_TIMEOUT;
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uint8_t count;
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#if defined (CH32V20x_D6)
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if(((*(uint32_t *) 0x40022030) & 0x0F000000) != 0)
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{
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RTC_DIV_VAL=128;
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}
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else {
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RTC_DIV_VAL=512;
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}
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#else
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RTC_DIV_VAL=512;
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#endif
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RTC_CHANGE_TIMEOUT=(HSIClock/F1M)*RTC_DIV_VAL;
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RTC_COUNT_MAX_TIMEOUT=(HSIClock/F1M)*RTC_DIV_VAL*RTC_COUNT_DELAY;
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Delay_Init();
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
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PWR_BackupAccessCmd(ENABLE);
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BKP_DeInit();
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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RCC_RTCCLKConfig(RCC_RTCCLKSource_HSE_Div512);
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#else
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RCC_RTCCLKConfig(RCC_RTCCLKSource_HSE_Div128);
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#endif
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RCC_RTCCLKCmd(ENABLE);
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RTC_WaitForLastTask();
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RTC_WaitForSynchro();
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RTC_WaitForLastTask();
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RTC_EnterConfigMode();
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RTC_SetPrescaler(0);
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RTC_WaitForLastTask();
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RTC_ExitConfigMode();
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while( (RCC->BDCTLR & (1<<15)) != (1<<15) ) {}
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count = CHECK_ERR_COUNT;
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while(1) {
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SysTick->CTLR = 0;
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SysTick->CNT =0;
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#if (CHECK_MODE == STclk_div1)
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SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
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#elif (CHECK_MODE == STclk_div8)
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SysTick->CTLR = (1<<5)|(1<<0);
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#endif
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rtc_val = RTC_GetCounter();
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while( rtc_val == RTC_GetCounter()) {
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if( SysTick->CNT > RTC_CHANGE_TIMEOUT ) {
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return 0;
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}
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}
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SysTick->CTLR = 0;
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SysTick->CNT =0;
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#if (CHECK_MODE == STclk_div1)
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SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
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#elif (CHECK_MODE == STclk_div8)
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SysTick->CTLR = (1<<5)|(1<<0);
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#endif
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rtc_val += (RTC_COUNT_DELAY);
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while( rtc_val >= RTC_GetCounter() ) {
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if( SysTick->CNT > RTC_COUNT_MAX_TIMEOUT ) {
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return 0;
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}
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}
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tick_val = SysTick->CNT;
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SysTick->CTLR = 0;
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#if (CHECK_MODE == STclk_div1)
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HSEFrequency = HSIClock/(tick_val/RTC_DIV_VAL)*RTC_COUNT_DELAY;
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#elif (CHECK_MODE == STclk_div8)
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HSEFrequency = HSIClock/(tick_val/(RTC_DIV_VAL/8))*RTC_COUNT_DELAY;
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#endif
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HSEFrequencyMhz = (HSEFrequency+(F1M/2))/F1M;
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SysTick->CTLR = 0;
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SysTick->CNT =0;
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#if (CHECK_MODE == STclk_div1)
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SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
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#elif (CHECK_MODE == STclk_div8)
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SysTick->CTLR = (1<<5)|(1<<0);
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#endif
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rtc_val = RTC_GetCounter();
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while( rtc_val == RTC_GetCounter() ) {
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if( SysTick->CNT > RTC_CHANGE_TIMEOUT ) {
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return 0;
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}
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}
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SysTick->CTLR = 0;
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SysTick->CNT =0;
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#if (CHECK_MODE == STclk_div1)
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SysTick->CTLR = (1<<5)|(1<<2)|(1<<0);
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#elif (CHECK_MODE == STclk_div8)
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SysTick->CTLR = (1<<5)|(1<<0);
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#endif
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rtc_val += (RTC_COUNT_DELAY);
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while( rtc_val >= RTC_GetCounter() ) {
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if( SysTick->CNT > RTC_COUNT_MAX_TIMEOUT ) {
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return 0;
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}
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}
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tick_val = SysTick->CNT;
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SysTick->CTLR = 0;
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#if (CHECK_MODE == STclk_div1)
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HSEFrequency = HSIClock/(tick_val/RTC_DIV_VAL)*RTC_COUNT_DELAY;
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#elif (CHECK_MODE == STclk_div8)
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HSEFrequency = HSIClock/(tick_val/(RTC_DIV_VAL/8))*RTC_COUNT_DELAY;
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#endif
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HSEFrequency_x = (HSEFrequency+(F1M/2))/F1M;
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if( HSEFrequencyMhz == HSEFrequency_x ) {
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break;
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}
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if( --count == 0 ) {
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HSEFrequencyMhz = 253;
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printf("HSE check error.\n");
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break;
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}
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}
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return HSEFrequencyMhz;
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}
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/*********************************************************************
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* @fn SetSysClockTo72
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*
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo72(void) {
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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USART_Printf_Init(115200);
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RCC->CTLR |= ((uint32_t) RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do {
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET) {
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value = HSE_FrequencyCheck();
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HSEStatus = (uint32_t) 0x00;
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#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
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if (value == 32) {
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HSEStatus = (uint32_t) 0x01;
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}
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#else
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if ((value >= 3) && (value <= 25)) {
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HSEStatus = (uint32_t) 0x01;
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}
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#endif
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} else {
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HSEStatus = (uint32_t) 0x00;
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}
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if (HSEStatus == (uint32_t) 0x01) {
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
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RCC_PLLMULL));
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RCC->CFGR0 |= (uint32_t) (RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL9);
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t) RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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} else {
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EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t) RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t) RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t) RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
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RCC_PLLMULL));
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RCC->CFGR0 |= (uint32_t) (RCC_PLLSRC_HSI_Div2 | RCC_PLLXTPRE_HSE
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| RCC_PLLMULL9);
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t) ((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t) RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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}
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/*********************************************************************
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* @fn main
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*
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* @brief Main program.
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*
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* @return none
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*/
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int main(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure={0};
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
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SetSysClockTo72();
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USART_Printf_Init(115200);
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SystemCoreClockUpdate();
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printf("SystemClk:%d\r\n",SystemCoreClock);
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printf("HSE value %02d\r\n", value);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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/* MCO Output GPIOA 8 */
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RCC_MCOConfig( RCC_MCO_HSE );
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while(1);
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}
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