21 lines
1.7 KiB
Markdown
21 lines
1.7 KiB
Markdown
# WCH RISC-V UF2 Bootloader
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- Triggered by a double reset within 0.5 seconds (like Adafruit bootloaders)
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- Needs usage of `R16_BKP_DATAR10`
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- Write 0x4170 ('Ap') to boot into the application immediately without delay
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- Write 0x624c ('bL') to unconditionally enter the bootloader
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- Fits in $\leq$ 4096 bytes
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- Tested and built with MounRiver GCC V1.91
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- Code size is improved through use of "XW" instructions, which are not upstream
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- Supports USBD peripheral *only* (i.e. not USBFS)
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- USBD and USBFS are completely different, and the QFN28 package (which is available in largest quantities on LCSC) only bonds out USBD
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- Runs off of internal 8 MHz oscillator (despite stability concerns)
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- The HSI oscillator's tolerance (-1.0% to +1.6%) is well outside of the range specified for USB full speed ($\pm$ 0.25%), but it seems to work in practice n=1 ¯\\\_(ツ)\_/¯
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- Should work across most of the CH32V2xx and CH32V3xx family with appropriate changes to hardcoded constants.
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- Allows both download to flash and to SRAM with the "not main flash" flag (this is how the RP2040 bootrom works)
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- Flash download address must be 08xxxxxx (i.e. not starting at 0)
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- SRAM download address must be 20xxxxxx
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- The entire size of the SRAM can be used, as USBD contains its own buffer memory independent of the main SRAM
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- Auto-reboot on complete download, _but_ **only** works if the download is sufficiently small. Larger downloads will of course still flash, but they will not trigger auto-reboot and a manual reboot will be required.
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- Lots of nasty code golfing tricks -- see comments in [bootloader.c](https://github.com/ArcaneNibble/wch-uf2/blob/main/bootloader.c)
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